CN1291069C - 微细间距倒装焊凸点电镀制备方法 - Google Patents

微细间距倒装焊凸点电镀制备方法 Download PDF

Info

Publication number
CN1291069C
CN1291069C CNB031406564A CN03140656A CN1291069C CN 1291069 C CN1291069 C CN 1291069C CN B031406564 A CNB031406564 A CN B031406564A CN 03140656 A CN03140656 A CN 03140656A CN 1291069 C CN1291069 C CN 1291069C
Authority
CN
China
Prior art keywords
course
key
salient point
technology
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB031406564A
Other languages
English (en)
Other versions
CN1552951A (zh
Inventor
陈正豪
肖国伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hong Kong University of Science and Technology HKUST
Original Assignee
Hong Kong University of Science and Technology HKUST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hong Kong University of Science and Technology HKUST filed Critical Hong Kong University of Science and Technology HKUST
Priority to CNB031406564A priority Critical patent/CN1291069C/zh
Priority to US10/854,174 priority patent/US7199036B2/en
Publication of CN1552951A publication Critical patent/CN1552951A/zh
Priority to HK05103510A priority patent/HK1070927A1/xx
Application granted granted Critical
Publication of CN1291069C publication Critical patent/CN1291069C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供了一系列新工艺用以通过电镀方法，制备可用于半导体封装，具有微细间距、良好可靠性的焊球。本发明所采用的新工艺技术可适用于不同组分的电镀铅-锡合金焊料、无铅的锡基焊料(如：铜-锡、锡-铜-银、锡-银、锡-铋合金)等。其工艺能够满足焊球边间距50微米以上，焊球直径在50至300微米的需求。在本发明中，通过采用凸点回流控制层，避免了工艺过程中焊料的损失，从而能够制备微细间距和高可靠性焊球。通过对关键工艺和电镀金属层的控制，以调整电镀层微观结构，本发明能够制备用于倒装焊封装的高可靠性焊球。本发明同时应用特殊设计涂覆光胶构件和光刻工艺，以满足微细间距电镀凸点的工艺制备要求。

Description

微细间距倒装焊凸点电镀制备方法
技术领域
本发明与电子封装有关，是一种使用于半导体工艺过程中，在晶片或芯片上制备倒装焊凸点焊球的技术(electroplated solder bumpingtechnology for flip-chip)。
本发明与电子封装有关，是一种使用于半导体工艺过程中，在晶片或芯片上制备倒装焊凸点焊球的技术。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化、高性能、高可靠性方向发展。而集成电路封装不仅直接影响着集成电路、电子模块乃至整机的性能，而且还制约着整个电子***的小型化、低成本和可靠性。在集成电路芯片尺寸逐步缩小，集成度不断提高的情况下，电子工业对集成电路封装技术的提出了越来越高的要求。
倒装焊技术是通过在芯片表面形成的焊球，使芯片翻转与底板形成连接，从而减小封装尺寸，满足电子产品的高性能(如高速、高频、更小的引脚)、小外形的要求，使产品具有很好的电学性能和传热性能。在60年代IBM公司首先开发了倒装焊技术和可控塌陷凸点(C4)技术，其中凸点制备技术是利用金属掩膜蒸发工艺完成的，由于成本很高、工艺复杂，这一技术的应用受到很大的限制。在凸点倒装焊技术中，凸点是焊料通过一定工艺沉积在芯片互连金属层上，经过一定温度回流形成的金属焊球。在焊球下有防塌陷金属层，以保证焊料在回流时不会流动塌陷在芯片表面。
目前焊球的制备技术有许多种，包括金属掩膜蒸发、电镀凸点技术、激光植球技术、模板印刷技术等。倒装焊凸点主要结构如图1所示。其中，晶片1在凸点制备工艺前，以完成互连金属层3和钝化层2工艺。电镀凸点技术一般使用蒸发或溅射工艺，首先在晶片1表面沉积一金属层6，作为电镀时导电层和凸点下金属层。然后，使用光刻胶工艺形成电镀掩膜和电镀图形，在焊料电镀液中通过电镀工艺完成金属层5和焊料的沉积。最后，去除光刻胶和金属层，在一定温度下焊料回流形成焊球4。
在电镀凸点技术中，焊球下防塌陷金属层、光刻工艺、电镀工艺和金属层刻蚀是决定凸点焊球质量的关键。光刻胶的厚度和显影后图形的质量会影响焊球的均匀性和可靠性，差的光刻工艺会导致焊球之间的搭桥现象，使焊点短路和器件失效。在电镀完成后，金属层刻蚀及焊球下防塌陷层形成时，化学刻蚀工艺通常会影响焊料，导致焊料流失，影响焊球均匀性和质量。同时，刻蚀中经常出现的残余金属，会导致焊料在回流中塌陷，影响焊球形状很均匀性，当焊点间距微小时，造成焊点短路。
发明内容
本发明采取了一系列新工艺方法，使晶片上焊球制备工艺易于完成，提高焊球均匀性，减小焊球间距，降低焊球中孔洞率，提高工艺成品率和焊球的可靠性。本发明采用的新工艺技术适用于不同组分的电镀铅-锡合金焊料、无铅的锡基焊料(如：铜-锡、锡-铜-银、锡-银、锡-铋合金)等。
本发明是在晶片集成电路半导体前工序加工工艺后，在钝化开孔处金属层上，完成可用于倒装焊技术的焊球制备的系列工艺。本发明适用于并能够实现焊球边间距50微米以上，焊球直径在50微米至300微米的工艺需求。
即本发明提出一种可用于半导体封装的、制备在晶片上钝化层开孔处互连金属层上的焊球的方法，包括以下步骤：
a)在晶片表面沉积作为凸点下金属层；
b)在凸点下金属层上涂覆凸点回流控制层；
c)运用半导体光刻技术或浮脱工艺，形成凸点回流控制层上的图形，以在金属互连层上形成用于露出凸点下金属层的开孔；
d)在凸点回流控制层上制备一个绕开孔周围覆盖的电镀掩膜用厚光胶；
e)在开孔处进行电镀，形成凸点下金属层上的电镀铜层；
f)在电镀铜层进行焊料形成的电镀工艺：
g)除去电镀掩膜用厚光胶，根据焊料成分决定回流温度曲线和时间，进行回流工艺，从而焊料能够形成焊球；
h)除去凸点回流控制层；
i)刻蚀去除部分凸点下金属层。
当凸点回流控制层为有机薄膜时，采用半导体光刻技术以形成凸点回流控制层上的图形；而当凸点回流控制层为金属薄层时，采用浮脱工艺形成凸点回流控制层上的图形。
本发明所采用的主要技术、方法和设计包括有：
1.通过溅射或者蒸发工艺，在晶片表面形成金属层，金属材料为钛、钛-钨合金、铜、镍等。然后，在金属层上制备一层薄膜，其材料选择上，必须使焊料不能在其表面粘附，如有机薄膜或不粘焊料的其他金属(钛、钨、钛-钨、铝、铝合金)。本发明称该薄膜层为凸点回流控制层(Bump-Reflow-Control Layer)。在其厚度以不影响后续工艺为准，一般在100纳米至1500纳米之间。运用半导体光刻工艺，在需要制备焊球的位置开出合适尺寸孔洞，使金属层露出。
2.当在晶片上旋转涂覆光刻胶时，采用一个特殊设计的构件，如图2所示，其加载在晶片1上的密封盖结构7，在光胶涂覆过程中，保证构件腔体8密闭，使涂覆的光刻胶达到焊料电镀工艺需要的高度。光胶厚度在50微米至175微米之间。
3.在光刻胶涂覆、显影和曝光过程，采用一系列特殊工艺过程，在使用不同光刻胶时，以满足焊料电镀工艺对光胶的要求。同时，保证工艺能够满足焊球中心间距在100微米至400微米的要求。
4.在电镀工艺中，通过控制有关工艺参数，使电镀铜层的晶粒尺寸尽可能减小在2微米内，表面均匀性控制在500纳米以内。这样能够通过工艺，减小形成较厚金属间化合物，影响焊球的可靠性。
5.在焊料电镀工艺完成后，去除光刻胶，但保留前面形成的有机薄膜。然后，根据焊料特性在一定温度曲线下，直接进行回流形成焊球。由于凸点回流控制层存在，焊料回流时不会塌陷在晶片表面，能够形成设计所需的球形。
6.回流后去除有机薄膜，然后刻蚀去金属层至原来晶片的钝化层完全露出。由于焊球已经过回流，上述工艺不会造成焊料损失，影响焊球均匀性和可靠性。
7.在上述工艺过程开始时，根据晶片集成电路互连金属线路情况，按照工艺过程需要，设计相应的光刻工艺掩膜版。掩膜版的设计参数要与相关工艺要求、焊球尺寸相匹配。
针对本发明所采用的技术、方法和设计，现使用有关材料举一实施例并结合附图，详细说明工艺过程。所使用附图不是按照为正常比例绘制。
附图简要说明：
图1为倒装焊凸点截面示意图。
图2为密封晶片涂胶器件结构示意图。
图3为晶片上金属溅射沉积钛-钨合金和铜金属层工艺截面示意图。
图4为使用有机薄膜制备凸点回流控制层(Bump-Reflow-ControlLayer)的工艺过程截面示意图，图4(a)为有机薄膜沉积后截面示意图，图4(b)为有机薄膜刻蚀后截面示意图。
图5为另一种采用金属层和浮脱工艺(Lift-off process)制备凸点回流控制层截面示意图，图5(a)为光胶工艺后截面示意图，图5(b)为凸点回流控制层沉积后截面示意图。图5(c)为浮脱工艺后截面示意图。
图6为光胶曝光、显影、烘干后截面图。
图7为电镀工艺过程截面示意图，图7(a)为厚光胶工艺完成后截面示意图，图7(b)为焊料沉积后截面示意图。
图8为电镀铜时电流密度和镀层表面均匀性的关系曲线。
图9为焊料经过回流工艺后形成焊球的截面图，图9(a)为去除厚光胶后截面示意图，图9(b)为回流工艺形成焊球的截面示意图。
图10为去除凸点回流控制层及金属层的工艺过程截面图，图10(a)为去除凸点回流控制层后截面示意图，图10(b)为去除电镀导电金属层后截面示意图。
图中：
1-晶片                          2-钝化层
3-互连金属层(铝或铜)            4-凸点焊球
5-电镀铜层                      6-凸点下金属层
7-涂覆光胶密封盖                8-密封空间
9-凸点回流控制层(有机层)        10-凸点回流控制层开孔处
11-钝化层开孔处                 12-浮脱工艺中光胶
13-凸点回流控制层(金属)         14-电镀掩膜用厚光胶
15-电镀焊料(未回流)
具体实施方式
如图2所示，当在晶片上旋转涂覆光刻胶时，采用一个特殊设计的构件，其加载在晶片1上的密封盖结构7，在光胶涂覆过程中，保证构件腔体8密闭，使涂覆的光刻胶达到焊料电镀工艺需要的高度。光胶厚度在50微米至175微米之间。
如图3所示，在晶片1上已完成了的互连金属化3(铝引线)和钝化层2。通过溅射工艺，钛-钨合金首先沉积在晶片1表面，其厚度在50纳米至120纳米之间。然后，铜金属层溅射沉积在钛-钨合金上，其厚度为200纳米至600纳米之间，形成电镀导电层和凸点下金属层6。为保证金属层6中的钛-钨合金与铜金属层之间良好的粘合性和电学性能，两种金属溅射需要在同一稳定真空环境下溅射完成。
图4描述了采用有机薄膜制备凸点回流控制层9(Bump-Reflow-Control Layer)的工艺过程。在晶片1上使用旋转涂覆的方法，把一种可感光的聚酰亚胺材料沉积下来，形成150纳米以下的薄膜层9。运用半导体光刻技术，在金属互连层开孔11上，刻蚀去聚酰亚胺薄膜层9，露出凸点下金属层6。其刻蚀开孔10直径要大于钝化层开孔11直径的10％～35％。需注意的是该有机薄膜9材料的选择，需能够承受焊料回流时的温度，保证在焊料回流工艺后，该薄膜层9能够刻蚀除去。如图4(b)所示，钝化层开孔11直径为80微米，聚酰亚胺薄膜层开孔10直径为110微米。光刻需要的掩膜版按照上述参数设计完成。
图5是另一种替代图4的方法，采用金属层和浮脱工艺(Lift-offprocess)制备凸点回流控制层6的过程。首先，按照薄膜层开孔图形和尺寸，在晶片1的上完成光刻胶12工艺，如图5(a)所示。光刻掩膜版按照有关参数制作。通过溅射工艺沉积30纳米至50纳米钛-钨合金层13在晶片1上(如图5(b))。使用浮脱工艺形成所需图形(如图5(c))。其中，该钛-钨金属层(13)开孔直径为110微米。
在凸点回流控制层制备完成后，即图4(b)或图5(c)之后，需要进行电镀中使用的光胶制备过程。为获得设计的焊球高度，光刻胶需要达到一定厚度要求。本发明在光刻胶旋转涂覆过程中，使用了图2所示设计器件。该设计使用密闭构件7，能够确保在旋转涂覆光刻胶过程中，晶片1和光刻胶处于一个封闭空间8中。当晶片旋转时，构件和其密闭空间的空气等速旋转，使光刻胶中成分不会大量挥发，从而获得足够厚度的胶层。
图6显示了光胶14曝光、显影、烘干后的图形结构。在此过程中，为保证光胶14图形质量和厚度，本发明采用了如下特殊工艺：
1)光胶涂覆后，在曝光前预烘工艺中，使用平板电炉在45～60摄氏度进行前预烘，时间一般为4～10分钟；2
)在20～25摄氏度环境放置30～60分钟；
3)按照正常预烘工艺，在110摄氏度进行预烘；
4)进行曝光和显影；
5)显影完成后，在50～60摄氏度平板电炉上烘干20～45分钟。
这里采用的是正胶材料。如需要增加胶层厚度，可以重复上述工艺。在光胶掩膜版设计中，光胶开孔处直径需小于凸点回流控制层开孔直径，以保证工艺质量，一般为5％左右。如图6中，光胶开孔处直径是100微米。
图7描述了电镀工艺过程。通过控制有关工艺参数，使电镀铜层5的晶粒尺寸尽可能减小在2微米内，表面均匀性控制在500纳米以内，消除电镀层中孔洞的形成。这样在使用过程中，能够减小焊球中形成较厚金属间化合物，增强焊球机械强度，提高焊球的可靠性。电镀铜层5厚度在5～25微米之间，以使焊球获得良好机械强度。铜层电镀完成后，进行焊料15的电镀工艺。
图8显示了电镀铜时电流密度和镀层表面均匀性的关系。其表面均匀性用算术平均值和均方根值描述。当使用饱和硫酸铜电镀液，在20～25摄氏度下，镀层表面均匀性会随着电镀电流密度增加而增加。
当焊料15电镀完成后，将光胶除去，如图9(a)所示。如图9(b)所示，根据焊料成分决定回流温度曲线和时间，进行回流工艺，由于凸点回流控制层13/9的存在，焊料能够形成焊球4，而不会塌陷在晶片1表面。
图10描述了回流完成后，去除凸点回流控制层13/9(聚酰亚胺薄膜或钛-钨层)，如图10(a)所示。然后，刻蚀去除溅射铜薄膜和底部的钛-钨薄膜6，如图10(b)所示。由于凸点回流控制层13/9的存在，电镀焊料15已经完成回流工艺形成焊球4，这样就避免了在焊料回流之前刻蚀这些凸点下金属膜层6，所导致的焊料损失和腐蚀，影响焊球质量和可靠性。至此，在晶片1上制备焊球的工艺过程完成。

Claims (8)

1.一种可用于半导体封装的、制备在晶片上钝化层(2)开孔处互连金属层(3)上的焊球的方法，包括以下步骤：
a)在晶片(1)表面沉积作为凸点下金属层(6)；
b)在凸点下金属层(6)上涂覆凸点回流控制层(9，13)；
c)运用半导体光刻技术或浮脱工艺，形成凸点回流控制层(9，13)上的图形，以在金属互连层(3)上形成用于露出凸点下金属层(6)的开孔(10)；
d)在凸点回流控制层(9，13)上制备一个绕开孔(10)周围覆盖的电镀掩膜用厚光胶(14)；
e)在开孔(10)处进行电镀，形成凸点下金属层(6)上的电镀铜层(5)；
f)在电镀铜层(5)进行焊料(15)形成的电镀工艺；
g)除去电镀掩膜用厚光胶(14)，根据焊料成分决定回流温度曲线和时间，进行回流工艺，从而焊料能够形成焊球(4)；
h)除去凸点回流控制层(9，13)；
i)刻蚀去除部分凸点下金属层(6)。
2.根据权利要求1所述的方法，其特征在于，凸点回流控制层(9，13)是一有机薄膜或金属薄膜，其材料与焊料在回流过程中不相粘附。
3.根据权利要求2所述的方法，其特征在于，凸点回流控制层(9，13)是在凸点下金属层沉积之后制备，凸点回流控制层厚度为100纳米至1500纳米之间。
4.根据权利要求1所述的方法，其特征在于，光刻工艺的掩膜版设计中，凸点回流控制层开孔尺寸大于钝化层开孔尺寸的10％～35％。
5.根据权利要求1所述的方法，其特征在于，当凸点回流控制层(9)为有机薄膜时，采用半导体光刻技术以形成凸点回流控制层上的图形；而当凸点回流控制层(13)为金属薄层时，采用浮脱工艺形成凸点回流控制层上的图形。
6.根据权利要求1所述的方法，其特征在于，电镀用厚光胶开孔(10)尺寸需小于凸点回流控制层开孔直径3～7％。
7.根据权利要求1所述的方法，其特征在于，当涂覆光刻胶时，使用一个密封构件(7)，使晶片和光刻胶处于一个封闭空间中，晶片旋转时，密封构件和所封闭空气与晶片等速旋转。
8.根据权利要求1所述的方法，其特征在于，一厚光胶工艺被采用，以获得厚度在50～175微米光胶层，其工艺步骤是：
a)在高温预烘前，使用平板电炉在低温下进行前预烘，温度为45～60摄氏度，时间为4～10分钟；
b)在20～25摄氏度环境放置30～60分钟；
c)在110摄氏度进行预烘，然后曝光和显影；
d)在50～60摄氏度平板电炉上烘干20～45分钟。
CNB031406564A 2003-05-31 2003-05-31 微细间距倒装焊凸点电镀制备方法 Expired - Lifetime CN1291069C (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CNB031406564A CN1291069C (zh) 2003-05-31 2003-05-31 微细间距倒装焊凸点电镀制备方法
US10/854,174 US7199036B2 (en) 2003-05-31 2004-05-27 Under-bump metallization layers and electroplated solder bumping technology for flip-chip
HK05103510A HK1070927A1 (en) 2003-05-31 2005-04-25 Method of preparing fine-pitch electroplated solder bumpoing for flip-chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB031406564A CN1291069C (zh) 2003-05-31 2003-05-31 微细间距倒装焊凸点电镀制备方法

Publications (2)

Publication Number Publication Date
CN1552951A CN1552951A (zh) 2004-12-08
CN1291069C true CN1291069C (zh) 2006-12-20

Family

ID=33752647

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031406564A Expired - Lifetime CN1291069C (zh) 2003-05-31 2003-05-31 微细间距倒装焊凸点电镀制备方法

Country Status (3)

Country Link
US (1) US7199036B2 (zh)
CN (1) CN1291069C (zh)
HK (1) HK1070927A1 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001063991A1 (fr) * 2000-02-25 2001-08-30 Ibiden Co., Ltd. Carte a circuits imprimes multicouche et procede de production d'une carte a circuits imprimes multicouche
EP1321980A4 (en) * 2000-09-25 2007-04-04 Ibiden Co Ltd SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD
AUPR451601A0 (en) * 2001-04-20 2001-05-24 Fawcett, Alan John Method and apparatus for the hardening of photopolymer plates
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
DE102004047730B4 (de) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen
TWI240979B (en) * 2004-10-28 2005-10-01 Advanced Semiconductor Eng Bumping process
JP2006173460A (ja) * 2004-12-17 2006-06-29 Renesas Technology Corp 半導体装置の製造方法
TWI246733B (en) * 2005-05-04 2006-01-01 Siliconware Precision Industries Co Ltd Fabrication method of under bump metallurgy structure
TWI295549B (en) * 2005-05-09 2008-04-01 Phoenix Prec Technology Corp Solder ball structure of circuit board and method for fabricating same
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
CN100359679C (zh) * 2005-09-27 2008-01-02 天津工业大学 倒装焊接结构及制作方法
JP2007220959A (ja) * 2006-02-17 2007-08-30 Fujitsu Ltd 半導体装置及びその製造方法
JP2007234754A (ja) * 2006-02-28 2007-09-13 Fujitsu Ltd レジストパターン形成方法及びレジストパターン形成装置
JP5050384B2 (ja) * 2006-03-31 2012-10-17 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US8844826B2 (en) * 2006-07-10 2014-09-30 Nxp B.V. Integrated circuit transponder, method of producing an integrated circuit and method of producing a transponder
TWI343112B (en) * 2007-08-08 2011-06-01 Unimicron Technology Corp Package substrate having electrical connection structure and method for fabricating the same
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US20090127695A1 (en) * 2007-11-19 2009-05-21 Patrick Kim Surface mount package with enhanced strength solder joint
US8232655B2 (en) 2008-01-03 2012-07-31 International Business Machines Corporation Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
JP5113544B2 (ja) * 2008-01-30 2013-01-09 新光電気工業株式会社 配線基板の製造方法
KR100949021B1 (ko) 2008-02-19 2010-03-23 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
DE102008014577B3 (de) * 2008-03-14 2009-07-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer Lotmetallisierung
US9324611B2 (en) * 2008-04-03 2016-04-26 Micron Technology, Inc. Corrosion resistant via connections in semiconductor substrates and methods of making same
JP4987823B2 (ja) * 2008-08-29 2012-07-25 株式会社東芝 半導体装置
JP5120342B2 (ja) * 2009-06-18 2013-01-16 ソニー株式会社 半導体パッケージの製造方法
JP5357784B2 (ja) * 2010-01-05 2013-12-04 パナソニック株式会社 半導体装置及びその製造方法
JP5459127B2 (ja) * 2010-07-20 2014-04-02 千住金属工業株式会社 機能部品の製造方法及び機能部品
CN102364702B (zh) * 2011-11-11 2012-11-14 保定天威集团有限公司 一种太阳能电池制备工艺中安装汇流排工序的方法
US9418937B2 (en) 2011-12-09 2016-08-16 Infineon Technologies Ag Integrated circuit and method of forming an integrated circuit
US9192048B1 (en) * 2014-06-20 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Bonding pad for printed circuit board and semiconductor chip package using same
CN104201118A (zh) * 2014-08-26 2014-12-10 南通富士通微电子股份有限公司 芯片级封装方法
KR102462504B1 (ko) 2015-11-19 2022-11-02 삼성전자주식회사 범프를 갖는 반도체 소자 및 그 형성 방법
WO2019123826A1 (ja) * 2017-12-19 2019-06-27 Ｊｘ金属株式会社 半導体ウェハ、及びその製造方法
CN110304604B (zh) * 2019-06-18 2023-04-28 上海应用技术大学 一种mems传感器的封装方法
CN110676175A (zh) * 2019-09-24 2020-01-10 浙江集迈科微电子有限公司 一种键合工艺制作大锡球的方法
CN112045329B (zh) * 2020-09-07 2022-03-11 中国电子科技集团公司第二十四研究所 一种金属基板上植球的倒装焊工艺方法
CN117187926B (zh) * 2023-11-03 2024-02-13 合肥矽迈微电子科技有限公司 一种封装体电镀用滚筒结构、电镀装置及方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869870B2 (en) * 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
US6258703B1 (en) 1999-07-21 2001-07-10 International Business Machines Corporation Reflow of low melt solder tip C4's
US6570251B1 (en) 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
KR100311975B1 (ko) * 1999-12-16 2001-10-17 윤종용 반도체소자 및 그 제조방법
US6521996B1 (en) * 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
US6881609B2 (en) * 2001-09-07 2005-04-19 Peter C. Salmon Component connections using bumps and wells
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
TWI243439B (en) * 2001-12-31 2005-11-11 Advanced Semiconductor Eng Bumping process
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
US20040088855A1 (en) * 2002-11-11 2004-05-13 Salman Akram Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
US20040140475A1 (en) * 2003-01-21 2004-07-22 United Test & Assembly Center Limited 3D MEMS/MOEMS package
US6992001B1 (en) * 2003-05-08 2006-01-31 Kulicke And Soffa Industries, Inc. Screen print under-bump metalization (UBM) to produce low cost flip chip substrate

Also Published As

Publication number Publication date
HK1070927A1 (en) 2005-06-30
CN1552951A (zh) 2004-12-08
US20050014355A1 (en) 2005-01-20
US7199036B2 (en) 2007-04-03

Similar Documents

Publication Publication Date Title
CN1291069C (zh) 微细间距倒装焊凸点电镀制备方法
US7932169B2 (en) Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers
US20040040855A1 (en) Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages
US20060223313A1 (en) Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same
Koh et al. Copper pillar bump technology progress overview
TWI674635B (zh) 包含單元特定對齊及單元特定佈線之多晶粒封裝
US9721913B2 (en) Semiconductor package and method of manufacturing thereof
KR102650296B1 (ko) 범프 구조물을 갖는 반도체 디바이스 및 반도체 디바이스의 제조 방법
KR20150069492A (ko) 반도체 구조 및 그 제조 방법
JP2004207685A (ja) 無鉛ソルダバンプの製造方法
CN1956158A (zh) 焊料凸块的制造方法、中间结构
Töpper Wafer level chip scale packaging
TWI242866B (en) Process of forming lead-free bumps on electronic component
Orii et al. Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump
CN100350581C (zh) 整合打线及倒装封装的芯片结构及工艺
KR100834804B1 (ko) 금속 스터드 스택 또는 칼럼을 이용한 플립칩 접속방법 및전자회로기판
Wei et al. Ultra-precise low-cost surface planarization process for advanced packaging fabrications and die assembly: A survey of recent investigations on unit process applications and integrations
Orii et al. Advanced interconnect technologies in the era of cognitive computing
Arshad et al. Under bump metallurgy (UBM)-A technology review for flip chip packaging
CN1284207C (zh) 一种用于半导体封装的焊球的制备方法
TW423132B (en) Bumpless flip chip package and method for fabricating
Baumgartner et al. Printing solder paste in dry film-a low cost fine-pitch bumping technique
TWI353030B (en) Tin processing method for surfaces of copper pads
US8648466B2 (en) Method for producing a metallization having two multiple alternating metallization layers for at least one contact pad and semiconductor wafer having said metallization for at least one contact pad
CN2603508Y (zh) 芯片结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1070927

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20061220

CX01 Expiry of patent term