CN1286029C - Device for controlling interior storage of chip and its storage method - Google Patents
Device for controlling interior storage of chip and its storage method Download PDFInfo
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- CN1286029C CN1286029C CN 02129193 CN02129193A CN1286029C CN 1286029 C CN1286029 C CN 1286029C CN 02129193 CN02129193 CN 02129193 CN 02129193 A CN02129193 A CN 02129193A CN 1286029 C CN1286029 C CN 1286029C
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Abstract
The present invention relates to a device for controlling the interior storage of a chip and a storage method thereof, wherein the device comprises a multichannel data buffer storage control / state unit, a date RAM (random access memory) read-write control unit, a data storing RAM with double ports, a configuration RAM control unit and a configuration RAM array, wherein the data storing RAM adopts chained list type storage management; the method comprises that the multichannel data buffer storage control / state unit receives data operation command firstly; then, the data RAM read-write control unit carry out read-write operation for the data storage RAM with double ports according to the command and parameter information in the configuration RAM array; finally, corresponding configuration parameter information needs to be updated. The present invention can effectively utilize the limited storage space in the chip, increase the flexibility of practical application and support larger data flow. In addition, the present invention can also greatly increase the band width and the utilization rate of system bus under the condition of multiple speed rates and multichannel application environment.
Description
Technical field
The present invention relates to the computer communication technology field, relate in particular to a kind of control chip sheet internal storage system and storage means thereof.
Background technology
In communication facilities, need between physical port and data transmission bus to be provided for that buffer memory receives or the hyperchannel control chip of sending direction data, as shown in Figure 1, and to reduce data service to the application of data transmission bus with take number of times, the effective bandwidth of utilizing.The solution of existing hyperchannel control chip sheet stored has two kinds usually: a kind of is the storage space that is fixed as the identical size of each channel allocation in a sheet in the metadata cache, and the indiscriminate use of each passage belongs between separately memory block; Another kind is to be respectively each physical port to use a data RAM, determines separately data RAM capacity according to fixed port speed.
Though it is fairly simple to be fixed as the sheet stored method circuit structure of each channel allocation storage space, realize and verify all being easy to, but owing to lost flexibly the ability that flow according to logical channel distributes the priority that buffer memory and bus transmit in the sheet, can't reach the maximum efficiency that hyperchannel is handled with buffer memory in the less sheet, especially under the situation that the buffer memory and the bus of the multi-channel data of realizing different rates transmits, performance difference is very big.And, the priority control that does not provide in the sheet stored method of the identical big or small storage space of each channel allocation at each passage is provided in the metadata cache in a sheet, be difficult on the basis of limited size data buffer memory in the sheet, adapt to multiple speed environment of applications preferably and satisfy the requirements at the higher level of the passage control of different flow.
And another kind all disposes the sheet stored method that a data RAM is made buffer memory separately for each port, though can use the port of different rates, can't adapt to the sort of multichannel application, and for example, the channelizing of single port is used.And can't between passage or port, allocate the size of buffer memory arbitrarily with the change of applied environment.In the back end design of control chip, increase the area of the Bist circuit of being RAM, reduce the allowance of rear end wiring.
Summary of the invention
The purpose of this invention is to provide a kind of control chip sheet internal storage system and storage means thereof, reception and sending direction data are at the buffer memory of control chip inside in the realization computer communication technology, reduce PCI (data transmission bus) number of operations, improve PCI sudden transmission length, thereby improve the utilization ratio of pci bus.
The object of the present invention is achieved like this: a kind of control chip sheet internal storage system comprises:
Multi-channel data buffer memory control/state cell: provide the data-interface of control chip and each passage, the synchronous operation between coordination data RAM read-write control unit and configuration RAM control module, maintenance channel storaging state information;
Data RAM (random access memory) read-write control unit: finish the basic read-write capability of dual-port data storage RAM, inputoutput data;
Dual-port data storage RAM: each passage is used for the storage entity of storing data information;
Configuration RAM control module: finish the read-write control of all configuration array rams, and the real-time update of configuration array ram, output state information;
Configuration array ram: be used for the metadata cache control information of each passage of real-time storage.
Comprise a plurality of storage blocks among the described dual-port data storage RAM, each storage block is organized with the form of chained list, the corresponding block pointer of each storage block, and as a node in the chained list.
Also be provided with the information of the chained list of each storage block formation among the dual-port data storage RAM in the described configuration array ram.
Comprise in the described configuration array ram:
Block (piece) pointer RAM (BP_RAM):, write down each block pointer next block pointer pointed in each passage chained list by BP_Pointer (block pointer) addressing;
Double word and EOF counting RAM (DW_EOF_RAM):, be used for each passage of real time record in stored data volume of buffer memory and the quantity that has the data (being the data of last double word of Frame) of EOF by unique recording mechanism (being channel number) addressing of each logical channel;
Read pointer RAM (RP_RAM):, be used for the read pointer of each passage of real time record by the channel number addressing;
Write pointer RAM (WP_RAM):, be used for the write pointer of each passage of real time record by the channel number addressing;
Water gauge RAM (WM_RAM):, be used to offer the user and be written as the threshold value that each passage sets by the channel number addressing.
The passage storaging state information that described multi-channel data buffer memory control/state cell is safeguarded is: passage chained list status information, the passage chained list is meant the storage area of a linked list type structure of being distributed for passage in dual-port data storage RAM, passage chained list status information is used to indicate the take situation of channel data to this storage area.
Described passage chained list status information comprises:
The signal " Exist.EOF " of passage chain table status: also there is at least one EOF data in its ' nonzero value ' representative in the prepass chained list;
The signal " Beyond.LWM " of passage chain table status: the data of its ' nonzero value ' representative in the prepass chained list surpass low water gauge value, and low water gauge value is the minimum data value in this passage chained list;
The signal " Not.Null " of passage chain table status: the data that its ' nonzero value ' representative is worked as in the prepass chained list are not empty;
The signal " Is.Full " of passage chain table status: its ' nonzero value ' representative is filled up by data writing operation in the prepass chained list.
A kind of method of control chip sheet stored comprises:
A, multi-channel data buffer memory control/state cell receive the data operation commands of sending direction and receive direction;
B, data RAM read-write control unit carry out read-write operation according to the parameter information in data operation commands that receives and the configuration array ram to dual-port data storage RAM;
C, dual-port data storage RAM read-write operation finished after, by configuration RAM control module the parameter information in the configuration array ram is upgraded;
D, while multi-channel data buffer memory control/state cell be new tunnel chained list status information more.
Described step a comprises: the physical port side joint of multi-channel data buffer memory control/state cell is received the order of read data.
Described step b comprises:
B1, basis are sent the passage effective index signal and the channel number of the passage of read data order, read the read pointer value and the low water gauge Configuration Values of this passage in the configuration array ram;
B2, multi-channel data buffer memory control/state cell read data among the dual-port data storage RAM according to the read pointer value that reads and low water gauge value by the data RAM read-write control unit;
B3, the data that read are exported by multi-channel data buffer memory control/state cell.
Described step b2 comprises:
B21, judge whether the data volume in the passage chained list of this passage is lower than the water gauge value, if be lower than this value, execution in step b22 then, otherwise, execution in step b23;
B22, the request in this passage chained list, import data, and in this passage chain the input data after execution in step b21;
B23, the operation of read data of beginning promptly utilize the read pointer value to read data in this passage chained list of dual-port data storage RAM by the data RAM read-write control unit.
Described step c comprises:
C1, determine read pointer, and upgrade the read pointer information among the read pointer RAM of current configuration array ram by configuration RAM control module according to block pointer information;
C2, upgrade data value in the configuration array ram according to the data message of output, for the double word of configuration array ram and the quantitative value of the data that have EOF among the EOF counting RAM, then need to judge whether to change, if change, then this quantitative value is upgraded, otherwise, do not do to upgrade operation.
Described steps d comprises:
D1, judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist then the state of maintenance " Exist.EOF ", otherwise, the state that makes " Exist.EOF " is a null value, and wherein also there is at least one EOF data in ' nonzero value ' of passage chained list status signal " Exist.EOF " representative in the prepass chained list;
D2, according to the read pointer value after upgrading and LWM (low water gauge) value of looking ahead, judge when the shared piece number of storage data in the storage chained list of prepass whether reduced to below the threshold value that low water gauge sets by the read data operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation, wherein the data of ' nonzero value ' of passage chained list status signal " Beyond.LWM " representative in the prepass chained list surpass low water gauge value;
D3, according to the read pointer value after upgrading, judge whether data all in the storage chained list of prepass are all run through by the read data operation, if then making " Not.Null " state of this passage is null value; Otherwise, keep " Not.Null " state, do not do any renewal operation, wherein ' nonzero value ' of passage chained list status signal " Not.Null " representative when the data in the prepass chained list be sky;
D4, automatically " Is.Full " state of this passage is updated to null value, wherein ' nonzero value ' of passage chained list status signal " Is.Full " representative is filled up by data writing operation in the prepass chained list.
Described step a comprises: the system bus side joint of multi-channel data buffer memory control/state cell is received the order of write data.
Described step b comprises:
B4, multi-channel data buffer memory control/state cell select to allow the passage chained list of write data according to the value of " Beyond.LWM " of each passage chain table status of inside, and definite channel number, and set up intermediateness at information in the configuration array ram of this passage, wherein the data of ' nonzero value ' of passage chained list status signal " Beyond.LWM " representative in the prepass chained list surpass low water gauge value;
B5, multi-channel data buffer memory control/state cell are according to the channel number of determining, the write pointer RAM, double word and the EOF that read in the configuration array ram by configuration RAM control module count RAM, water gauge RAM value;
Each value among the write pointer RAM that b6, basis read, double word and EOF counting RAM, the water gauge RAM is by data RAM read-write control unit write data in dual-port data storage RAM.
Described step b6 comprises:
B61, judge whether write full data in this passage chained list according to the data value among the threshold value among the water gauge RAM and double word and the EOF counting RAM, if, execution in step b62, otherwise, execution in step b63;
The data in this passage chained list are exported in b62, request, and after the output of the data in this passage chained list, execution in step b61;
B63, data writing operation of beginning are promptly according to the write data in dual-port data storage RAM of the write pointer value among the write pointer RAM, execution in step c.
Described step c comprises:
C3, determine write pointer according to block pointer information; Determine stored data value and the quantitative value that has the data of EOF among double word and the EOF counting RAM according to the data message that writes, quantitative value for the data that have EOF then needs to judge whether to change, if change, then upgrades this value, otherwise, do not do to upgrade operation;
C4, after each data writing operation is finished, the intermediateness of passing through to be set up is carried out the renewal of each value among write pointer and double word and the EOF counting RAM;
C5, when the repeatedly data writing operation of epicycle finishes, each parameter value in the above-mentioned intermediateness is written back in the current configuration array ram by configuration RAM control module;
Described steps d comprises:
D5, judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist, the state that then makes " Exist.EOF " is a nonzero value, otherwise, the state that keeps " Exist.EOF ", wherein also there is at least one EOF data in ' nonzero value ' of passage chained list status signal " Exist.EOF " representative in the prepass chained list;
D6, according to write pointer value after upgrading and the low water gauge value of looking ahead, judge when the shared piece number of storage data in the storage chained list of prepass whether be increased to more than the threshold value that low water gauge sets by data writing operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation;
D7, be nonzero value from " Not.Null " of this passage of command of execution state, wherein ' nonzero value ' of passage chained list status signal " Not.Null " representative when the data in the prepass chained list be sky;
D8, judge according to read pointer and write pointer value whether this passage chained list has write full data, if write full data, then making " Is.Full " state of this passage is nonzero value, otherwise, keep " Is.Full " state, do not do any operation, wherein ' nonzero value ' of passage chained list status signal " Is.Full " representative is filled up by data writing operation in the prepass chained list.
In the method for control chip sheet stored of the present invention: before execution in step b, also comprise:
E, multi-channel data buffer memory control/state cell carry out priority arbitration to receiving a plurality of data operation commands, determine the priority of each data operation commands;
F, according to the priority orders of determining respectively to each data operation commands execution in step b successively.
Described step e comprises:
E1, in the physical port side, be to determine priority level according to the port order, promptly believe the little port priority of port numbers formerly;
E2, in system's general line side, be the priority of determining each passage application according to the priority of each passage that sets in advance.
Described step f according to priority adopts stream line operation in proper order in a plurality of read data orders of physical port side, be after priority read data order has formerly been determined channel number by multi-channel data buffer memory control/state cell, priority after the read data order more successively by the definite channel number separately of multi-channel data buffer memory control/state cell.
By technique scheme as can be seen, the present invention adopts the dynamic chain tabular form storage to data, and finite storage space in the sheet that made more efficient use has increased the dirigibility of practical application.Adopt the streamline mechanism of physical port side, can support bigger data traffic.In addition, the control of the priority of system bus side is visited, and can improve the bandwidth availability ratio of system bus under the multichannel applied environment of many speed greatly.
Description of drawings
Fig. 1 is the applied environment synoptic diagram of control chip;
Fig. 2 is the structural drawing of control chip sheet internal storage system;
Fig. 3 is the control table of passage priority;
Fig. 4 is the process flow diagram of reading data course of the method for control chip sheet stored;
Fig. 5 is the process flow diagram of write data process of the method for control chip sheet stored.
Embodiment
Control chip sheet internal storage system of the present invention as shown in Figure 2, its structure comprises:
Multi-channel data buffer memory control/state cell (being M_Buffer_Ctrl/Status_Unit) 1: the data-interface of control chip and each passage is provided, comprises physical port side interface 7 and system bus side interface 6; And be used for the synchronous operation between coordination data RAM read-write control unit and configuration RAM control module, the maintenance channel storaging state information is promptly being safeguarded the passage chained list status information of each passage; The passage chained list is meant the storage area of a linked list type structure of being distributed for passage in dual-port data storage RAM, passage chained list status information is used to indicate the take situation of channel data to this storage area;
Described passage chained list status information comprises:
The signal " Exist.EOF " of passage chain table status: also there is at least one EOF data in its ' nonzero value ' representative in the prepass chained list;
The signal " Beyond.LWM " of passage chain table status: the data of its ' nonzero value ' representative in the prepass chained list surpass low water gauge value, and low water gauge value is the minimum data value in this passage chained list;
The signal " Not.Null " of passage chain table status: the data that its ' nonzero value ' representative is worked as in the prepass chained list are not empty;
The signal " Is.Full " of passage chain table status: its ' nonzero value ' representative is filled up by data writing operation in the prepass chained list.
Data RAM (random access memory) read-write control unit (being Cfg_RAM_Ctrl_Unit) 2: finish the basic read-write capability of dual-port data storage RAM, inputoutput data;
Dual-port data storage RAM3: i.e. buffer memory in the sheet, for each passage is used for the storage entity of storing data information, adopted the dual-port data RAM of two 16KB among the present invention; And from logic the data RAM of 16KB being resolved into 1024 Block (piece), each Block is as the basic unit of storage of chained list, carry out addressing for each Block sets up a Block pointer (Block_Pointer), provide a Block pointer RAM (being BP_RAM) to store the corresponding next Block pointer of each Block pointer on the hardware; Realize sharing the purpose of buffer memory in the sheet among the present invention for one section passage chained list of each channel allocation, the size of the storage space of every section passage chained list distribution is disposed as required by the user, also can be configured automatically for control chip;
Configuration RAM control module (being Data_RAM_Ctrl) 4: finish the read-write control of all configuration array rams, and the real-time update of configuration array ram, output state information;
Configuration array ram 5: be used for the metadata cache control information of each passage of real-time storage, further comprise in the configuration array ram:
Block (piece) pointer RAM (BP_RAM):, write down each BP_Pointer next BP_Pointer pointed in each passage chained list by BP_Pointer (block pointer) addressing;
Double word and EOF counting RAM (DW_EOF_RAM):, be used for each passage of real time record in stored data volume of buffer memory and the quantity that has the data (being the data of last double word of Frame) of EOF by unique recording mechanism (being channel number) addressing of each logical channel;
Read pointer RAM (RP_RAM): by the channel number addressing, be used for the read pointer of each passage of real time record, be convenient to reading to data in each passage chained list of dual-port data storage RAM;
Write pointer RAM (WP_RAM): by the channel number addressing, be used for the write pointer of each passage of real time record, be convenient to write data in each the passage chained list in dual-port storage RAM;
Water gauge RAM (WM_RAM):, be used to offer the user and be written as the threshold value that each passage sets by the channel number addressing; Based on both transmit and receive direction, application process to this threshold value is similar, and basic role is: when the shared Block of data has surpassed threshold value in the passage chained list, and the operation of request output data, when being lower than threshold value, request input data manipulation; At receive direction, can also set a Flow Control threshold value, when the data of receiving surpass threshold value, the communication far-end is carried out Flow Control, when being lower than this threshold value, then remove Flow Control; Usually at receive direction, the water gauge of this expression threshold value is called floodmark (High Water Mark, HMW), the meaning of expressing directly perceived is that the input data of physical port wing passage have surpassed local current Data Receiving ability and make and grasp a threshold value for the data in the buffer memory of its distribution, need control importing data manipulation; At sending direction, this threshold value is called low water gauge (Low Water Mark, LWM), the meaning directly perceived of expression is that the data output of physical port side has surpassed local current data transmission capabilities and makes to the data in the buffer memory of its distribution are lower than a threshold value, needs the output of control data; In application, any water gauge all has control action to the physical port side and the system bus side of data buffer area.
M_Buffer_Ctrl/Status_Unit is a kernel control module in the said apparatus, and the data that can handle simultaneously from physical port side interface and system bus side interface transmit task; The method of control chip sheet stored of the present invention is:
When signal that the request msg of certain passage of receiving the physical port side interface sends, M_Buffer_Ctrl/Status_Unit allows according to the related channel program chain table status of this passage or forbids this secondary data request; Under request of data enabled condition, by Cfg_RAM_Ctrl_Unit from the configuration array ram relevant configuration information of reading this passage; Output to the physical port side interface according to associated pointers information by Data_RAM_Ctrl reads this passage from data RAM data then, upgrade the configuration information of respective channel chain table status and passage, and by Cfg_RAM_Ctrl_Unit write-back configuration array ram, a secondary data of finishing the physical port side transmits, i.e. a read data flow process;
When the data sending request signal of certain passage of receiving the system bus side interface, M_Buffer_Ctrl/Status_Unit reads this passage by Cfg_RAM_Ctrl_Unit from the configuration array ram relevant configuration information, by Data_RAM_Ctrl this channel data is written to the relevant position of dual-port data storage RAM then from the system bus interface side according to associated pointers information, upgrade the configuration information of corresponding passage chain table status and passage, and by Cfg_RAM_Ctrl_Unit write-back configuration array ram, a secondary data of finishing the system bus side transmits, i.e. a write data flow process.
Below with regard to the situation of single passage, the detailed description of carrying out read data flow process and write data flow process; Wherein, the read data flow process of single logical channel is that example describes with the reading data course of physical port side, and as shown in Figure 4, this process specifically comprises:
Step 10: the physical port side joint of multi-channel data buffer memory control/state cell is received the order of read data;
Step 11:, read the read pointer value and the low water gauge Configuration Values of this passage in the configuration array ram according to the passage effective index signal and the channel number of the passage that sends the read data order;
Multi-channel data buffer memory control/state cell goes out the passage effective index signal " ch_id_vld " and the channel number " ch_id " of the passage of a current request for data by priority arbitration, M_Buffer_Ctrl/Status_Unit according to channel number " ch_id ", initiate to read RP_RAM and LWM_RAM operation, read pointer value that the passage chained list of this passage of looking ahead is current and low water gauge Configuration Values by Cfg_RAM_Ctrl_Unit;
Step 12: multi-channel data buffer memory control/state cell reads data among the dual-port data storage RAM according to the read pointer value that reads and low water gauge value by the data RAM read-write control unit;
Step 121: judge whether the data volume in the passage chained list of this passage is lower than the water gauge value, if be lower than this value, then execution in step 122, otherwise, execution in step 123;
The physical port side will provide request of data useful signal " data_req_vld " and Is.SOF (the SOF data application of physical port side) status signal, and will be invalid as " data_req_vld ", then terminating operation; M_Buffer_Ctrl/Status_Unit then carries out pretreatment operation based on internal state Exist.EOF, Beyond.LWM, the Not.Null status signal of the data buffer area of Is.SOF state and this passage to this request of data useful signal " data_req_vld "; As Exist.EOF, Beyond.LWM, when Not.Null is nonzero value, accept this read data application of this passage of physics port side, and continue this line of complete carrying out and operate, otherwise, do not accept this read data application from this passage of physical port side, this operation is terminated, and promptly can not continue to finish this operation of this passage;
Step 122: the request in this passage chained list, import data, and in this passage chain the input data after execution in step 121;
Step 123: beginning read data operation, promptly utilize the read pointer value to read data in this passage chained list of dual-port data storage RAM by the data RAM read-write control unit;
The operation that M_Buffer_Ctrl/Status_Unit reads data among the dual-port data storage RAM according to the read pointer value of looking ahead by the Data_RAM_Ctrl_Unit initiation, simultaneously initiate to read operation by Cfg_RAM_Ctrl_Unit to BP_RAM, and initiate to read the current double word count value among the DW_EOF_RAM and the operation of EOF count value according to the channel number of this passage when the next Block pointer value of the passage chained list current location of prepass according to the value of read pointer;
Step 13: the data that read are exported by multi-channel data buffer memory control/state cell;
M_Buffer_Ctrl/Status_Unit will be to physical port side output data response signal, and the data that read from metadata cache by Data_RAM_Ctrl_Unit of output;
Step 14: the parameter information in the configuration array ram is upgraded by configuration RAM control module;
Determine read pointer according to block pointer information, and by the read pointer information among the RP_RAM of the current configuration array ram of configuration RAM control module renewal; Judge promptly whether next read pointer strides the Block border, if transboundary, then determine new read pointer value according to the Block pointer in the configuration array ram, otherwise, only needing that read pointer is added one gets final product, initiate the operation of write-back RP_RAM then by Cfg_RAM_Ctrl_Unit, upgrade wherein read pointer value corresponding to this passage;
Data message according to output upgrades the data value that disposes in the array ram: subtract one automatically for the double word count value, and initiate the operation of write-back DW_EOF_RAM by Cfg_RAM_Ctrl_Unit, this quantitative value is upgraded; Quantitative value for the data that have EOF among the DW_EOF_RAM of configuration array ram then needs to judge whether to change, if change, then initiate the operation of write-back DW_EOF_RAM by Cfg_RAM_Ctrl_Unit, this quantitative value is upgraded, otherwise, do not do to upgrade operation;
Step 15: multi-channel data buffer memory control/state cell is new tunnel chained list information more;
Judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist then the state of maintenance " Exist.EOF ", otherwise the state that makes " Exist.EOF " is a null value;
According to read pointer value after upgrading and the LWM that looks ahead (low water gauge) value, judge when the shared Block number of storage data in the storage chained list of prepass whether reduced to below the threshold value that LWM sets by the read data operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation;
According to the read pointer value after upgrading, judge whether data all in the storage chained list of prepass are all run through by the read data operation, if then making " Not.Null " state of this passage is null value; Otherwise, keep " Not.Null " state, do not do any renewal operation;
Automatically " Is.Full " state of this passage is updated to null value.
For the data writing operation process of single passage, be that example describes with the single write data process of system bus side, as shown in Figure 5, this process specifically may further comprise the steps:
Step 21: the system bus side joint of multi-channel data buffer memory control/state cell is received the order of write data;
In system's general line side, dynamically arbitrate out indicator signal and the channel number that the permission data send by multi-channel data buffer memory control/state cell, and according to allowing signal and channel number to initiate the write data process of a system bus to dual-port data storage RAM;
In M_Buffer_Ctrl/Status_Unit, a preprocessing process that similarly allows data to send is arranged; Can select to allow the passage chained list of data writing operation according to the passage chain table status Beyond.LWM of inside, the Beyond.LWM state has surpassed the low water gauge that sets for the data (promptly waiting for this channel data that is sent by physical port) of ' 1 ' expression this temporary passage in metadata cache in the anter; Mask the passage of the request that sends in system bus side no datat then according to the state of St.TDMA (the channel data status signal of system's general line side), the St.TDMA state is sent out for having the data that belong to this passage to wait in the data transmit queue in the current system of ' 1 ' expression; This process has mainly provided controlled data and has sent condition, and each passage of control sending direction helps the utilization to the bigger efficient of pci bus bandwidth to the frequency that the pci bus request for data sends;
In addition, different requirements based on the bandwidth and the real-time of each passage, interface in the system bus side allows signal to provide controlled priority algorithm to arbitrate to the data transmission of carrying out above-mentioned pretreated a plurality of passages, indicator signal and the channel number of according to priority arbitrating out the transmission of permission data in proper order send to TDMA (DMA of sending direction (direct memory access) module) by the system bus side interface, and TDMA then begins to initiate the data writing operation of system bus to dual-port data storage RAM according to indicator signal and the channel number that these real-time permission data send;
Step 22: multi-channel data buffer memory control/state cell is according to the passage chained list of the value selection permission write data of " Beyond.LWM " of each passage chain table status of inside, and definite channel number;
Complete write data process always issues with TDMA that positive pulse commencing signal that one of M_Buffer_Ctrl/Status_Unit effectively begins write signal " push_start " starts, M_Buffer_Ctrl/Status_Unit receives after the push_start signal, determines the channel number that TDMA sends;
Step 23: multi-channel data buffer memory control/state cell reads WP_RAM, DW_EOF_RAM, the WM_RAM value that disposes in the array ram according to the channel number of determining by configuration RAM control module; Come the next Block pointer value of fetch channel storage chained list current location from BP_RAM according to the readout of WP_RAM;
Finish after the reading of passage chained list and passage relevant configuration information, also need to set up the intermediateness of all these information of write data process; Because the process operation data of physical port side is single always, the operation of system bus side then most applications is the repeatedly data writing operation of burst type, it can be long process, the physical port side data operation of same channels may take place during this period, in order to control easily and to avoid critical point (for example empty state etc. of expiring) that misjudgment takes place in some passage chain table status, in each complete write data process, all carry out the differentiation of passage chain table status during this by intermediateness, no longer each data writing operation is all upgraded the value among the configuration RAM, and when being unified in this write data and finishing, these intermediateness write-back configurations RAM, upgrade operation;
Each data writing operation process also comprises the value of obtaining when the real-time read pointer of prepass, as carrying out the Rule of judgment that Is.Full passage chain table status is upgraded, promptly judges by comparing the reading and writing pointer value;
Step 24: according to each value among the WP_RAM that reads, DW_EOF_RAM, the WM_RAM, by data RAM read-write control unit write data in dual-port data storage RAM;
That is: at first can send out data by a M_Buffer_Ctrl/Status_Unit effective standby ready signal of output " ready_for_data " notice TDMA; M_Buffer_Ctrl/Status_Unit can keep the ready_for_data signal effective in the process of whole write data, be moved to end up to this write data process, perhaps because the TDMA notice finishes, perhaps because the full state of passage chained list finishes this write data process by M_Buffer_Ctrl/Status_Unit, at this moment, this signal will be changed to invalid;
Then, after M_Buffer_Ctrl/Status_Unit output ready_for_data signal, represent ready, TDMA begins data writing operation, it can be operation continuous or that be interrupted, it is an effective data writing operation that TDMA need notify M_Buffer_Ctrl/Status_Unit current by write data useful signal " data_ready ", if an effective data writing operation, M_Buffer_Ctrl/Status_Unit then can write this passage chained list to data so;
Described step 24 further comprises:
Step 241: judge whether write full data in this passage chained list according to threshold value among the WM_RAM and the data value among the DW_EOF_RAM, if, execution in step 242, otherwise, execution in step 243;
Step 242: the data in this passage chained list are exported in request, and after the output of the data in this passage chained list, execution in step 241;
Step 243: begin a data writing operation, promptly according to the write data in dual-port data storage RAM of the write pointer value among the WP_RAM, execution in step 25;
Step 25: the parameter information in the configuration array ram is upgraded by configuration RAM control;
Upgrade write pointer value: determine write pointer according to block pointer information, and by the write pointer value among the WP_RAM of the current configuration array ram of configuration RAM control module renewal; Promptly after each data writing operation was finished, write pointer added one automatically, or skipped to next Block from last double word position of current Block, pointed to the reference position of next Block;
Upgrade the data value in this passage chained list: carry out the renewal of the data value among the DW_EOF_RAM according to the data message that writes; Quantitative value for the data that have EOF then needs to judge whether to change, if change, then upgrades this value, otherwise, do not do to upgrade operation; Automatically add one for DW (double word) count value, then need to judge whether that according to the data that write needs add one to the EOF count value for the quantity that has the EOF data;
In this write data process, if the physical port side read data operation of same channels is arranged, the operation of its write-back DW_EOF_RAM is with conductively-closed, and the operation that forwards to this intermediateness comes up;
Step 26: multi-channel data buffer memory control/state cell is new tunnel chained list information more;
Judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist, the state that then makes " Exist.EOF " is a nonzero value, otherwise, the state of maintenance " Exist.EOF ";
According to write pointer value after upgrading and the LWM value of looking ahead, judge when the shared Block number of storage data in the storage chained list of prepass whether be increased to more than the threshold value that LWM sets by data writing operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation;
From " Not.Null " of this passage of command of execution state is nonzero value;
Judge according to read pointer and write pointer value whether this passage chained list has write full data, if write full data, then making " Is.Full " state of this passage is nonzero value, otherwise, keep " Is.Full " state, do not do any operation.
Among the present invention, when multi-channel data buffer memory control/state cell is received a plurality of data operation commands simultaneously, then need each data operation commands is carried out priority arbitration, determine the priority of each data operation commands; Then, respectively each data operation commands is handled successively accordingly according to the priority orders of determining.
In the physical port side, be to determine port priority by the port numbers order, port 0 has the highest priority, the priority of port one 5 is minimum: therefore, by arranging the less physical port of rate applications use side slogan, just can realize dynamically reasonably being the port bandwidth of different physical port distribute data buffer areas, and adopt the operation mechanism of streamline in the buffer area visit of this side, can be provided under the condition that multiport works simultaneously, the port of higher rate is used; Described stream line operation mechanism is: after priority data operation commands has formerly been determined channel number by multi-channel data buffer memory control/state cell, just can priority after data operation commands more successively by the definite channel number separately of multi-channel data buffer memory control/state cell, carrying out corresponding data manipulation, and need not to carry out again after priority data operation commands is formerly finished by the time priority after data operation commands operate.
In the system bus side ports, for passage at a plurality of application system bus transfer datas of synchronization, according to the passage priority that sets in advance to passage application arbitrate, the passage that priority is high will preferentially obtain data service; The priority setting of passage can be provided with reference to control table as shown in Figure 3, the priority control bit is provided with type for the priority that the user can select, have four types, the passage of high decoding according to priority and press Round-Robin service the passage separate provision priority rule of concrete each passage; Decoding according to priority is meant that channel number is more little, priority is high more, passage by the Round-Robin service is meant: suppose all passages are arranged from small to large by channel number, token ring of end to end then formation, the transmission of token for according to fixing sense of rotation promptly 0,1,2, the direction of 3...253,254,255,0,1,2... transmits successively, the condition that token take place to transmit is " once service having taken place; promptly have a passage to be arbitrated out ", and then token is passed to current serviced passage adjacent next passage on the token direction of transfer.Whenever, the passage of holding token is the highest passage of current priority, the priority descending order is for arranging from the direction that begins when prepass to transmit according to token, then the passage of holding token this moment passage on adjacent on the reverse direction of token transmission is the minimum passage of current priority, initialized the time, owner of a token is ' 0 ' passage, and promptly ' 0 ' passage is the highest passage of priority.
Claims (20)
1, a kind of control chip sheet internal storage system is characterized in that comprising:
Multi-channel data buffer memory control/state cell: provide the data-interface of control chip and each passage, the synchronous operation between coordination data RAM read-write control unit and configuration RAM control module, maintenance channel storaging state information;
Data RAM read-write control unit: finish the basic read-write capability of dual-port data storage RAM, inputoutput data;
Dual-port data storage RAM: each passage is used for the storage entity of storing data information;
Configuration RAM control module: finish the read-write control of all configuration array rams, and the real-time update of configuration array ram, output state information;
Configuration array ram: be used for the metadata cache control information of each passage of real-time storage.
2, control chip sheet internal storage system according to claim 1, it is characterized in that comprising a plurality of storage blocks among the described dual-port data storage RAM, each storage block is organized with the form of chained list, the corresponding block pointer of each storage block, and as a node in the chained list.
3, control chip sheet internal storage system according to claim 2 is characterized in that also being provided with in the described configuration array ram information of the chained list that each storage block among the dual-port data storage RAM constitutes.
4, according to claim 2 or 3 described control chip sheet internal storage systems, it is characterized in that comprising in the described configuration array ram:
Block pointer RAM:, write down each block pointer next block pointer pointed in each passage chained list by the block pointer addressing;
Double word and EOF counting RAM:, be used for each passage of real time record in stored data volume of buffer memory and the quantity that has the data of EOF by unique recording mechanism addressing of each logical channel;
Read pointer RAM:, be used for the read pointer of each passage of real time record by the channel number addressing;
Write pointer RAM:, be used for the write pointer of each passage of real time record by the channel number addressing;
Water gauge RAM:, be used to offer the user and be written as the threshold value that each passage sets by the channel number addressing.
5, according to claim 2 or 3 described control chip sheet internal storage systems, it is characterized in that the passage storaging state information that described multi-channel data buffer memory control/state cell is safeguarded is: passage chained list status information, the passage chained list is meant the storage area of a linked list type structure of being distributed for passage in dual-port data storage RAM, passage chained list status information is used to indicate the take situation of channel data to this storage area.
6, control chip sheet internal storage system according to claim 5 is characterized in that described passage chained list status information comprises:
The signal " Exist.EOF " of passage chain table status: also there is at least one EOF data in its ' nonzero value ' representative in the prepass chained list;
The signal " Beyond.LWM " of passage chain table status: the data of its ' nonzero value ' representative in the prepass chained list surpass low water gauge value, and low water gauge value is the minimum data value in this passage chained list;
The signal " Not.Null " of passage chain table status: the data that its ' nonzero value ' representative is worked as in the prepass chained list are not empty;
The signal " Is.Full " of passage chain table status: its ' nonzero value ' representative is filled up by data writing operation in the prepass chained list.
7, a kind of method of control chip sheet stored is characterized in that comprising:
A, multi-channel data buffer memory control/state cell receive the data operation commands of sending direction and receive direction;
B, data RAM read-write control unit carry out read-write operation according to the parameter information in data operation commands that receives and the configuration array ram to dual-port data storage RAM;
C, dual-port data storage RAM read-write operation finished after, by configuration RAM control module the parameter information in the configuration array ram is upgraded;
D, while multi-channel data buffer memory control/state cell be new tunnel chained list status information more.
8, the method for control chip sheet stored according to claim 7 is characterized in that described step a comprises: the physical port side joint of multi-channel data buffer memory control/state cell is received the order of read data.
9, the method for control chip sheet stored according to claim 8 is characterized in that described step b comprises:
B1, basis are sent the passage effective index signal and the channel number of the passage of read data order, read the read pointer value and the low water gauge Configuration Values of this passage in the configuration array ram;
B2, multi-channel data buffer memory control/state cell read data among the dual-port data storage RAM according to the read pointer value that reads and low water gauge value by the data RAM read-write control unit;
B3, the data that read are exported by multi-channel data buffer memory control/state cell.
10, the method for control chip sheet stored according to claim 9 is characterized in that described step b2 comprises:
B21, judge whether the data volume in the passage chained list of this passage is lower than the water gauge value, if be lower than this value, execution in step b22 then, otherwise, execution in step b23;
B22, the request in this passage chained list, import data, and in this passage chain the input data after execution in step b21;
B23, the operation of read data of beginning promptly utilize the read pointer value to read data in this passage chained list of dual-port data storage RAM by the data RAM read-write control unit.
11, the method for control chip sheet stored according to claim 9 is characterized in that described step c comprises:
C1, determine read pointer, and upgrade the read pointer information among the read pointer RAM of current configuration array ram by configuration RAM control module according to block pointer information;
C2, upgrade data value in the configuration array ram according to the data message of output, for the double word of configuration array ram and the quantitative value of the data that have EOF among the EOF counting RAM, then need to judge whether to change, if change, then this quantitative value is upgraded, otherwise, do not do to upgrade operation.
12, the method for control chip sheet stored according to claim 11 is characterized in that described steps d comprises:
D1, judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist then the state of maintenance " Exist.EOF ", otherwise, the state that makes " Exist.EOF " is a null value, and wherein also there is at least one EOF data in ' nonzero value ' of passage chained list status signal " Exist.EOF " representative in the prepass chained list;
D2, according to read pointer value after upgrading and the low water gauge value of looking ahead, judge when the shared piece number of storage data in the storage chained list of prepass whether reduced to below the threshold value that low water gauge sets by the read data operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation, wherein the data of ' nonzero value ' of passage chained list status signal " Beyond.LWM " representative in the prepass chained list surpass low water gauge value;
D3, according to the read pointer value after upgrading, judge whether data all in the storage chained list of prepass are all run through by the read data operation, if then making " Not.Null " state of this passage is null value; Otherwise, keep " Not.Null " state, do not do any renewal operation, wherein ' nonzero value ' of passage chained list status signal " Not.Null " representative when the data in the prepass chained list be sky;
D4, automatically " Is.Full " state of this passage is updated to null value, wherein ' nonzero value ' of passage chained list status signal " Is.Full " representative is filled up by data writing operation in the prepass chained list.
13, the method for control chip sheet stored according to claim 7 is characterized in that described step a comprises: the system bus side joint of multi-channel data buffer memory control/state cell is received the order of write data.
14, the method for control chip sheet stored according to claim 13 is characterized in that described step b comprises:
B4, multi-channel data buffer memory control/state cell select to allow the passage chained list of write data according to the value of " Beyond.LWM " of each passage chain table status of inside, and definite channel number, and set up intermediateness at information in the configuration R A M array of this passage, wherein the data of ' nonzero value ' of passage chained list status signal " Beyond.LWM " representative in the prepass chained list surpass low water gauge value;
B5, multi-channel data buffer memory control/state cell are according to the channel number of determining, the write pointer RAM, double word and the EOF that read in the configuration array ram by configuration RAM control module count RAM, water gauge RAM value;
Each value among the write pointer RAM that b6, basis read, double word and EOF counting RAM, the water gauge RAM is by data RAM read-write control unit write data in dual-port data storage RAM.
15, the method for control chip sheet stored according to claim 14 is characterized in that described step b6 comprises:
B61, judge whether write full data in this passage chained list according to the data value among the threshold value among the water gauge RAM and double word and the EOF counting RAM, if, execution in step b62, otherwise, execution in step b63;
The data in this passage chained list are exported in b62, request, and after the output of the data in this passage chained list, execution in step b61;
B63, data writing operation of beginning are promptly according to the write data in dual-port data storage RAM of the write pointer value among the write pointer RAM, execution in step c.
16, the method for control chip sheet stored according to claim 14 is characterized in that described step c comprises:
C3, determine write pointer according to block pointer information; Determine stored data value and the quantitative value that has the data of EOF among double word and the EOF counting RAM according to the data message that writes, quantitative value for the data that have EOF then needs to judge whether to change, if change, then upgrades this value, otherwise, do not do to upgrade operation;
C4, after each data writing operation is finished, the intermediateness of passing through to be set up is carried out the renewal of each value among write pointer and double word and the EOF counting RAM;
C5, when the repeatedly data writing operation of epicycle finishes, each parameter value in the above-mentioned intermediateness is written back in the current configuration array ram by configuration RAM control module;
17, the method for control chip sheet stored according to claim 16 is characterized in that described steps d comprises:
D5, judge in the current passage chained list whether have the data of being with EOF according to upgrading back EOF value, if exist, the state that then makes " Exist.EOF " is a nonzero value, otherwise, the state that keeps " Exist.EOF ", wherein also there is at least one EOF data in ' nonzero value ' of passage chained list status signal " Exist.EOF " representative in the prepass chained list;
D6, according to write pointer value after upgrading and the low water gauge value of looking ahead, judge when the shared piece number of storage data in the storage chained list of prepass whether be increased to more than the threshold value that low water gauge sets by data writing operation, if then making " Beyond.LWM " state of this passage is null value; Otherwise, keep " Beyond.LWM " state, do not do any renewal operation;
D7, be nonzero value from " Not.Null " of this passage of command of execution state, wherein ' nonzero value ' of passage chained list status signal " Not.Null " representative when the data in the prepass chained list be sky;
D8, judge according to read pointer and write pointer value whether this passage chained list has write full data, if write full data, then making " Is.Full " state of this passage is nonzero value, otherwise, keep " Is.Full " state, do not do any operation, wherein ' nonzero value ' of passage chained list status signal " Is.Full " representative is filled up by data writing operation in the prepass chained list.
18, the method for control chip sheet stored according to claim 7 is characterized in that: also comprised before execution in step b:
E, multi-channel data buffer memory control/state cell carry out priority arbitration to receiving a plurality of data operation commands, determine the priority of each data operation commands;
F, according to the priority orders of determining respectively to each data operation commands execution in step b successively.
19, the method for control chip sheet stored according to claim 18 is characterized in that described step e comprises:
E1, in the physical port side, be to determine priority level according to the port order, promptly believe the little port priority of port numbers formerly;
E2, in system's general line side, be the priority of determining each passage application according to the priority of each passage that sets in advance.
20, the method for control chip sheet stored according to claim 18, it is characterized in that described step f according to priority adopts stream line operation in proper order in a plurality of read data orders of physical port side, be after priority read data order has formerly been determined channel number by multi-channel data buffer memory control/state cell, priority after the read data order more successively by the definite channel number separately of multi-channel data buffer memory control/state cell.
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| CN 02129193 CN1286029C (en) | 2002-08-20 | 2002-08-20 | Device for controlling interior storage of chip and its storage method |
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| CN 02129193 CN1286029C (en) | 2002-08-20 | 2002-08-20 | Device for controlling interior storage of chip and its storage method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101350737B (en) * | 2007-07-19 | 2011-05-04 | 宏正自动科技股份有限公司 | Ipmi systems and electronic apparatus and memory sharing method |
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| CN100337226C (en) * | 2004-04-08 | 2007-09-12 | 华为技术有限公司 | Dada buffer designing method with multiple channels and device thereof |
| CN1304971C (en) * | 2004-07-08 | 2007-03-14 | 威盛电子股份有限公司 | Storage access device and relative device |
| CN100456271C (en) * | 2007-03-19 | 2009-01-28 | 中国人民解放军国防科学技术大学 | Stream application-oriented on-chip memory |
| CN101465722B (en) * | 2007-12-21 | 2011-07-13 | 瑞昱半导体股份有限公司 | Method for deciding target type of multi-channel system control signal |
| CN101610477B (en) * | 2009-07-13 | 2012-09-05 | 中兴通讯股份有限公司 | Multimedia messaging service processing system and method |
| CN101692655B (en) * | 2009-10-23 | 2012-05-30 | 烽火通信科技股份有限公司 | Data frame storage management device |
| CN103714038B (en) * | 2012-10-09 | 2019-02-15 | 中兴通讯股份有限公司 | A kind of data processing method and device |
| CN104333803B (en) * | 2014-10-29 | 2018-08-21 | 华为技术有限公司 | Method, equipment and the system of frame losing when preventing video editing |
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| CN106775477B (en) * | 2016-12-19 | 2021-01-01 | 湖南国科微电子股份有限公司 | SSD (solid State disk) master control data transmission management device and method |
| CN108959107B (en) * | 2017-05-18 | 2020-06-16 | 深圳市中兴微电子技术有限公司 | Sharing method and device |
| CN111290715B (en) * | 2020-02-24 | 2023-04-28 | 山东华芯半导体有限公司 | Safe storage device based on partition realization |
| CN112306420B (en) * | 2020-11-13 | 2023-01-17 | 山东云海国创云计算装备产业创新中心有限公司 | Data read-write method, device and equipment based on storage pool and storage medium |
| CN114003526B (en) * | 2021-12-30 | 2022-04-01 | 中科声龙科技发展（北京）有限公司 | Method and circuit for accessing write data path of on-chip memory control unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101350737B (en) * | 2007-07-19 | 2011-05-04 | 宏正自动科技股份有限公司 | Ipmi systems and electronic apparatus and memory sharing method |
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