CN1304971C - Storage access device and relative device - Google Patents
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- CN1304971C CN1304971C CNB2004100633886A CN200410063388A CN1304971C CN 1304971 C CN1304971 C CN 1304971C CN B2004100633886 A CNB2004100633886 A CN B2004100633886A CN 200410063388 A CN200410063388 A CN 200410063388A CN 1304971 C CN1304971 C CN 1304971C
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Abstract
The present invention provides an access method of storage devices and a relative device thereof. In one embodiment of the present invention, a storage device has double channels; storage arrays connected with the channels are arranged asymmetrically, namely that each channel is connected with at least one storage array with the same capacity to form paired symmetric parts on the double channels; however, in addition, at least one non-paired storage array forms the asymmetric parts of the double channels. When the storage device is accessed, the present invention uses single-channel transmission frequency width for accessing the data of the asymmetric parts, and uses double-channel high transmission frequency width for accessing the data of the symmetric parts. In this way, even if the storage arrays configurated on the double channels are asymmetric, the present invention still can use the characteristic of the double channels for enhancing the access efficiency of the storage device.
Description
Technical field
The present invention relates to a kind of access method and relevant apparatus of memory storage, relate in particular to a kind of storage access device and relevant apparatus that can in the binary channels memory storage of asymmetric configuration, improve data access efficiency.
Background technology
Microprocessor system as computer system or the like, has become one of most important hardware foundation of advanced information society; And to the efficient requirement of microprocessor system, also improve day by day.As is known to the person skilled in the art, computer system cooperates chipset (as north bridge chips) and memory storage to operate with central processing unit.For instance, memory storage can be a random access storage device, with program code stored and data or the like; Central processing unit is also carried out by program code in the chipset accessing storage devices and related data, just can realize the function of computer system.Hence one can see that, promote the efficient of computer/microprocessor system, and one of its key promotes the efficient to the memory storage data access exactly.
As is known to the person skilled in the art, in existing common computer system specification, memory storage is to be come out by one or several memory modules (memory module) institute common combination.Each memory module can be provided with one or two storage array (rank), and is provided with a plurality of memory circuit particles (device) in each memory array, with record data.For instance, in the existing computer system specification, the dual inline memory module (DIMM, Dual-Inline Memory Module) of so-called monolateral (single sided) or bilateral (double sided) is arranged; Only be provided with the memory circuit particle in the monolateral memory module, and these memory circuit particles can be connected to a storage array by unification in a side.Relatively, the both sides of bilateral storage array are equipped with the memory circuit particle, are connected to a storage array separately, so two storage arrays that memory capacity is identical can be provided in the bilateral memory module.Existing computer system is many can hold a plurality of memory modules, and by the control of chipset these memory modules is integrated as a whole memory storage, with the unified memory resource of supporting computer system.
When accessing storage devices, chipset can transmit the data that are recorded in storage array in each memory module by passage (channel).Can be provided with two passages (binary channels) in the existing computer system, each passage can be connected in the memory module of one or more correspondences.Particularly, when each storage array on being connected in same passage all has the identical corresponding stored array of memory capacity on another passage, just can on binary channels, form the memory storage of balanced configuration in couples.When memory storage has balanced configuration, chipset can be simultaneously at two passage transmitting datas, in the unit interval, transmit two data on the passage simultaneously, come accessing storage devices with twin-channel data transmission frequency range (the data transmission frequency range is the product of interior volume of transmitted data of unit interval and transfer rate).Relatively, during as if memory storage and symmetrical arrangements, chipset is interior at one time just can only be by single passage access data, and the data in the unit interval on passage of transmission are just come accessing storage devices with single pass data transmission frequency range.
In general, even the message transmission rate on each passage all is certain, but because twin-channel access mode can be simultaneously with two channel transmission datas, thus twin-channel transmitting bandwidth far above single pass transmitting bandwidth, obvious twin-channel data transmission has greater efficiency.Yet twin-channel data transmission frequency range can only could realize when memory storage has balanced configuration that this has also further limited the elasticity of memory storage in the configuration configuration.For instance, the user is when the configuration store device, just must use in pairs, the memory module of memory capacity, structure identical (as being all bilateral memory module) just can be combined into the memory storage of balanced configuration, this has also just increased the cost of computer system configurations.On the other hand, in the prior art,,, also can't utilize binary channels to promote the transmitting bandwidth of storage access fully even memory storage has two passages if the memory storage of user's configuration does not have balanced configuration.
Summary of the invention
Therefore, the present invention promptly provides a kind of binary channels characteristic of effectively utilizing in asymmetric memory storage to promote the access method and the relevant apparatus of data transmission frequency range, to overcome the shortcoming of prior art.
Access method of the present invention and relevant apparatus can be established in the chipset, to cooperate the access of binary channels memory storage.When the configuration of this memory storage is asymmetric, if the some storage arrays on the passage still have the identical storage array of another memory capacity to arrange in pairs or groups in couples with it at once on another passage, the present invention just can be divided into same virtual storage array with these two the paired storage arrays that are connected in different passages; And the virtual store array just can be considered the balanced configuration part of this memory storage.Relatively, be not divided into the virtual store array in pairs storage array just can be considered the asymmetric configuration section of this memory storage.
At the balanced configuration part in the memory storage, the present invention comes access in addition with regard to available binary channels transmitting bandwidth.That is to say,, in the identical time, come access, transmission via two passages respectively, reach binary channels data transmission frequency range when the data of wanting access are that data just can be divided into two parts when being stored in the balanced configuration part.When the data of wanting access are when being stored in asymmetric part, just come in addition access with single pass data transmission frequency range.
In other words, even the configuration of memory storage is asymmetric, the present invention still can partly give full play to twin-channel high transmission frequency width at balanced configuration, and then promotes the operational paradigm of computer system, and the configuration elasticity of memory storage is also higher.By contrast, in the prior art, just can only come the memory storage of the asymmetric configuration of access with single pass transmitting bandwidth.
According to an aspect of the present invention, provide a kind of binary channels access method of storage, wherein each this passage connects at least one storage array respectively.This access method includes: when in the different described passages all when identical one first storage array of an amount of capacity should be arranged, then a plurality of these first storage arrays with different described passages are divided into a virtual array; Judge whether a target storage array of desiring access data belongs to this virtual array; If the target storage array of these data does not belong to this virtual array, then with single pass these data of transmitting bandwidth access; And if the target storage array of these data belongs to this virtual array, then with twin-channel these data of transmitting bandwidth access.
According to another aspect of the present invention, provide a kind of storage access control chip, in order to the outside binary channels memory module of access, wherein each this memory module comprises at least one storage array to a passage and this memory module should be arranged.This control chip includes: access module, and should outside binary channels memory module in order to access; One addressed module is connected to this access module, when in the different described passages when a storage array of same capability should be arranged, a plurality of these storage arrays of same capability in all these passages are used as a virtual array; And a judge module, be connected to this access module and this addressed module, whether belong to this virtual array in order to judge a target storage array of desiring access data.Wherein when this judge module judges that the target storage array of these data does not belong to this virtual array, then this access module utilizes these data pairing one these these data of passage access, if this judge module judges when the target storage array of these data belongs to this virtual array that then this access module utilizes two these these data of passage access simultaneously.
Description of drawings
Fig. 1 is the function block schematic diagram of the invention process in a computer system.
Fig. 2 is a synoptic diagram of realizing memory storage among Fig. 1 with balanced configuration.
Fig. 3 is the sequential synoptic diagram of each coherent signal during the balanced configuration memory storage in the access graph 2 of the present invention.
Fig. 4 is a synoptic diagram of realizing memory storage among Fig. 1 with an asymmetric configuration.
Fig. 5 is the sequential synoptic diagram of each coherent signal during asymmetric memory storage in the access graph 4 of the present invention.
Fig. 6, Fig. 7 are the synoptic diagram of realizing memory storage among Fig. 1 with other two kinds of asymmetric configurations.
Fig. 8 is the process flow diagram of access memory data of the present invention
20 control circuits, 22 interface modules
24 judge modules, 26 access modules
28 addressing moulds, 30 memory storages
32A-32B passage 34A-34B, 36A-36B slot
38 chipsets, 40 main frames
42 computer system 46A-46B, 48A-48B memory module
The 460-467 storage array T cycle
S0-S7 control signal t0-t4, ta-tb, ta2-tb2 are constantly
RDX, RDY steering order
Embodiment
Please refer to Fig. 1.Fig. 1 is control circuit 20 of the present invention and is implemented on the chipset 38 of a computer system 42 the memory storage 30 of a binary channels is carried out the function block schematic diagram of access control.In computer system 42 (as a personal computer or other microprocessor system), chipset 38 can be a storage access control chip, with access interface as memory storage 30, the memory resource that makes a main frame (host) 40 can utilize memory storage 30 to be provided.Wherein, main frame 40 can be a central processing unit, or other can directly store device or the circuit of getting; Then include an interface module 22 and a control circuit 20 in the chipset 38.For realizing technology of the present invention, be provided with a judge module 24, an access module 26 and an addressed module 28 in the control circuit 20.In memory storage 30, then be provided with the slot (in Fig. 1 with slot 34A to 34B, 36A to 36B as representative) of a plurality of memory modules, each slot can be planted and a memory module is installed (as can random-access dual inline memory module, DIMM); The memory capacity of gathering memory module on each slot, just 30 of the memory storages total memory resource that can provide.And each memory module in chipset 38, passage 32A, 32B and the memory storage 30 also just is combined into the memory access device of a hyperchannel (binary channels).
For memory module recorded data on each slot of access, access module 26 can transfer to each memory module via each slot with instruction, the signal of various access control.For instance, if what plant on a certain slot is bilateral memory module and have two storage arrays, this slot just can transfer to different control signals respectively the different storage array of same memory module at each storage array.For instruction, the signal that will respond access control, each memory module also can be through transmitting its recorded data by the passage that slot connected.As in the embodiment in figure 1, slot 34A, 36A just are connected in passage 32A, and slot 34B, 36B then are connected in passage 32B.So, the memory module that is inserted on slot 34A, the 36A just can transfer out its recorded data via passage 32A, maybe will transfer to the memory module data recording.In like manner, the memory module that is installed on slot 34B, 36B then can be transmitted data via passage 32B.
The situation that 38 pairs of memory storages of chipset 30 carry out access control can be described below.When computer system 42 starts, it can detect memory storage 30 (as by ROM-BIOS, Basic InputOutput System, detect), with the configuration (having how much memory capacity or the like) of each memory module in the detection of stored device 30, and then confirm the memory resource that memory storage 30 can provide altogether as the memory module on that slot.And the global storage resource addressing that chipset 38 will can provide 30 of memory storages, divide into different address (as physical address), and set up mapping relations between address and each storage array, make main frame 40 to come data access that memory storage 30 is carried out at random according to the address.For instance, suppose that the mounted memory module can provide three storage arrays altogether in the memory storage 30, the storage space that chipset 38 just can provide these three storage arrays maps to different addresses.When main frame 40 will deposit data in certain address, it is to belong to the storage space which storage array provides that chipset 38 can be deciphered out earlier this address, control this storage array with the control signal of correspondence then, and with data transmission to this storage array, to write down this data.In like manner, if main frame 40 will be read the data of certain address correspondence, which storage array chipset 38 goes out this address corresponding to regard to decodable code, and with the control signal of correspondence by this storage array sense data.
When memory storage was carried out access, at different storage device configuration, control circuit 20 of the present invention also can carry out the access control of different mode to memory storage 30.At first please refer to Fig. 2; The framework of continuity among Fig. 1, Fig. 2 are the synoptic diagram that chipset 38 carries out access control at the memory storage 30 of balanced configuration.In the illustrated embodiment of Fig. 2, suppose on slot 34A, 34B, to be separately installed with bilateral memory module 46A, a 46B, so memory module 46A has two storage arrays 460,461, memory module 46B equally also has two storage arrays 464,465.By slot 34A, 34B, storage array 460 to 461,464 to 465 can be distinguished control signal S0 to S1, the S4 to S5 of receiving chip group 38.Under the configuring condition of Fig. 2,, just can form the memory storage of further formation balanced configuration if storage array 460,461 has identical memory capacity with storage array 464,465 respectively.Under this configuration, the storage array 460 that is connected in passage 32A has the identical storage array of a memory capacity 464 corresponding in pairs with it on another passage 32B, storage array 461 also has the identical storage array of a memory capacity 465 corresponding in pairs with it on another passage, makes memory storage 30 have the configuration of symmetry on binary channels.
When memory storage 30 was balanced configuration, control circuit 20 of the present invention just can be divided into storage array paired on the binary channels same virtual storage array, comes accessing storage devices 30 with twin-channel data transmission frequency range.With the balanced configuration among Fig. 2 is example, it is virtual arrays that addressed module 28 will be used as storage array paired on the binary channels 460 and 464, storage array 461 and 465 respectively, and the global storage mapping resources that in view of the above 30 of memory storages can be provided is to different addresses.As data (for example is the data of a 8QW, one 16 is a quad word (four words), can note by abridging and be QW) in the time of will depositing virtual array in, access module 26 is actually these data is decomposed into two parts (as the part of two each 4QW), is recorded in respectively in the storage array paired on two passages.Because these two-part data can transfer to corresponding storage array simultaneously respectively on two passages, so can bring into play twin-channel data transmission frequency range.In like manner, if will from a virtual array data be read, access module 26 is actually by in the paired storage array of two passages two parts of same data being read via the passage of correspondence respectively, and recombinant is original data.For further specifying the principle that said process carries out, please continue with reference to figure 3 (and in the lump with reference to figure 2).Fig. 3 is chipset 38 at the memory storage of balanced configuration among Fig. 2 and when carrying out data access in memory storage 30, the sequential chart of each relevant data signals; The transverse axis of Fig. 3 is the time.
Example among continuity Fig. 2 in Fig. 3, supposes when moment t0 that main frame 40 requirements will be read data of certain address from memory storage 30, and this data length is 8QW, and the data Dt0 to Dt7 that is 1QW by 8 length is formed jointly.Suppose that the storage space that this address is mapped to is in storage array 460,464 formed virtual arrays, access module 26 will read steering order RDX as control signal S0, S4 (Fig. 2) with identical simultaneously at moment t1, transfers to two storage arrays 460 and 464 on the passage respectively.Arrived t2 constantly, storage array 460 will begin to transmit data Dt0, Dt2, Dt4, Dt6 in regular turn by passage 32A; At the same time, storage array 464 also can begin to transmit data Dt1, Dt3, Dt5, Dt7 in regular turn by passage 32B.Chipset 38 combines data Dt0 to Dt7, just can obtain original 8QW data.In other words, when the data of a 8QW will be stored to memory storage 30, if memory storage 30 is balanced configurations, chipset 38 just can be controlled storage array paired on the binary channels symmetrically, deposited the data of 4QW simultaneously in each storage array respectively in; Just as example discussed above, chipset 38 can be alternately with first and third, five, seven QW of 8QW data as a part, second, four, six, eight QW deposits two storage arrays respectively in as another part.In the time of these data will being read, chipset 38 also just can be combined into original 8QW data symmetrically by simultaneously the data of each 4QW being read in twin-channel paired storage array.
By above-mentioned discussion as can be known, when having balanced configuration as if memory storage 30 on binary channels, chipset 38 just can be controlled storage array paired on the binary channels respectively with identical steering order and control signal symmetrically and carry out access.Because binary channels all can be transmitted data in the same time, so can realize the higher data transmitting bandwidth.Just as shown in Figure 3, owing to the data of a 8QW can be transmitted on binary channels abreast, so only need the time of 2 period T just can finish the data transmission (supposing that the memory module of using is double data rate, Double Data Rate) of 8QW.In addition, twin-channel symmetrical access can also reduce the delay (latency) of access operation.For instance, at moment t3, access module 26 can also send another steering order RDY as control signal by paired storage array simultaneously on binary channels, make paired storage array respectively again by the data Dy0 to Dy7 that transmits 8QW on the binary channels, to form the data of another 8QW.
But, when memory storage is not balanced configuration, just can't utilize twin-channel high transmission frequency width fully.Because configuration is asymmetric, chipset just can not controlled different storage arrays on the binary channels with the control signal of symmetry simultaneously; No matter data storage is in which storage array, chipset all only can be controlled a single storage array at one time, transmits data via a single passage.In other words, the data of a 8QW can only be fully by a single channel transfer, so need the time of 4 period T just can finish the transmission of 8QW data.
And the present invention can overcome can't use twin-channel shortcoming in the memory storage of symmetrical arrangements, and then promotes the data transmission efficiency of asymmetric memory storage.When the configuration of a memory storage was also asymmetric, the present invention still can be divided into the part of balanced configuration in this memory storage same virtual array, and then utilizes twin-channel high data transmission frequency range.Below promptly illustrate that with example the present invention carries out the technical spirit of data access in the memory storage of asymmetric configuration.
Please refer to Fig. 4 and Fig. 5; The computer system architecture of continuity among Fig. 1, the configuration of supposing memory storage 30 is asymmetric configuration as shown in Figure 4, and Fig. 5 is the sequential synoptic diagram of the present invention's relevant data signals when the memory storage among Fig. 4 is carried out access, and the transverse axis of Fig. 5 is the time.In the asymmetric configuration of Fig. 4, suppose that memory storage 30 has three slot 34A, 36A and 34B to be separately installed with a memory module 46A, 48A and 46B.Wherein, memory module 46A, 46B are bilateral memory module, has storage array 460 and 461,464 and 465 respectively, and storage array 460 and 464,461 and 465 has identical memory capacity, so storage array 460 and 464 can be considered as the storage array of symmetry in pairs, 461,465 of storage arrays are the storage array of another composition to symmetry.These paired storage arrays just form the part of balanced configuration in the memory storage 30.Relatively, another bilateral memory module 48A with storage array 462,463 then becomes the part of asymmetric configuration.Because the storage array 462,463 that is connected on the passage 32A does not all have the collocation in pairs with it of relative storage array on another passage, make that the configured in one piece of memory storage 30 is asymmetric.
Though the configured in one piece of memory storage 30 is asymmetric, but because storage array 460,461 still has the paired with it correspondence of the storage array 464,465 of identical memory capacity on another passage, so in the present invention, addressed module 28 will be divided into same virtual array with storage array paired on the binary channels 460,464, and storage array 461,465 is divided into another virtual array; And these virtual arrays just can come access in addition with twin-channel data transmission frequency range.These can't find the storage array in pairs of paired storage array on another passage as storage array 462,463, just come in addition access with single pass data transmission frequency range.
In other words, when detecting memory storage 30 when computer system 42 start and not having balanced configuration, addressed module 28 of the present invention still can be divided into same virtual array with storage array paired on the binary channels according to the part that has balanced configuration in the memory storage 30, each storage array of asymmetric part then is considered as a storage array on the single channel, and sets up the mapping relations of storage space according to above-mentioned these array configurations.When main frame 40 has data will write to certain address in the memory storage 30, judge module 24 among the present invention can judge that earlier this address is to map to the formed virtual array storage space of paired storage array, the still not paired formed storage space of storage array.If this map addresses is the paired formed storage space of storage array on the binary channels, access module 26 just can utilize identical control signal to be controlled to right storage array symmetrically, simultaneously the different piece of these data is utilized binary channels to transfer in the paired storage array, finished data access with twin-channel data transmission frequency range.Relatively, if this address is to map to the storage space that storage array is in pairs provided, 26 of access modules utilize single channel with the lump-sum data transmission to same storage array.
Please refer to the example among Fig. 5.Suppose that main frame 40 will read two 8QW data, data are made up of the data Dt0 to Dt7 of 1QW, the map addresses of these data is to the paired formed virtual array of storage array 461 and 465 (Fig. 4), so these data are actually and are divided into two parts and are recorded in respectively in storage array 461 and 465.Relatively, suppose that another 8QW data have 8 1QW data Dy0 to Dy7, and the storage space of the map addresses of these 8QW data is in azygous storage array 462, so all data Dy0 to Dy7 of these 8QW data are recorded in the same storage array 462.When main frame 40 was wanted above-mentioned two data of access, the map addresses storage space extremely that judge module 24 of the present invention can be judged these two data why.Wherein, last 8QW data are to be recorded in the formed virtual array of paired storage array, so access circuit 30 will be at the same time is used as control signal S1, S5 on the binary channels with identical steering order RDX, make storage array 461 and 465 simultaneously begin to transmit in regular turn data Dt0, Dt2, Dt4, Dt6 and Dt1, Dt3, Dt5, Dt7 at moment tb, this is recorded in data in the paired storage array just to come access with twin-channel data transmission frequency range.
Want another 8QW data of access, judge module 24 of the present invention can judge that it is recorded in the not paired storage array 462 according to the address of these data.So access module 26 can be used as control signal S2 with the steering order RDY on the single passage 32A at moment ta2, begins to transmit in regular turn 8 1QW data Dy0 to Dy7 of these data at moment tb2 with control store array 462.
By foregoing description as can be known, though the configured in one piece of memory storage 30 is asymmetric, the present invention still can give full play to the advantage of binary channels data transmission at the part that has balanced configuration in the memory storage.Note that in the prior art if the configured in one piece of its memory storage is asymmetric, no matter want the paired or azygous storage array of access, the prior art chipset all only can utilize single passage to carry out data access.Illustrate with the example among Fig. 4, Fig. 5, do not have at memory storage under the situation of balanced configuration, because the prior art chipset can not be divided into paired memory module same virtual array, even want the 8QW data in the access storage array 461, prior art also still can only be utilized tb2 sequential afterwards constantly, on single passage, transmit whole 8 1QW data Dt0 to Dt7, and can't make full use of the characteristic of " storage array 461 has a paired storage array 465 in addition on another passage " as the present invention.
Circuit framework among continuity Fig. 2 below will illustrate the situation of the invention process in asymmetric configuration store device with two among Fig. 6, Fig. 7 configuration examples again.In Fig. 6, memory storage 30 disposes four memory module 46A to 46B, 48A to 48B, and wherein, memory module 46A, 48B are bilateral, is respectively equipped with storage array 460 and 461, storage array 466 and 467.Memory module 48A, 46B then are monolateral memory modules, respectively have a storage array 462,465.Suppose storage array 460,461 and 466,467 to have identical memory capacity respectively and on binary channels the symmetry, addressed module 28 of the present invention just the storage array on the binary channels 460,466 can be mixed into to and be considered as a virtual array, another on the binary channels then becomes another virtual array to storage array 461,467; And the data in these two virtual arrays just can with twin-channel mode come access (as in Fig. 4 to paired storage array 461 and 465 modes of carrying out access).In addition, if the memory capacity of storage array 462,465 is inequality, just become azygous storage array on the single channel, the present invention comes access storage array 462,465 (be exactly among Fig. 4 not the paired access mode of storage array 462) in single pass mode.
In Fig. 7, memory storage 30 disposes a bilateral memory module 46A and a monolateral memory module 48B, and memory module 46A has two storage arrays 460,461; Then be provided with a storage array 467 among the memory module 48B.The memory capacity of supposing storage array 460,461 and 467 is all identical, but one of two storage arrays of memory module 46A can't find the storage array of paired collocation on another passage, so the configured in one piece of memory storage 30 is asymmetric.Under this kind configuration, addressed module 28 of the present invention can be considered as same virtual array with storage array on the binary channels 460 and storage array 467 (or storage array 461 and storage array 467), and azygous storage array 461 (or storage array 460) then is the separate, stored array on the single channel.When main frame 40 was wanted the data of a certain address of access, judge module 24 can be judged the storage space of this map addresses.If this address is in pairs in the formed storage space of storage array 461 (or storage array 460), access module 26 just can be on passage 32A with the in addition access of single pass pattern.If this address is in the paired formed virtual array of storage array 460,467 (or storage array 461,467) time, access module 26 just can utilize binary channels to come these two paired storage arrays of access symmetrically simultaneously, makes full use of the characteristic of the high data transmission frequency range of binary channels.
Fig. 8 is the process flow diagram of the asymmetric configuration storage module of access of the present invention.If when having its amount of capacity of storage array A identical with storage array B on another passage on a passage, the storage array A and the B that then are positioned on the different passages promptly are set as a virtual array.When the target location of access data is positioned on the virtual array, then can utilize the dual port access data simultaneously.Otherwise, if target location cloth is on virtual array, then with the single channel access memory.
In summary, in the prior art, if the configuration of memory storage is asymmetric, no matter data are to be recorded in which storage array, and the prior art chipset all only can come in addition access in single pass mode.By contrast, when the invention process is in asymmetric memory storage, only in pairs just can not continue to use single pass access mode during storage array in access; At storage array paired on the binary channels, the present invention still can give full play to the binary channels advantage of data transmission simultaneously.Even the configuration of memory storage is asymmetric, the present invention still can essence promotes the access efficiency of this type of memory storage.In the present invention in the enforcement framework of Fig. 1, the function of judge module 24, addressed module 28 can realize with software (as come the software program for execution code with chipset) or hardware circuit, changes access mode to memory storage so that whether map to paired storage array according to the access address when address decoding (address decoding), paging decoding (page decoding) and instruction ordering (command scheduling).
The above only is preferred embodiment of the present invention, and all equalizations that claim is done according to the present invention change and modify, and all should belong within the covering scope of patent of the present invention.
Claims (7)
1. binary channels access method of storage, wherein each this passage connects at least one storage array respectively, and this access method includes:
When in the different described passages all when identical one first storage array of an amount of capacity should be arranged, then a plurality of these first storage arrays with different described passages are divided into a virtual array;
Judge whether a target storage array of desiring access data belongs to this virtual array;
If the target storage array of these data does not belong to this virtual array, then with single pass these data of transmitting bandwidth access; And
If the target storage array of these data belongs to this virtual array, then with twin-channel these data of transmitting bandwidth access.
2. binary channels access method of storage as claimed in claim 1, when wherein the target storage array of storing when this data desire belongs to this virtual array, the each several part of these data of stored interleaved in these a plurality of first storage arrays that this virtual array comprised.
3. binary channels access method of storage as claimed in claim 1, when wherein the target storage array of desiring to read when these data belongs to this virtual array, be combined into this data after then from these a plurality of first storage arrays that this virtual array, comprised, reading the each several part of these data respectively.
4. storage access control chip, in order to the outside binary channels memory module of access, wherein each this memory module comprises at least one storage array to a passage and this memory module should be arranged, and this control chip includes:
One access module should outside binary channels memory module in order to access;
One addressed module is connected to this access module, when in the different described passages when a storage array of same capability should be arranged, a plurality of these storage arrays of same capability in all these passages are used as a virtual array; And
One judge module is connected to this access module and this addressed module, whether belongs to this virtual array in order to judge a target storage array of desiring access data;
Wherein when this judge module judges that the target storage array of these data does not belong to this virtual array, then this access module utilizes these data pairing one these these data of passage access, if this judge module judges when the target storage array of these data belongs to this virtual array that then this access module utilizes two these these data of passage access simultaneously.
5. storage access control chip as claimed in claim 4, wherein when the target storage array of this data desire storage belongs to this virtual array, with the each several part stored interleaved of these data in these a plurality of storage arrays that this virtual array comprised.
6. storage access control chip as claimed in claim 4, when wherein the target storage array of desiring to read when these data belongs to this virtual array, be combined into this data after then from these a plurality of storage arrays that this virtual array, comprised, reading the each several part of these data respectively.
7. storage access control chip as claimed in claim 4, wherein the transmitting bandwidth of this passage is identical.
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| CNB2004100633886A CN1304971C (en) | 2004-07-08 | 2004-07-08 | Storage access device and relative device |
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| CNB2004100633886A CN1304971C (en) | 2004-07-08 | 2004-07-08 | Storage access device and relative device |
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| CN1588335A CN1588335A (en) | 2005-03-02 |
| CN1304971C true CN1304971C (en) | 2007-03-14 |
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| CNB2004100633886A Expired - Lifetime CN1304971C (en) | 2004-07-08 | 2004-07-08 | Storage access device and relative device |
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| US7872892B2 (en) * | 2005-07-05 | 2011-01-18 | Intel Corporation | Identifying and accessing individual memory devices in a memory channel |
| CN102810079A (en) * | 2011-06-03 | 2012-12-05 | 联咏科技股份有限公司 | Heterogeneous memory architecture and access method |
| CN105446911B (en) * | 2014-05-29 | 2018-05-25 | 展讯通信（上海）有限公司 | The memory access control method and device of terminal device |
| CN105531682A (en) * | 2014-08-15 | 2016-04-27 | 联发科技股份有限公司 | Method for managing multi-channel memory device to have improved channel switch response time and related memory control system |
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| CN1122927A (en) * | 1994-11-05 | 1996-05-22 | 联华电子股份有限公司 | Virtual array type access device of direct memory |
| WO1996035166A1 (en) * | 1995-05-01 | 1996-11-07 | Computer Performance, Inc. | Enhanced-performance floppy diskette subsystem |
| US6145024A (en) * | 1997-06-06 | 2000-11-07 | Hitachi, Ltd. | Input/output optical fiber serial interface link that selectively transfers data in multiplex channel path mode or high speed single channel path mode |
| CN1477532A (en) * | 2002-08-20 | 2004-02-25 | 华为技术有限公司 | Device for controlling interior storage of chip and its storage method |
| CN1487428A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Controller for outer multi-channel network disc array and its protocol fitting method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122927A (en) * | 1994-11-05 | 1996-05-22 | 联华电子股份有限公司 | Virtual array type access device of direct memory |
| WO1996035166A1 (en) * | 1995-05-01 | 1996-11-07 | Computer Performance, Inc. | Enhanced-performance floppy diskette subsystem |
| US6145024A (en) * | 1997-06-06 | 2000-11-07 | Hitachi, Ltd. | Input/output optical fiber serial interface link that selectively transfers data in multiplex channel path mode or high speed single channel path mode |
| CN1477532A (en) * | 2002-08-20 | 2004-02-25 | 华为技术有限公司 | Device for controlling interior storage of chip and its storage method |
| CN1487428A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Controller for outer multi-channel network disc array and its protocol fitting method |
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