CN1276491C - Semiconductor chiop and its packaging method - Google Patents
Semiconductor chiop and its packaging method Download PDFInfo
- Publication number
- CN1276491C CN1276491C CNB011026065A CN01102606A CN1276491C CN 1276491 C CN1276491 C CN 1276491C CN B011026065 A CNB011026065 A CN B011026065A CN 01102606 A CN01102606 A CN 01102606A CN 1276491 C CN1276491 C CN 1276491C
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- Prior art keywords
- chip
- film layer
- photosensitive film
- semiconductor
- chiop
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
Abstract
The present invention relates to a semiconductor chip device and an encapsulation method thereof. The encapsulation method comprises the following steps: a semiconductor chip has an installation surface for welding pads provided with welding pads, and each welding pad has a conductive contact; a sensitive thin-film layer is formed on the installation surface; photo-etching is carried out to the thin-film layer to form exposure holes exposing the conductive contacts; solder paste is used for filling the exposure holes to make the exposure holes form a conductive welding spot. The semiconductor chip device comprises the semiconductor chip and the sensitive thin-film layer, wherein the semiconductor chip has the installation surface for welding pads provided with the welding pads, and the conductive contact is formed on each welding pad; the sensitive thin-film layer is formed on the installation surface for welding pads, and the exposure holes filled with the solder paste are formed at the positions of the sensitive thin-film layer corresponding to the conductive contacts. The semiconductor chip device can be conveniently and electrically connected with an external circuit.
Description
Technical field
The invention relates to a kind of semiconductor chip, particularly a kind of semiconductor chiop and method for packing thereof.
Background technology
Development along with semiconductor fabrication, in the conventional semiconductor chip apparatus, weld pad on its chip surface becomes more and more littler, and the distance between weld pad also can be dwindled more, so that make itself and being electrically connected of external circuit, become very difficult, and then influence production efficiency, even influence the continuation development of semiconductor fabrication process.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor chiop of being connected with external circuit be convenient to.
Another object of the present invention is to provide a kind of method for packing of semiconductor chiop.
For achieving the above object, the present invention takes following technical measures:
The method for packing of a kind of semiconductor chiop of the present invention, this semiconductor chiop is suitable for being mounted on a substrate or another semiconductor chiop, this substrate or semiconductor chiop have a chip installation area territory, are provided with several solder joints in this chip installation area territory; It comprises the steps:
A semiconductor chip is provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
On the pad installation surface of chip, form a photosensitive film layer;
On photosensitive film layer, put a photomask that covers this photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to this conductive contact part;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed at least a portion by the flushing of photomask cover part, to form the exposed hole that at least the conductive contact head portion of correspondence is exposed;
With each exposed hole of tin cream filling;
Make the tin cream formation two of each exposed hole be suitable for the conductive welding spots that is electrically connected with the corresponding solder joint of substrate or another semiconductor chiop with the infrared ray mode of heating.
Wherein, the position of the weld pad of described semiconductor chip does not correspond to the position of the solder joint of described substrate or another semiconductor chiop, and after the step with the infrared ray heating, also comprises the steps:
With the conducting metal glue material, be formed with electric conductor on described photosensitive film layer, each electric conductor has that a solder joint connecting portion that is electrically connected with the corresponding conductive welding spots of described chip, one are electrically connected with the solder joint connecting portion and as the extension of circuit trace and a free end that is positioned at extension and its position corresponding electrical connection section in position with the corresponding solder joint of described substrate or another semiconductor chiop.
Wherein, after forming the electric conductor step, also comprise the steps:
On the electrical connection section of each electric conductor, form two connecting terminals.
The method for packing of another kind of semiconductor chiop of the present invention, this semiconductor chiop is suitable for being mounted on a substrate or another semiconductor chiop, this substrate or semiconductor chiop have a chip installation area territory, are provided with several solder joints in the chip installation area territory; Comprise the steps:
A semiconductor chip is provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads;
On the pad installation surface of chip, form a photosensitive film layer;
On photosensitive film layer, put a weld pad photomask partly that covers photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to this chip;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed by the flushing of photomask cover part, to form exposed hole with the corresponding pad exposure of this chip;
With the plating means, on the perisporium of each exposed hole, form the conduction connector that is electrically connected and extends to the photosensitive film laminar surface with corresponding pad, this conduction connector is suitable for being electrically connected with the corresponding solder joint of described substrate or another semiconductor chiop.
Wherein, the position of the weld pad of the semiconductor chip that is provided does not correspond to the position of the solder joint of described substrate or another semiconductor chiop, and after described plating step, also comprises the steps:
With the conducting metal glue material, form electric conductor on described photosensitive film layer, each electric conductor has that a connector connecting portion that is electrically connected with the corresponding conduction connector of this chip, one are electrically connected with the connector connecting portion and as the extension and a free end that is positioned at this extension and its position electrical connection section corresponding with the position of the corresponding solder joint of described substrate or another semiconductor chiop of circuit trace.
Wherein, after the step of described formation electric conductor, also comprise the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
A kind of semiconductor chiop of the present invention, it is suitable for being mounted on a substrate or another semiconductor chiop, and this substrate or semiconductor chiop have a chip installation area territory, are provided with several solder joints in the chip installation area territory; Comprise:
A semiconductor chip, it has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
Photosensitive film layer on pad installation surface that is formed on chip, this photosensitive film layer is formed with several in order to expose the exposed hole of the head portion of corresponding conductive contact at least corresponding to the conductive contact place;
Each exposed hole is filled with the tin cream as the conductive welding spots that is suitable for being electrically connected with corresponding solder joint.
Wherein, the bond pad locations of described semiconductor chip does not correspond to the position of the solder joint of described substrate or another semiconductor chiop; Also comprise:
Several are formed on the electric conductor on the described photosensitive film layer, and each electric conductor has that a solder joint connecting portion that is electrically connected with corresponding conductive welding spots, one are electrically connected with the solder joint connecting portion and as the extension and a free end that is positioned at this extension and its position electrical connection section corresponding with the position of the solder joint of described substrate or another semiconductor chiop of circuit trace.
Another kind of semiconductor chiop of the present invention comprises:
A semiconductor chip, it has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
A photosensitive film layer that is formed on the pad installation surface, this photosensitive film layer is formed with several in order to expose the exposed hole of the head portion of corresponding conductive contact at least corresponding to this conductive contact;
Each exposed hole is filled with the tin cream as conductive welding spots;
A substrate, it has a chip installation area territory, is provided with the solder joint that several conductive welding spots corresponding with chip are electrically connected in this chip installation area territory.
Reaching embodiment in conjunction with the accompanying drawings is described in detail as follows architectural feature of the present invention and method feature:
Description of drawings
Fig. 1 to Fig. 6: the schematic flow sheet of method for packing first embodiment of semiconductor chiop of the present invention;
Fig. 7: the schematic diagram that first embodiment of apparatus of the present invention combines with a substrate or another semiconductor chiop;
Fig. 8 to Figure 11: the second embodiment part schematic flow sheet of the method for packing of semiconductor chiop of the present invention;
Figure 12 to Figure 14: the schematic flow sheet of method for packing the 3rd embodiment of semiconductor chiop of the present invention;
Figure 15: the schematic diagram of fourth embodiment of the invention;
Figure 16: the schematic diagram of fifth embodiment of the invention;
Figure 17: the schematic diagram of sixth embodiment of the invention;
Figure 18: the schematic diagram of seventh embodiment of the invention;
Figure 19: the schematic diagram of eighth embodiment of the invention;
Figure 20: the schematic diagram of ninth embodiment of the invention.
Embodiment
Semiconductor chiop of the present invention is suitable for being mounted on a substrate or another semiconductor chiop (seeing shown in Figure 7).This substrate or semiconductor chiop have a chip installation area territory.Be provided with several solder joints in the chip installation area territory.
As shown in Figure 1, at first provide a semiconductor chip 1, semiconductor chip 1 has one and is provided with several weld pads 11 pad installation surface 10 of (only showing in graphic).Then, utilize prior art, on each weld pad 11, form one as the conductive contact 2 as the conductive metal balls.In the present embodiment, conductive contact 2 is a gold goal.
Then, as shown in Figure 2, a photosensitive film layer 3 is formed on the pad installation surface 10 of chip 1.Then, as shown in Figure 3, on photosensitive film layer 3, part that should conductive contact 2 is covered a photomask 4.Then, to photosensitive film layer 3 expose (photoetch) handle so that the partially hardened that photosensitive film layer 3 is not covered by photomask 4.
As shown in Figure 4, after removing photomask, utilize the control washing time, photosensitive film layer 3 is rinsed removal by the part that photomask 4 covers, the exposed hole 30 that exposes with the head portion that only forms the conductive contact 2 of correspondence.Then, again photosensitive film layer 3 is carried out exposure-processed, make photosensitive film layer 3 not be rinsed the partially hardened of removal.
Then, as shown in Figure 5,, afterwards, make tin cream 5 form a conductive welding spots with the infrared ray heating, as shown in Figure 6 with each exposed hole 30 of tin cream 5 fillings.
As shown in Figure 7, semiconductor chiop of the present invention is suitable for being mounted on a substrate or another semiconductor chiop 6.The electric conductor that sets in advance 61 that each conductive welding spots 5 sees through on the solder joint (not shown) of this substrate or another semiconductor chiop 6 is electrically connected with the corresponding solder joint of this substrate or another semiconductor chiop 6.
As shown in Figs. 8 to 11, it is the part schematic flow sheet of method for packing second embodiment of semiconductor chiop of the present invention; As shown in Figure 8, it is identical with first embodiment, on the pad installation surface 10 of chip 1, form a photosensitive film layer 3, afterwards, on photosensitive film layer 3, part that should conductive contact 2 is covered a photomask 4, then, photosensitive film layer 3 is carried out exposure-processed, so that the partially hardened that is not covered on the photosensitive film layer 3 by photomask 4.
As shown in Figure 9, with the first embodiment difference, after removing photomask,, photosensitive film layer 3 is removed by the partial flushing that photomask 4 covers, to form the exposed hole 30 that corresponding conductive contact 2 exposes with existing douching technique.The size of each exposed hole 30 is only to expose corresponding conductive contact 2 just, and can not expose the pad installation surface 10 of chip 1.
Then, as shown in figure 10,, afterwards,, make tin cream 5 form a conductive welding spots with infrared ray heating with each exposed hole 30 of tin cream 5 fillings, as shown in figure 11 as.
Should be noted that when semiconductor chiop with as the method for above-mentioned second embodiment when making, it also as first embodiment, is suitable for being mounted on a substrate or another semiconductor chiop.Because its mode that is mounted to substrate or another semiconductor chiop is identical with first embodiment, repeats no more.
To shown in Figure 14, it represents the schematic flow sheet of method for packing the 3rd embodiment of semiconductor chiop of the present invention as Figure 12;
As shown in figure 12, at first provide a semiconductor chip 1.This semiconductor chip 1 has one and is provided with several weld pads 11 pad installation surface 10 of (only showing among the figure).Different with first and second embodiment, do not form conductive contact on this weld pad 11.
Then, as shown in figure 13, on the pad installation surface 10 of chip 1, form a photosensitive film layer 3, afterwards, on photosensitive film layer 3, cover a photomask 4 corresponding to weld pad 11 parts.Then, photosensitive film layer 3 is carried out exposure-processed, so that the partially hardened that photosensitive film layer 3 is not covered by photomask 4.
As shown in figure 14, after removing photomask, with existing douching technique, photosensitive film layer 3 is removed by the partial flushing that photomask 4 covers, to form the exposed hole 30 that exposes corresponding weld pad 11.Then, with existing plating mode, on the perisporium of each exposed hole 30, form the conduction connector 7 that is electrically connected and extends to photosensitive film layer 3 surfaces with corresponding pad 11.
Should be noted that when semiconductor chiop the 3rd embodiment makes with said method it is also the same with two embodiment as first, is suitable for being mounted on a substrate or another semiconductor chiop.Because its mode that is mounted to substrate or another semiconductor chiop is identical with first embodiment, repeats no more.
As shown in figure 15, its expression semiconductor chiop the 4th embodiment of the present invention.The embodiment of this semiconductor chiop also is suitable for being installed on a position with several solder joints and this solder joint and the position of the weld pad 11 of the chip 1 not corresponding substrate or another semiconductor chiop (not shown).Not existing together with first embodiment is, in the present embodiment, after forming conductive welding spots 5, is with the conducting metal glue material, is formed with electric conductor 8 on photosensitive film layer 3.In the present embodiment, conducting metal glue can be a kind of conducting metal glue in the conductive metallic materials such as being doped with gold, silver, copper, iron, tin and aluminium.Each electric conductor 8 has that a solder joint connecting portion that is electrically connected with corresponding conductive welding spots 5 800, one are electrically connected with solder joint connecting portion 800 and as extension 801 and a free end that is positioned at extension 801 of circuit trace, and its position electrical connection section 802 corresponding with the position of the corresponding solder joint of this substrate.
It should be noted that in the present embodiment, electric conductor 8 forms to print the son section.
Then, on the electrical connection section 802 of each electric conductor 8, form a connecting terminal 9 spherical as conducting metal with prior art.
As shown in figure 16, its expression semiconductor chiop the 5th embodiment of the present invention.The semiconductor chiop of present embodiment also is suitable for being installed on a position with several solder joints and solder joint and the position of the weld pad 11 of the chip 1 not corresponding substrate or another semiconductor chiop (not shown).Not existing together with second embodiment is in the present embodiment, after forming conductive welding spots 5, with the conducting metal glue material, to be formed with electric conductor 8 on photosensitive film layer 3.In the present embodiment, this conducting metal glue can be a kind of metal-to-metal adhesive in the conductive metallic materials such as being doped with gold, silver, copper, iron, tin and aluminium.Each electric conductor 8 has that a solder joint connecting portion that is electrically connected with corresponding conductive welding spots 5 800, one are electrically connected with solder joint connecting portion 800 and as the extension 801 and a free end that is positioned at extension 801 and its position electrical connection section 802 corresponding with the position of the corresponding solder joint of this substrate of circuit trace.
Should be noted that in the present embodiment this electric conductor 8 forms with printing means.
Then, on the electrical connection section 802 of each electric conductor 8, form one as the connecting terminal 9 as the conductive metal balls with prior art.
As shown in figure 17, the 6th embodiment of its expression semiconductor chiop of the present invention.The embodiment of this semiconductor chiop be suitable for being installed in a position with several solder joints and this solder joint be with the position of the weld pad 11 of chip 1 not corresponding substrate or another semiconductor chiop (not shown) on.Different with second embodiment is, in the present embodiment, after forming conduction connector 7, be with the conducting metal glue material, be formed with electric conductor 8 on photosensitive film layer 3, conducting metal glue can be a kind of conducting metal glue in the conductive metallic materials such as being doped with gold, silver, copper, iron, tin and aluminium.Each electric conductor 8 has a connecting portion that is electrically connected with corresponding conduction connector 7 800, was electrically connected and was positioned at as the extension and of circuit trace this extension with connector connecting portion 800 free end and its position electrical connection section 802 corresponding with the position of the corresponding solder joint of substrate.
Should be noted that in the present embodiment this electric conductor 8 forms to print the son section.
Then, on the electrical connection section 802 of each electric conductor 8, form one as the connecting terminal 9 as the conductive metal balls with prior art.
As shown in figure 18, its expression seventh embodiment of the invention.Different with the 4th embodiment, connecting terminal 9 is integrally formed with electric conductor 8.
As shown in figure 19, its expression eighth embodiment of the invention.Different with interior embodiment, connecting terminal 9 is integrally formed with electric conductor 8.
As shown in figure 20, its expression ninth embodiment of the invention.Different with the 4th embodiment, connecting terminal 9 is integrally formed with electric conductor 8.
Compared with prior art, the present invention has following effect:
Owing to be formed with conduction connector in the semiconductor chiop of the present invention, make it easy to and the outside Circuit is electrically connected, and then can improve the production efficiency of semiconductor chiop.
Claims (28)
1, a kind of method for packing of semiconductor chiop, this semiconductor chiop is suitable for being mounted on a substrate or another semiconductor chiop, this substrate or semiconductor chiop have a chip installation area territory, be provided with several solder joints in this chip installation area territory, it is characterized in that, comprise the steps:
Two semiconductor chips are provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
On the pad installation surface of chip, form a photosensitive film layer;
On photosensitive film layer, put two photomasks that cover this photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to these conductive contact parts;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed at least a portion by the flushing of photomask cover part, to form the exposed hole that at least the conductive contact head portion of correspondence is exposed;
With each exposed hole of tin cream filling;
Make the tin cream formation one of each exposed hole be suitable for the conductive welding spots that is electrically connected with the corresponding solder joint of substrate or another semiconductor chiop with the infrared ray mode of heating.
2, method for packing as claimed in claim 1, it is characterized in that, the position of the weld pad of described semiconductor chip does not correspond to the position of the solder joint of described substrate or another semiconductor chiop, and after the step with the infrared ray heating, more comprises following step:
With the conducting metal glue material, be formed with electric conductor on described photosensitive film layer, each electric conductor has that a solder joint connecting portion that is electrically connected with the corresponding conductive welding spots of described chip, one are electrically connected with the solder joint connecting portion and as the corresponding electrical connection section in position of the corresponding solder joint of the extension of circuit trace and a free end that is positioned at extension and its position and described substrate or other-semiconductor chiop.
3, method for packing as claimed in claim 2 is characterized in that, after forming the electric conductor step, more comprises the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
4, method for packing as claimed in claim 3 is characterized in that, in the step of described formation connecting terminal, described connecting terminal is conduction tin ball.
5, method for packing as claimed in claim 3 is characterized in that, in the step of described formation connecting terminal, described conductive contact and described electric conductor are integrally formed.
6, method for packing as claimed in claim 1 is characterized in that, on the semiconductor chip that is provided, described conductive contact is conduction tin ball.
7, method for packing as claimed in claim 2 is characterized in that, in the step of described formation electric conductor, conducting metal glue is the conducting metal glue that one of is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
8, method for packing as claimed in claim 1, it is characterized in that, in described chemical rinsing step, be that the part of utilizing the control washing time that photosensitive film layer is covered by photomask only is rinsed and removes a part, the exposed hole that exposes with the head portion that only forms the conductive contact of correspondence; After chemical rinsing step, this method also comprises step: again photosensitive film layer is carried out exposure-processed.
9, a kind of method for packing of semiconductor chiop, this semiconductor chiop is suitable for being mounted on a substrate or another semiconductor chiop, this substrate or semiconductor chiop have a chip installation area territory, in the chip installation area territory, be provided with several solder joints, it is characterized in that, comprise the steps:
A semiconductor chip is provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads, and the position of the weld pad of the semiconductor chip that is provided does not correspond to the position of the solder joint of described substrate or another semiconductor chiop;
On the pad installation surface of chip, form a photosensitive film layer;
On photosensitive film layer, put a weld pad photomask partly that covers photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to this chip;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed by the partial flushing that photomask covers, to form the exposed hole of the corresponding weld pad that exposes this chip;
With the plating means, on the perisporium of each exposed hole, form the conduction connector that is electrically connected and extends to the photosensitive film laminar surface with corresponding pad, these conduction connectors are suitable for being electrically connected with the corresponding solder joint of described substrate or another semiconductor chiop.
With the conducting metal glue material, form electric conductor on described photosensitive film layer, each electric conductor has that a connector connecting portion that is electrically connected with the corresponding conduction connector of this chip, one are electrically connected with the connector connecting portion and as the extension of circuit trace and a free end that is positioned at this extension and its position corresponding electrical connection section in position with the corresponding solder joint of described substrate or another semiconductor chiop.
10, method for packing as claimed in claim 9 is characterized in that, after the step of described formation electric conductor, also comprises the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
11, method for packing as claimed in claim 10 is characterized in that, in described formation connecting terminal step, described connecting terminal is conduction tin ball.
12, method for packing as claimed in claim 10 is characterized in that, in the step of described formation connecting terminal, described conductive contact is integrally formed with described electric conductor.
L3, method for packing as claimed in claim 9 is characterized in that, in described formation electric conductor step, conducting metal glue is the conducting metal glue that one of is doped with in the conducting metals such as gold, silver, copper, iron, tin and aluminium.
14, a kind of method for packing of semiconductor chiop is characterized in that, comprises the steps:
A semiconductor chip is provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
On the pad installation surface of chip, form a photosensitive film layer;
On this photosensitive film layer, put a photomask that covers this photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to this conductive contact part;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed at least a portion by the partial flushing that photomask covers, to form the exposed hole that at least head portion of the conductive contact of correspondence is exposed;
With each exposed hole of tin cream filling;
Make the tin cream of each exposed hole form a conductive welding spots with the infrared ray heating;
A substrate is provided, and this substrate has a chip installation area territory, is provided with the solder joint that several are electrically connected with the corresponding conductive welding spots of described chip in this chip installation area territory.
15, a kind of method for packing of semiconductor chiop is characterized in that, comprises the steps:
A semiconductor chip is provided, and this semiconductor chip has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
On the pad installation surface of chip, form a photosensitive film layer;
On this photosensitive film layer, put a photomask that covers photosensitive film layer, and this photosensitive film layer is carried out exposure-processed corresponding to this conductive contact part;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed at least a portion by the partial flushing that photomask covers, to form the exposed hole that at least head portion of the conductive contact of correspondence is exposed;
With each exposed hole of tin cream filling;
Make the tin cream of each exposed hole form a conductive welding spots with the infrared ray heating;
A semiconductor chiop is provided, and this semiconductor chiop has a chip installation area territory, is provided with the solder joint that several are electrically connected with the corresponding conductive welding spots of chip in this chip installation area territory.
16, a kind of semiconductor chiop, it is suitable for being mounted on a substrate or another semiconductor chiop, and this substrate or semiconductor chiop have a chip installation area territory, are provided with several solder joints in the chip installation area territory; It is characterized in that, comprising:
A semiconductor chip, it has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
Photosensitive film layer on pad installation surface that is formed on chip, this photosensitive film layer is formed with several in order to expose the exposed hole of the head portion of corresponding conductive contact at least corresponding to the conductive contact place;
Each exposed hole is filled with the tin cream that is suitable for the conductive welding spots that is electrically connected with corresponding solder joint.
17, device as claimed in claim 16 is characterized in that, the bond pad locations of described semiconductor chip does not correspond to the position of the solder joint of described substrate or another semiconductor chiop; Also comprise:
Several are formed on the electric conductor on the described photosensitive film layer, and each electric conductor has that a solder joint connecting portion that is electrically connected with corresponding conductive welding spots, one are electrically connected with the solder joint connecting portion and as the extension and a free end that is positioned at this extension and its position electrical connection section corresponding with the position of the solder joint of described substrate or another semiconductor chiop of circuit trace.
18, device as claimed in claim 17 is characterized in that, also comprises the connecting terminal on the electrical connection section that is formed on described electric conductor.
19, device as claimed in claim 18 is characterized in that, described connecting terminal is conduction tin ball.
20, device as claimed in claim 18 is characterized in that, described connecting terminal and described electric conductor are integrally formed.
21, device as claimed in claim 16 is characterized in that, described conductive contact is conduction tin ball.
22, device as claimed in claim 17 is characterized in that, described electric conductor is formed by conducting metal glue, and conducting metal glue is the conducting metal glue that one of is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
23, a kind of semiconductor chiop, it is suitable for being mounted on a substrate or another semiconductor chiop, and this substrate or semiconductor chiop have a chip installation area territory, are provided with several solder joints in the chip installation area territory, it is characterized in that, comprising:
A semiconductor chip, it has a pad installation surface that is provided with several weld pads, and the position of described weld pad does not correspond to the position of the solder joint of described substrate or another semiconductor chiop;
A photosensitive film layer that is formed on the pad installation surface, photosensitive film layer is formed with several in order to expose the exposed hole of corresponding weld pad corresponding to the weld pad of this semiconductor chip;
Be formed on the conduction connector that is electrically connected and extends to the photosensitive film laminar surface on the perisporium of each exposed hole with the corresponding weld pad of this chip, this conduction connector is suitable for and the electrical connection of corresponding solder joint; And
Several are formed on the electric conductor on the described photosensitive film layer, and each electric conductor has that a connector connecting portion that is electrically connected with the corresponding conduction connector of described chip, one are electrically connected with the connector connecting portion and as the extension and a free end that is positioned at extension and its position electrical connection section corresponding with the position of the corresponding solder joint of described substrate or another semiconductor chiop of circuit trace.
24, device as claimed in claim 23 is characterized in that, also comprises the connecting terminal on the electrical connection section that is formed on each electric conductor.
25, device as claimed in claim 24 is characterized in that, described connecting terminal is conduction tin ball.
26, device as claimed in claim 24 is characterized in that, described connecting terminal is integrally formed with described electric conductor.
27, device as claimed in claim 23 is characterized in that, electric conductor is to be formed by conducting metal glue, and conducting metal glue is the conducting metal glue that one of is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
28, a kind of semiconductor chiop is characterized in that, comprising:
A semiconductor chip, it has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
A photosensitive film layer that is formed on the pad installation surface, this photosensitive film layer is formed with several in order to expose the exposed hole of the head portion of corresponding conductive contact at least corresponding to this conductive contact;
Each exposed hole is filled with the tin cream as conductive welding spots;
A substrate, it has a chip installation area territory, is provided with the solder joint that several conductive welding spots corresponding with chip are electrically connected in this chip installation area territory.
29, a kind of semiconductor chiop is characterized in that, comprising: a semiconductor chip, and it has a pad installation surface that is provided with several weld pads, is formed with a conductive contact on each weld pad;
A photosensitive film layer that is formed on the pad installation surface, this photosensitive film layer is formed with several in order to expose the exposed hole of the head portion of corresponding conductive contact at least corresponding to this conductive contact;
Each exposed hole is filled with the tin cream as conductive welding spots;
A semiconductor chiop, it has a chip installation area territory, is provided with the solder joint that several are electrically connected with the corresponding conductive welding spots of this chip in the chip installation area territory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011026065A CN1276491C (en) | 2001-02-02 | 2001-02-02 | Semiconductor chiop and its packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011026065A CN1276491C (en) | 2001-02-02 | 2001-02-02 | Semiconductor chiop and its packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1368758A CN1368758A (en) | 2002-09-11 |
| CN1276491C true CN1276491C (en) | 2006-09-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011026065A Expired - Fee Related CN1276491C (en) | 2001-02-02 | 2001-02-02 | Semiconductor chiop and its packaging method |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100350578C (en) * | 2004-03-02 | 2007-11-21 | 沈育浓 | Packaging method for semiconductor wafer package |
| CN100431174C (en) * | 2004-03-16 | 2008-11-05 | 联华电子股份有限公司 | A packaging structure with a chip above a photosensitive element and electric packaging structure thereof |
| US9214454B2 (en) * | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
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2001
- 2001-02-02 CN CNB011026065A patent/CN1276491C/en not_active Expired - Fee Related
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| CN1368758A (en) | 2002-09-11 |
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