CN1172358C - Overlapped chip binding structure and generating method - Google Patents
Overlapped chip binding structure and generating method Download PDFInfo
- Publication number
- CN1172358C CN1172358C CNB021285977A CN02128597A CN1172358C CN 1172358 C CN1172358 C CN 1172358C CN B021285977 A CNB021285977 A CN B021285977A CN 02128597 A CN02128597 A CN 02128597A CN 1172358 C CN1172358 C CN 1172358C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The present invention relates to a flip-chip joint structure and a generating method thereof. When the method of the present invention is used, volume mini bumps are formed on a metal layer under solder bumps of a wafer, the number of voids near an interface of the metal layer under solder bumps in the solder bump can be minimized, the volume can be minimized, and the reliability of the soldering joint can be increased; in addition, the volume of soldering flux which is filled in a squeegee printing mode on the wafer is small, and therefore, generated voids can escape easily; generation positions of the solder bumps on a substrate and the solder bumps on the wafer can be accurately positioned in a laser opening mode or an electric slurry etching process, the solder bumps can be accurately formed on a bump pad on the substrate and the metal layer under solder bumps on the wafer, and pitches between solder bumps can be reduced to form solder bumps in high concentration and with fine pitches.
Description
Technical field
The present invention is about a kind of flip-chip bonded structure and formation method, particularly a kind of flip-chip bonded structure and formation method with the highly dense intensity weld pad of thin space.
Background technology
The semiconductor chip that contains integrated circuit is an epochmaking assembly in the electronic installation.These semiconductor chips are fixed on one usually to have on the ground of terminal to connect other external circuit.This ground can be single-layer metal lead frame or multilayer printed circuit board.Except the connection that other external circuit of semiconductor chip is provided, ground also provides mechanical support.The outside of semiconductor chip coats can protect semiconductor chip not to be subjected to the influence of external environment and external impacts.
Figure 1A to Fig. 1 G shows a kind of projection formation method of conventional package technology.Shown in Figure 1A, show the assembly encapsulation structure before a soldering projection forms, this assembly encapsulation structure comprises an assembly 100, a weld pad 102 (Pad), a passivation layer 104 (Passivation Layer) and a soldering projection lower metal layer 106 (Under Bump Metal).Shown in Figure 1B,, must form a photoresist layer 108 on the structure shown in Figure 1A in order to form soldering projection on soldering projection lower metal layer 106.Then shown in Fig. 1 C, with lithography process with photoresist layer 108 exposure imagings to expose soldering projection lower metal layer 106, make soldering projection can be formed at soldering projection lower metal layer 106.Then shown in Fig. 1 D, one soldering projection (Solder Bump) 110 is formed on the soldering projection lower metal layer 106, and general process of electroplating is complicated and permanent manufacturing cost consuming time is higher with electroplating technique.The another kind of soldering projection that forms is to utilize steel version (Stencil Mask) solder(ing) paste to be utilized print process insert opening on the steel version in the method on the soldering projection lower metal layer 106, and prerequisite is that the pattern on the steel version must accurately be aimed at soldering projection lower metal layer 106.Also having a kind of method of soldering projection on soldering projection lower metal layer 106 that form is to utilize printing (the Photo Film Defined Printing) mode of a kind of photoresistance film definition, but is subject to the resolution of photoresistance film (Photo Film) and is unsuitable for forming the soldering projection of high aspect ratio (High Aspect Ratio) thin space (Fine Pitch).
Remove the result of photoresist layer 108 behind Fig. 1 E demonstration formation soldering projection 110.And Fig. 1 F shows that etching soldering projection lower metal layer 106 is to expose the result of passivation layer 104.Before formally welding, after the heating of reflow (Reflow) technology, the kenel that soldering projection 110 forms shown in Fig. 1 G.
The projection formation method of above-mentioned conventional package technology has following multinomial shortcoming.Projection formation method shown in Figure 1A to Fig. 1 G has been used consuming time and expensive electroplating technology, aims at difficult and steel version cost height and use the steel version to form soldering projection.The mode of the printing (Photo Film Defined Printing) of photoresistance film definition is subject to the resolution of photoresistance film (Photo Film) and is unsuitable for forming the soldering projection of high aspect ratio (High Aspect Ratio) thin space in addition.
Summary of the invention
Because the shortcoming of above-mentioned conventional package structure and technology, therefore be necessary to develop and a kind of novel structure that improves and technology to overcome the shortcoming of traditional structure and technology.
A purpose of the present invention is the flip-chip bonded structure and the formation method that a kind of low cost and technology are provided simplify and the technology required time is short.
Another object of the present invention is for providing high high-resolution flip-chip bonded structure of a kind of alignment accuracy and formation method.
Another object of the present invention is for providing a kind of flip-chip bonded structure and formation method that forms little soldering projection of size and soldering projection spacing.
In order to reach above-mentioned purpose, the invention provides a kind of flip-chip bonded structure formation method, this flip-chip bonded structure formation method comprises following steps.One substrate and a wafer at first are provided, wherein have a plurality of first weld pads and first dielectric layer on this substrate, have passivation layer and a plurality of soldering projection lower conductor layer that be positioned at this second weld pad on of a plurality of first openings to expose this second weld pad and have a plurality of second weld pads, on this wafer.Then the pattern that shifts a plurality of first soldering projections with a vertical direction perforate method for processing enters this first dielectric layer forming a plurality of second openings and to expose this first weld pad, and scolder is inserted this second opening.Then this substrate is carried out reflow process to form a plurality of first soldering projections.Remove this first dielectric layer and this first soldering projection is carried out one and flatten technology.Form non-sensing optical activity second dielectric layer and cover this wafer, the pattern that shifts a plurality of second soldering projections by a vertical direction perforate method for processing enters this dielectric layer to form a plurality of the 3rd openings and to expose this soldering projection lower conductor layer.Scolder is inserted the 3rd opening, and this wafer carried out a reflow process to form a plurality of second soldering projections, wherein the thickness of first dielectric layer is greater than the thickness of second dielectric layer, and therefore second soldering projection is the less minute bumps of volume (Mini-Bump).After substrate and wafer cut into unit substrate and chip, aim at this a plurality of first soldering projections with this substrate of solder bond and this chip with these a plurality of second soldering projections, encapsulate again at last and fix this substrate and this chip.
Form the flip-chip bonded encapsulating structure of a preferred embodiment of the present invention with flip-chip bonded structure formation method of the present invention, this flip-chip bonded encapsulating structure comprises a substrate, have a plurality of first weld pads on this substrate, first soldering projection that has a plurality of top flat on these a plurality of first weld pads; One chip, have a plurality of second weld pads on this chip, one has passivation layer and a plurality of soldering projection lower conductor layer that be positioned at this second weld pad on of a plurality of openings to expose this second weld pad, one non-sensing optical activity dielectric layer covers this passivation layer and exposes this a plurality of soldering projection lower conductor layer, a plurality of second soldering projections are positioned on these a plurality of soldering projection lower conductor layer, wherein the height of this first soldering projection is greater than this second soldering projection, and these a plurality of first soldering projections are aimed at electrical combination of welding individually with these a plurality of second soldering projections, make this substrate and this chips incorporate; Reach an encapsulation filler and fill up between this substrate and this chip, fix this substrate and this chip with encapsulation.
Description of drawings
Figure 1A shows the assembly encapsulation structure before a soldering projection forms;
Figure 1B shows the result of formation one photoresist layer on the assembly encapsulation structure shown in Figure 1A;
Fig. 1 C shows that exposure shows photoresist layer to expose the result of soldering projection lower metal layer;
Fig. 1 D shows the result of formation one soldering projection on the soldering projection lower metal layer;
Fig. 1 E shows the result who removes photoresist layer;
Fig. 1 F shows that etching soldering projection lower metal layer is to expose the result of passivation layer;
Fig. 1 G shows the result of soldering projection through reflow;
Fig. 2 A show have on the substrate a plurality of flip-chip bonded convex pads with a dielectric layer;
Fig. 2 B shows that etching dielectric layer is to expose the result of substrate and flip-chip bonded convex pads;
Fig. 2 C shows scolder is inserted the result that scolder that the opening Inner ， And Will that exposes convex pads overflows removes;
Fig. 2 D shows the result who the scolder shown in Fig. 2 C is formed soldering projection through reflow process;
Fig. 2 E demonstration removes the dielectric layer shown in Fig. 2 D, and soldering projection is flattened the result of technology;
Fig. 3 A shows that the present invention comprises the wafer part assembly encapsulation structure of integrated circuit (IC) chip;
Fig. 3 B shows that etching dielectric layer is to form the result that Kai Kou And exposes the soldering projection lower metal layer;
Fig. 3 C shows scolder is inserted the result that scolder that the opening Inner ， And Will that exposes the projection lower metal layer overflows removes;
Fig. 4 A shows and will carry out the result that the flip chip bonding access node closes after the cutting of the wafer shown in the substrate shown in Fig. 2 E and Fig. 3 C;
Fig. 4 B demonstration fills moulding compound or upside-down mounting with the result that (Underfill) thing is inserted structure shown in Fig. 4 A.
Symbol description among the figure
100 assemblies
102 weld pads
104 passivation layers
106 soldering projection lower metal layers
The welding of 108 photoresist layers
110 projections
200 substrates
202 flip-chip bonded convex pads
204 dielectric layers
206 scolders
208 soldering projections
300 chips
302 weld pads
304 passivation layers
306 soldering projection lower metal layers
308 dielectric layers
310 soldering projections
400 moulding compounds or upside-down mounting filler
Embodiment
In this mandatory declaration is that processing step described below and structure do not comprise complete technology.The present invention can be implemented by various processes, only mentions at this and understands process required for the present invention.
Below accompanying drawing according to the present invention is described in detail, please notes that icon is simple form and, and size all is beneficial to understand the present invention by exaggerative not according to scaling.
In preferred embodiment of the present invention, flip-chip bonded structure and formation method are applied on flip-chip packaged (the Flip Chip Package) technology.Fig. 2 A to Fig. 2 E and Fig. 3 A to Fig. 3 C show respectively in the preferred embodiment of the present invention relevant for substrate (Substrate) partly and comprise the wafer technology partly of integrated circuit (IC) chip, Fig. 4 A to Fig. 4 B is unit of display substrate and flip-chip joint technology and structure then.
Shown in figure 2A, have a plurality of flip-chip bonded convex pads (FlipChip Bump Pad) 202 and one dielectric layer 204 on the substrate 200, wherein also can have weld-proof membrane (Solder Mask) (not shown) on the substrate 200.Flip-chip bonded convex pads 202 can be traditional materials and methods form.This dielectric layer 204 is preferable with a release film (Release Film).And release film is the used dielectric film of general packaging technology, prevents that with what substrate from polluted by external environment condition in being transported to the process of subsequent technique.The release film that the present invention uses then defines the formation position of soldering projection on the substrate and peelable removing after technology is finished with what.
Then, show that etching dielectric layer 204 is to expose the result of substrate 200 and flip-chip bonded convex pads 202 with reference to shown in the figure 2B.Dielectric layer 204 is a release film, and the mode of etching dielectric layer 204 is vertical direction perforate method for processing, for example anisotropic etching method.Particularly remove part on the release film position what convex pads 202, to form opening (Opening) with the mode of laser beam drilling (Laser) or the technology of plasma etching (Plasma Etching).Utilize laser beam drilling or plasma etching can reach the opening that high-resolution is accurately aimed at, soldering projection can accurately be formed on the convex pads; can further dwindle the spacing (Pitch) of soldering projection, and successfully form the soldering projection of high aspect ratio (high Aspect Ratio) the highly dense intensity of thin space with Time.
Shown in figure 2C, show scolder 206 inserted the opening Inner that exposes convex pads 202 in the mode of scraper printing (Squeegee Printing) that the scolder that And Will overflows removes.Scolder 206 comprises soldering paste or tiny soldered balls (Solder Paste/Solder Powder), and soldering paste or tiny soldered balls soldering paste be by many tiny soldered balls (Solder Sphere), solvent and help weldering (melting) agent (Flux) to constitute, and soldered ball is generally the leypewter of eutectic composition.Then with reference to shown in the figure 2D, the soldering projection 208 of scolder 206 shown in Fig. 2 C in solidifying (Curing) and/or reflow (Reflow) technology formation figure, when using tiny soldered balls then must after printing, add scaling powder again before the reflow, so the soldered ball bubble can be reduced to minimum.
Shown in figure 2E, release film dielectric layer 204 shown in Fig. 2 D is removed, after release film 204 removes, substrate is carried out a dry etch process cleaning base plate surface, and soldering projection 208 is once flattened (Coining) technology make soldering projection 208 top flattenings and preferable coplanarity is arranged in order to engaging with soldering projection on the wafer.In addition, flattening before technology makes soldering projection 208 top flattenings, also can carry out one time reflow process again.
Fig. 3 A to Fig. 3 C shows in the preferred embodiment of the present invention relevant for the wafer that comprises integrated circuit (IC) chip technology partly.At first with reference to shown in the figure 3A, show that the present invention comprises the wafer part assembly encapsulation structure of integrated circuit (IC) chip, this wafer partly assembly encapsulation structure comprises chip 300, weld pad 302 (Metal Pad), passivation layer 304 (Passivation Layer), soldering projection lower metal layer 306 (Under Bump Metal) and a dielectric layer 308.Weld pad 302 comprises aluminium welding pad, but other material weld pad also should not be excluded.Weld pad 302 can be traditional deposition, little shadow and etch process form.Passivation layer 304 can be formed by conventional method.Passivation layer 304 forms opening and exposes weld pad 302 with traditional little shadow and etch process.Soldering projection lower metal layer 306 is formed in the opening with traditional deposition, little shadow and etch process and reaches on the weld pad 302.Dielectric layer 308 comprises non-photosensitive type dielectric material and preferable with a release film, the thickness of the little what aforesaid base plate of its thickness upper dielectric layer 204.
Then, open a mouthful And with the mode etching dielectric layer 308 of vertical direction perforate processing with formation and expose soldering projection lower metal layer 306 with reference to shown in the figure 3B.This vertical direction perforate method for processing comprises laser beam drilling or method for plasma etching.Utilize the technology of plasma etching form opening must Shall what release film on Should etching shade.Utilize laser beam drilling or plasma etching can reach the opening that high-resolution is accurately aimed at, make soldering projection can accurately be formed on the projection lower metal layer; can further dwindle the spacing of soldering projection, and successfully form the soldering projection of the highly dense intensity of thin space with Time.With reference to shown in the figure 3C, scolder is inserted the opening Inner that exposes projection lower metal layer 306 in the mode of scraper printing (Squeegee Printing) then, the scolder that And Will overflows removes.Scolder comprises soldering paste or tiny soldered balls (Solder Paste/SolderPowder).Soldering paste is by many tiny soldered balls (Solder Sphere), solvent and help weldering (melting) agent (Flux) to constitute, and soldered ball is generally the leypewter of eutectic composition.Small soldering projection or the mini projection (Mini-Bump) 310 of scolder in reflow (Reflow) technology formation figure, because the thickness of dielectric layer 308 is less with respect to the thickness of dielectric layer in the technology on the substrate 204, so the volume of formed soldering projection is less relatively on the wafer.When using tiny soldered balls then must after printing, add scaling powder again before the reflow, so the soldered ball bubble can be reduced to minimum.Then dielectric layer 308 can be removed and also can not remove ， And and can use dry-etching or electricity slurry clean surface.
Fig. 4 A to Fig. 4 B shows in the preferred embodiment of the present invention relevant for substrate part and wafer part flip-chip bonded technology and structure.The substrate shown in Fig. 2 E is cut and the wafer shown in Fig. 3 C is cut into chip (Chip) afterwards in advance, shown in figure 4A, carry out flip-chip packaged technology, the soldering projection 208 of unit substrate is aimed at the small soldering projection 310 of chips.Fig. 4 B then shows the result that (Underfill) thing 400 is inserted structure shown in Fig. 4 A is filled in moulding compound (Molding Compound) or upside-down mounting, to finish the flip-chip bonded structure.
Generally speaking, in upside-down mounting soldering projection technology, be difficult to avoid the generation of emptying aperture (Void), and the cavity is big than edge of substrate for the influence of die terminals, for effectively promoting the reliability of solder joints, in the present invention, because the thickness of applied dielectric layer 308 is little with respect to the thickness of dielectric layer used in the technology on the substrate 204 on the wafer, so the volume of formed soldering projection is less relatively on the wafer, and the formation mini projection of volume (Mini Bump), and the volume of solder of inserting with the scraper printing on wafer in the technology is less, the emptying aperture that produces because of the scraper printshop is easier to overflow, therefore can will reduce to minimum near emptying aperture (Void) quantity of soldering projection lower metal layer interface in the soldering projection and volume reduces to minimum, so can increase the reliability of solder joints.Utilize the mode of laser beam drilling or the technology of plasma etching accurately to locate the soldering projection on the substrate and the formation position of the soldering projection on the wafer simultaneously, can form the opening that high-resolution is accurately aimed at by what dielectric layer Inner, make soldering projection can accurately be formed at the spacing that Tong Time can further dwindle soldering projection on convex pads on the substrate and the soldering projection lower metal layer on the wafer, and successfully form the soldering projection of the highly dense intensity of thin space, can overcome simultaneously and use steel version (Stencil Mask) to form the aligning that soldering projection caused to be difficult for and the expensive problem of steel version (StencilMask), and printing (the Photo FilmDefined Printing) mode that solves traditional photoresistance film definition is subject to the resolution of photoresistance film (Photo Film) and is difficult to form the problem of the soldering projection or the weld pad of thin space.In addition, the opening Inner that utilizes soldering paste or tiny soldered balls to insert highly dense intensity of thin space and the accurate aligning of high-resolution can solve tradition with the consuming time and expensive problem of galvanoplastic formation soldering projection to form soldering projection.
Above-mentioned relevant detailed description of the invention only is an example and unrestricted.Other equivalence that does not break away from spirit of the present invention changes or modifies within the scope of the claims of the present invention that all should be included in.
Claims (10)
1. a flip-chip bonded structure formation method is characterized in that, comprises:
One substrate and a wafer are provided, wherein have a plurality of first weld pads and a release film on this substrate, have a plurality of first openings with the passivation layer that exposes this second weld pad, and a plurality of soldering projection lower conductor layer that are positioned on this second weld pad and have a plurality of second weld pads, on this wafer;
The pattern that shifts a plurality of first soldering projections with vertical direction perforate method for processing enters this release film to form a plurality of second openings and to expose this first weld pad;
Scolder is inserted this second opening;
This substrate is carried out reflow process to form a plurality of first soldering projections;
Remove this release film;
This first soldering projection is carried out one flatten technology;
Form a non-sensing optical activity dielectric layer and cover this wafer, wherein the thickness of this non-sensing optical activity dielectric layer is less than the thickness of this release film;
The pattern that shifts a plurality of second soldering projections by vertical direction perforate method for processing enters this dielectric layer to form a plurality of the 3rd openings and to expose this soldering projection lower conductor layer;
Scolder is inserted the 3rd opening;
This wafer is carried out a reflow process to form a plurality of second soldering projections;
Cut this substrate, to form a plurality of unit substrate;
Cut this wafer to form a plurality of chips;
Aim on this unit substrate a plurality of first soldering projections with this unit substrate of solder bond and this chip with a plurality of second soldering projections on this chip; And
This unit substrate and this chip are fixed in encapsulation.
2. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, this above-mentioned vertical direction perforate method for processing comprises the laser beam drilling method.
3. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, this above-mentioned vertical direction perforate method for processing comprises method for plasma etching.
4. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that this above-mentioned scolder is inserted in the mode of scraper printing.
5. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that this above-mentioned scolder comprises soldering paste.
6. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that this above-mentioned scolder comprises soldered ball.
7. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, after this above-mentioned release film removes, this substrate is carried out a dry etch process clean this substrate surface.
8. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, after this above-mentioned release film removes, more comprises this substrate is carried out a reflow process.
9. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, this above-mentioned unit substrate and this chip are fixing with the moulding compound encapsulation.
10. flip-chip bonded structure formation method as claimed in claim 1 is characterized in that, this above-mentioned unit substrate and this chip are fixing with the encapsulation of upside-down mounting filler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021285977A CN1172358C (en) | 2002-08-13 | 2002-08-13 | Overlapped chip binding structure and generating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021285977A CN1172358C (en) | 2002-08-13 | 2002-08-13 | Overlapped chip binding structure and generating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1396641A CN1396641A (en) | 2003-02-12 |
| CN1172358C true CN1172358C (en) | 2004-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021285977A Expired - Lifetime CN1172358C (en) | 2002-08-13 | 2002-08-13 | Overlapped chip binding structure and generating method |
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| CN (1) | CN1172358C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI661523B (en) * | 2017-07-28 | 2019-06-01 | 日商愛立發股份有限公司 | Device for mounting columnar member and method for mounting columnar member |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100372104C (en) * | 2004-09-07 | 2008-02-27 | 日月光半导体制造股份有限公司 | Substrate plated with enhanced welding pad structure |
| US7416104B2 (en) | 2006-04-21 | 2008-08-26 | International Business Machines Corporation | Rotational fill techniques for injection molding of solder |
| US7410090B2 (en) | 2006-04-21 | 2008-08-12 | International Business Machines Corporation | Conductive bonding material fill techniques |
| US7410092B2 (en) | 2006-04-21 | 2008-08-12 | International Business Machines Corporation | Fill head for injection molding of solder |
| US9314864B2 (en) | 2007-07-09 | 2016-04-19 | International Business Machines Corporation | C4NP compliant solder fill head seals |
| US11213690B2 (en) * | 2012-06-15 | 2022-01-04 | Medtronic, Inc. | Wafer level packages of high voltage units for implantable medical devices |
| US8824161B2 (en) | 2012-06-15 | 2014-09-02 | Medtronic, Inc. | Integrated circuit packaging for implantable medical devices |
| CN103794515B (en) * | 2012-10-30 | 2016-12-21 | 碁鼎科技秦皇岛有限公司 | Chip package base plate and structure and preparation method thereof |
| JP2015012005A (en) * | 2013-06-26 | 2015-01-19 | ソニー株式会社 | Semiconductor device |
-
2002
- 2002-08-13 CN CNB021285977A patent/CN1172358C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI661523B (en) * | 2017-07-28 | 2019-06-01 | 日商愛立發股份有限公司 | Device for mounting columnar member and method for mounting columnar member |
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| CN1396641A (en) | 2003-02-12 |
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