CN1270375C - Solvent assisted burnishing of pre-underfilled solder-bumped wafers for flipchip bonding - Google Patents

Solvent assisted burnishing of pre-underfilled solder-bumped wafers for flipchip bonding Download PDF

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Publication number
CN1270375C
CN1270375C CNB018173675A CN01817367A CN1270375C CN 1270375 C CN1270375 C CN 1270375C CN B018173675 A CNB018173675 A CN B018173675A CN 01817367 A CN01817367 A CN 01817367A CN 1270375 C CN1270375 C CN 1270375C
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China
Prior art keywords
adhesive
chip
projection
integrated circuit
conductivity
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CNB018173675A
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Chinese (zh)
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CN1470068A (en
Inventor
P·B·霍格通
K·Y·陈
J·A·格伯
R·L·D·泽纳
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3M Innovative Properties Co
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3M Innovative Properties Co
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Priority claimed from US09/690,600 external-priority patent/US7170185B1/en
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

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Abstract

The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of pre-applying adhesive directly to a bumped side of an integrated circuit chip. The method also includes the steps of removing portions of the adhesive from the tips of the solder bumps to expose a contact surface, and pressing the bumped side of the integrated circuit chip, which has previously been coated with adhesive, against the circuit substrate such that the bumps provide an electrical connection between the integrated circuit chip and the circuit substrate. The adhesive is removed from the tips of the solder bumps using a solvent assisted wiping action. The pre-applied adhesive on the chip forms a bond between the integrated circuit chip and the circuit substrate.

Description

The method of attachment of integrated circuit (IC) chip and circuit substrate and application thereof
Invention field
The present invention relates to be used for preparing the solder projection integrated circuit (IC) chip of filling out the end in advance and be connected to method on the circuit substrate.More particularly, the present invention relates to after the adhesive film that will fully fill up is pressed in the integrated circuit (IC) chip of solder projection as end packing layer, make solder projection exposed, make solder projection can between integrated circuit (IC) chip and its encapsulated circuit, form conductivity and connect.
Background of invention
In the world today, a large amount of electronic-circuit devices use integrated circuit (IC) chip that is contained in the protectiveness encapsulation.These are encapsulated as chip and machinery are provided, are the protection of calorifics aspect sometimes, and being connected to each other of medium level between chip and the printed circuit board (PCB) also is provided simultaneously.Permitted to compare chip size many years ago, the size of encapsulation is very big.Because it is very big that the feature sizes that printed circuit board (PCB) (PCB) can reach is compared chip, so be essential on this point part.After this, the ability of making the circuit board of fine-feature improves, and package dimension is with respect to the size correspondingly reduction of IC.But,, just required to develop circuit package method and the required technology of manufacturing function device that a kind of materials used is tried one's best few owing to need cutting down cost, reduce the size of circuit and improve performance.
A kind of technology of reducing circuit size and improving performance of being used to, relate to use the scope that is installed in the solder ball on the chip surface or area array directly with the IC device attached on the substrate.By upset or " upside-down mounting " chip described solder ball is contacted with on-chip pad, and whole assembly is passed through the scolder reflow process, IC can be metallurgically bonded in the substrate.Before though flip chip technology at first was created at more than 30 year, successful Application in a handful of different field of electronics industry only.Use the most significant example of electronic product of flip chip technology to comprise wrist-watch, vehicle sensors/controller and host computer.Being characterized as of these purposes requires computing capability (main frame) high in very-close-coupled circuit size (wrist-watch, vehicle) or the unit volume.This point lay special stress on following simple fact: because the encapsulation of the IC in the middle of having eliminated, flip chip technology makes and forms minimum possible silicon vestige on the circuit board.
Flip chip technology is the fundamental cause of extensive use more, is because as its situation about developing at present, the technology and the equipment requirements of this method are high.As a result, the flip chip technology implementation cost is very high, and many problems appear in regular meeting.In addition, it states the limit that application technology and performance requirement have reached present material.
Existing flip chip technology uses the chip that in advance scolder has been applied on the interconnection pad.Scolder is 95Pb-5Sn or 63Sn-37Pb alloy normally, and before final plate assembling, flows the projection that forms near " sphere " usually again.
The assemble method that the flip-over type chip assembly is general relates to following steps: 1) the flux slurry is applied on the substrate bonding pad; 2) with IC to placing on the substrate well, this moment, the viscosity of flux was fixing on the throne with chip; 3) make described device through reflow furnace, scolder just fusing also is attached on the substrate pad metallurgically; 4) make the cleaning operation of sample through flux.Removing usually of flux carried out with solvent clean.Originally, need to use chlorinated solvent to remove the flux residue, still, further developing of flux chemistry can be used the solvent that is more suitable for recently.
Then, the described flip-over type chip assembly of finishing must keep the energising continuity in accelerated test such as thermal cycle and the measured device of thermal shock in useful life.When the thermal cycle of circuit experience, not matching of thermal coefficient of expansion between silicon dioxide IC and the PCB (CTE) and modulus of elasticity (E) can contact the big stress of joint area generation.After repeated temperature circulation, it is tired that these stress can cause solder joints to take place, Here it is the main failure cause of flip-over type joint.This reason has high-modulus and low CTE with the selection major limitation of substrate material, and performance classes is similar to the ceramic hybrid substrate such as the Al of silicon dioxide 2O 3Even the use ceramic substrate, the flip-over type chip assembly still is confined to the purposes of little chip block.
At nearest 10-15, grasp the interest that how this flip-over type chip assembly is used for large chip more and wider printed substrate and improve just day by day.Especially now the organic group substrate high wiring density that can reach makes them become the low replacement thing of the suitable cost of ceramic substrate.But, the CTE that organic material is high has relatively slowed down the organic substrate flip-chip device because of above-mentioned failure mechanism application.An important breakthrough is to use the technology of end filler.Filler technology of the described end is to use the high-modulus curable adhesive to fill the space between the solder ball under the chip, and the stress of joint is shared by adhesive, and distributes more equably on total inner surface, rather than concentrates on the periphery of bead.The use of above-mentioned " end is filled out " adhesive can make flip chip technology (fct) be used for installing widely.
In present practice, the resin that the end is filled out is to apply as liquid, makes it to wick into below the assembly of stream by capillarity again.Therefore, such sealing is commonly referred to " filling out at the bottom of the capillary ".Revolve at present and add the step of filling out resin and separate, append to and above-mentionedly always sting in the step with total process steps with cured base.Stream and flux thing are removed after the step again, the assembly of dry adhesion in advance, preheating it (to promote core sucting action) is provided and delivered resin, make resin wick into chip below, and the resin of providing and delivering once more solidifies it then.Fill out resin and need reach 2 hours 150 ℃ of curing at the end that can get at present.In order to ensure can entrapped air under chip and guarantee around chip, to form good end filler shape, also need extra dispensing step.Exploitation and maintenance are very difficult to the good control of this material behavior and dispensing technology, and, need only defectiveness, all can damage the reliability of solder joints.And, though still the capillary end fill out and be extensive use of, but the IC designer trends of bigger IC size and pad step pitch (pitch) reduce can increase the required time of wicking and the appearance of defective.
Recently, developed the another kind of method of filling out resin in the end that applies, promptly before placing chip, in fact uncured liquid resin has been provided and delivered.Use liquid resin to replace above-mentioned flux slurry in this case, and developed special adhesive preparation, they can provide the effect of flux in reflow furnace before beginning is significantly solidified.Such material often is called " end filler does not flow ", and this is owing to cancelled the Capillary Flow step.Can use the special adhesive preparation that to a certain degree flux effect can be provided when solidifying in reflow furnace.Because resin is positioned on the plate before placing chip, chip must be pressed in the resin down, thereby the resin at displacement contact position place.This method is very attractive, because it eliminates the step of cleaning, dispensing and the wicking of flux.But, verified, can use in order to make this method, the resin that the end is filled out must not fill up.Can not fill out the end of in this method and use filler in the resin is to limit it to handle the limiting factor of using in large-scale IC size and the meticulous step pitch.For example visible U.S. Patent No. 5,128,746 (Shi etc.), High Performanc Underfills for Low-Cost Flipchip Applications, Proc.3d Int ' l Symp, in Adv.Packing Materials, in March, 1997 (Gamote etc.), Advanced Flipchip Materials:Reflowable Underfill Systems,Proc.Pac.Rim ASME Int ' l Intersocity Electronic and photonic PackagingConf., ASME, in June, 1997, (Johnson etc.), Reflow Curable Polymer Fluxes for Flipchip Assembly, Proc.Surface Mount Int ' l 1997.
End filler stick selection chemically is subject to above-mentioned technology and performance demands.For obtaining best fatigue behaviour, preferably be chosen in the material that the thermal cycling temperature scope has high-modulus and minimum CTE.For polymer, this means that according to purposes glass transition temperature (Tg) will be higher than 125-170 ℃.With inorganic filler such as SiO 2Come filled polymer, what its CTE and modulus can be with silicon dioxide is approaching.But, be lower than 30ppm/ ℃ CTE in order in polymer system, to obtain, need 50 volume % or more filler usually.This high filler content has significantly improved its viscosity.In order to obtain required balance between processing characteristics and the curing materials performance, use low-viscosity epoxy resin as far as possible usually.After containing mass filler in these materials and being cured to high Tg is very crisp, and to the poor adherence of polyimides on the IC and aluminium nitride passivation layer.Therefore, Zui Jia end filler stick system is necessary trading off between processing request and the performance requirement.By improving its chemical composition, reduce or eliminate the improvement flip-chip device technology or the structure of all these materials limitations, can significantly improve the reliability of flip-over type chip apparatus.
From the above-mentioned background situation as can be known, the reliable scolder flip-over type chip method that is interconnected to the IC chip on the ceramic substrate has just begun to use organic substrate.Although the designer has strong request, the difficulty on processing and the material has been slowed down the popularization of this technology.The technology of flip-over type chip accessory has too many step at present, and cost is too high, IC is in the future designed be difficult to promote the use of.If have the flip-over type chip accessory technology of simplifying to reduce cost and, just can make and adopt the flip-over type chip assembly to become method for circuit arrangement with extensive more attraction to the requirement of end filler stick system.
Summary of the invention
The invention provides a kind of new method of simplifying described flip-over type chip assembly technology, the bigger material of the energy scope of application, thus reduce cost, and improve the reliability of interconnection.
One aspect of the present invention relates to integrated circuit (IC) chip is connected to method on the circuit substrate.Said method comprising the steps of: adhesive is applied directly to integrated circuit (IC) chip in advance to be had on the one side of projection, and removes the adhesive some parts, and projection is exposed.After adhesive had applied, preferable solvent assisted burnishing by projection was removed adhesive segment.Described method is further comprising the steps of: have one side projection and that stick with glue the agent coating in advance to be pressed on the circuit substrate described integrated circuit (IC) chip, make projection provide conductivity to connect between integrated circuit (IC) chip and circuit substrate.The adhesive of precoating just forms between integrated circuit (IC) chip and circuit substrate and has glued combination on the chip.
Compare prior art, said method provides many advantages.For example, before substrate is enclosed, adhesive is applied on the IC of projection, just obtains sealing and checking easily of projection easily, and need not consider size and the step pitch of IC.And, just so strict because this technology is not utilized core sucting action to the viscosity requirement of adhesive applications, can be about 1000-30 with viscosity, the adhesive of 000 pool obtains effectively to seal.If need, the elimination of viscosity limitation just can be used more filer content, uses available chemistry and catalysis system.This wider adhesive formulation just can obtain the higher device of reliability by the performance that improves adhesive material.In addition, owing to when in cohesive process, being out of shape,, make said method that the possibility of adhering to without flux is provided to the wiping action of projection.
The present invention relates on the other hand and prepares the method for assembling with integrated circuit (IC) chip.Described method comprises the step of the wafer that the face that has many conductivity projections above it is provided.Described method comprises that also adhesive is applied to wafer to be had on the face of projection, with the softening adhesive of solvent, wipes through softening adhesive from the projection top, then wafer is cut into the step of integrated circuit (IC) chip one by one.Because described adhesive is to be deposited on the wafer level, rather than on the chip level, so do not need dispensing, wicking or weir to block up (damming).When on the wafer level, rather than when carrying out on the chip level, this technology is also quicker.In addition, owing to used quick-setting adhesive, can cancel the back solidification process.
Further aspect of the present invention relates to integrated circuit (IC) chip.Described integrated circuit (IC) chip comprises the face that many conductivity projections are arranged above it.Comprise also on the chip that one deck is covered with the adhesive of bumping surface.These projections have the exposed contact area that is not covered by adhesive layer basically.The bumping surface that has to wafer carries out solvent assisted burnishing, just can make the exposed contact area of projection keep its original circular contour.
The various extra advantages of the present invention have the part explanation in the following description, and partly from then on may be obvious that in the explanation, perhaps can obtain to understand by working of an invention.By key element of specifically noting in claims and combination, can understand and realize advantage of the present invention.Be to be understood that above-mentioned general remark and following detailed explanation only are exemplary and explanat, the invention that proposes claim be there is no restriction.
Brief Description Of Drawings
Constitute this specification part and the description of the accompanying drawing of several embodiments of the present invention together with specification has been described, be used for explaining the principle of the invention.Brief Description Of Drawings is as follows:
Figure 1A-1C has illustrated the manufacture method that is used for the IC chip that is connected with circuit substrate;
Fig. 2 A-2B has illustrated that the IC chip that is used for making among Fig. 1 C is connected to the method on the circuit substrate;
Fig. 3 A-3B is the microphotograph figure of the IC chip that makes by method shown in Figure 1A-1C, and Fig. 3 A shows the chip before the abrasion, and Fig. 3 B shows the chip after the abrasion.
Fig. 4 A-4C has illustrated the another kind of method that is used for making the IC chip that is connected usefulness with circuit substrate;
Fig. 5 A-5B is the microphotograph figure of the IC chip that makes by method shown in Fig. 4 A-4C, and Fig. 5 A shows the chip before the abrasion, and Fig. 5 B shows the chip after the abrasion;
Fig. 6 A is the cross section microphotograph figure that is connected to the IC chip on the circuit substrate, and described IC chip was not denuded step before connecting;
Fig. 6 B is the cross section microphotograph figure that is connected to the IC chip on the circuit substrate, and described IC chip had carried out the abrasion step before connecting.
Fig. 7 A and 7B have illustrated the method for making conductive strips;
Fig. 8 A has illustrated with 8B and has used Fig. 7 A to form the method that conductivity is connected with the conductive strips shown in the 7B;
Fig. 9 A-9D has illustrated the method that is used for sealing wafer integrated circuit upper protruding block.
Figure 10 has illustrated and has used 1200 granularity diamond dust sand paper to carry out after the dry-fine thickness profile figure of adhesive layer on the IC chip.
Figure 11 is the microphotograph figure of IC chip shown in Figure 10, has shown the pollution of adhesive and the situation that flattens of solder projection.
Figure 12 has shown an IC chip after the solvent assisted burnishing, its lack of homogeneity and stayed a large amount of residues on the IC chip.
Figure 13 has shown an IC chip after the solvent assisted burnishing, and it has good uniformity and stayed the little residual thing on the IC chip.
Figure 14 A and 14B have illustrated after the solvent assisted burnishing, the thickness profile figure of adhesive layer on the IC chip.
Figure 15 A-15C has illustrated the solvent assisted burnishing method that is used for making the IC chip that is connected usefulness with circuit substrate, and described adhesive thickness is greater than the height of solder projection.
Figure 16 A-16C has illustrated the solvent assisted burnishing method that is used for making the manufacturing IC chip that is connected with circuit substrate, and described adhesive thickness is less than the height of solder projection.
The detailed description of preferred implementation
Now in detail with reference to some illustrative embodiments shown in the accompanying drawing of the present invention.Whenever possible, in each figure, use the identical identical or similar parts of numeral.
The invention provides the binder resin that the end is filled out and be applied to a kind of available method on the IC chip.In this case, to the interconnection substrate of usefulness such as printed circuit board (PCB) (PCB) before,, be applied on the face that projection is arranged that the IC chip is preferably the wafer level the resin that the end is filled out with chips incorporate.Resin can apply by the technology as laminated film material or liquid coating.Rely on the end embankment method of wicking covering hidden face different with tradition, the present invention can be applied directly to resin on the whole exposed surface/face of IC chip.Thus, can eliminate and tradition is filled with the entrapped air of pass or fills incomplete problem in the end.Use method of the present invention, can control the end and fill out the coverage rate and the thickness of resin, to guarantee uniformity.Because it is do not adopt the wicking process, just not really strict to the requirement of uncured resin rheological property.Can use alternative chemical material and higher filer content thus, after solidifying, obtain better mechanical performance.
After chip has applied adhesive resin, perhaps in coating procedure, remove the some parts of binder resin, the top of solder projection is exposed.Removing of adhesive resin can be undertaken by several modes, comprise that the Mechanical Method of removing material (comprising some scolder) with abrasive material removes, replaces the physics of adhesive and remove, use as the indirect physics of plasma treatment and remove or remove by comprehensive mechanical and chemical reagent method, in a kind of method in back, the surface combination that Rong lower (thinner) abrasive material quality obtains is used solvent to clean from solder globules and is removed adhesive.For example, can use mechanical means to remove the adhesive that applies in advance on the projection top.The exemplary mechanical method comprises with abrasive material to be ground, strikes off adhesive or adhesive is ironed and finally make its cracking or otherwise replace the jointing material at projection top with blade.
Above-mentioned adhesive remove step for before flow step again, with substrate between, obtain good metal-Metal Contact very importantly in solder projection and interconnection, the top surface of projection should expose to small part.The exposed step of removing with projection of adhesive also plays the effect of removing oxide-film on the projection that it begins to form in the reflow process.In some cases, after finishing the exposed operation of projection, the guard cover of film or other type should be coated on the wafer/chip protection adhesive and exposed projection.
After the top of projection was exposed, the wafer that forms chip was cut into many chips one by one.After the wafer cutting (if having, and after removing diaphragm), can be with the substrate of selected IC chip and interconnection usefulness to good and with heating and attached thereto in advance of pressure.Usually, just before placing step, chip do not flow end underfill material dispensing on the PC plate with a spot of.This additional material is used to provide complete joint line and fills, also play a part interim gluing, chip is fixing on the throne when it enters reflow furnace.In this process of attachment steps in advance, the solder projection of chip is out of shape a little, the result can further guarantee IC and interconnection with good metal-Metal Contact between the substrate and adhesive to good wetting of substrate.The deformation energy of projection makes IC and substrate at regular intervals, and allow ooze under the adhesive contact substrate surface and with its complete wetting, the space under the complete filling chip thus.In addition, subsiding of projection can make the oxide on surface on the solder projection ftracture, thereby exposes fresh solder surface, and the latter is smeared on the substrate pad forms the good metal combination.
When the IC chips incorporate that has applied resin to the substrate of interconnection usefulness, the adhesive that applies in advance forms and keeps mechanical bond between chip and the substrate, significantly reduces the stress in the solder joints.How depend on purposes, need not to use flux just can form solder joints, still can form reliable interconnection.In this case, adhesive replaces the flux slurry to play before stream again IC adhered to effect onboard.The scolder reflow process also can play the part or even full solidification at the bottom of fill out resin effect, can eliminate the back curing schedule that carries out in addition.
Figure 1A-1C has shown according to the principle of the invention and has been used for forming the illustrative methods that the IC chip is connected with circuit substrate conductivity.Figure 1A has shown IC chip 20 or the wafer with passivated surface 22, many conductivity projection 24 is arranged as solder projection above it.Described projection 24 can be made by various known electric conducting materials.Exemplary materials comprises fusible solid metal, gold, conduction slurries, conducting polymer, the nickel of no electrical method plating and the gold of electroless plating method.
Projection 24 should be deposited on the I/O pad of chip 20, and outwards gives prominence to or protrusion from the passivated surface 22 of chip 20.The bumping surface of chip 20 covers as adhesive film or adhesive solvent with one deck adhesive material 26.Described adhesive can use any known technology deposition or be coated on the bumping surface of chip.For example, described adhesive can hot melt applies, solution applies or be bonded on having on the crowning of chip as film laminating.
Before assembling, adhesive material 26 be filled in projection 24 around be used in processing procedure protection projection 24.Shown in Figure 1A, the thickness of adhesive material 26 is short in the height of projection 24.As a result, have many on the exposed surface of adhesive 26 and the grand piece 28 of projection 24 corresponding adhesive.Grand piece 28 has covered projection 24, and outwards protrudes from the adhesive basic surface 30 of the substantially flat between projection 24.If adhesive applies as liquid, suitable b-stage solidification of then described liquid or the dry adhesive film that forms.
In order to ensure with substrate better conductivity be connected, should remove the grand piece 28 of the adhesive that covers on the projection 24 to small part.Shown in Figure 1B, use abrasion process to remove the jointing material that is positioned on the projection 24, conductivity projection 24 is exposed, make it with enclosed chip better conductivity be connected.In erosion process, allow as sand paper, fine ground film, with the trade name of Scotch Bright from 3M Company, St.Paul, the grinding pad that MN buys, emery cloth, scraper or apply these abrasive materials 32 of cutter and cover projection 24 on the grand piece 28 of adhesive contact, for the conductivity connection is exposed projection 24.Because described grand piece is higher than the average height on the chip 20, therefore, these grand pieces just become build-up of pressure, accept main abrasion or scraping action.Fig. 1 C has shown by abrasion makes described projection expose chip 20 afterwards.In case described projection has revealed to come out, can use the guard cover of film, band or other type to cover chip 20, protection adhesive 26 and exposed projection 24.
Can use various technology that conductivity projection 24 is exposed.If adhesive applies as liquid, in coating procedure, can use the blade of scraper or pocket knife to remove adhesive on the projection so.For example, can use pocket knife to sprawl adhesive and remove adhesive segment on the projection 24 simultaneously.Perhaps, after the liquid adhesive sclerosis, projection 24 is exposed by abrasion.And described adhesive can be used as film and applies, and the part of film is then removed by erosion process.
Shown in Fig. 1 C, each projection 24 penetrates adhesive layer 26 in vertical direction fully.Like this, the height of the projection 24 of each experience wear adhesive layer 26 to the thickness of small part of making peace greatly equates or is higher than the thickness of adhesive layer 26 to small part.In addition, the exposed region 36 of projection 24 protrudes slightly from adhesive basic surface 30.
Fig. 2 A and 2B have illustrated and have been used for prepared chip 20 conductivity are connected to circuit substrate 34 as the method on the encapsulated circuit.For chip 20 being connected on the circuit substrate 34 circuit pad 38 symmetries of the exposed region 36 of projection 24 and circuit substrate 34.Then chip 20 is pressed on the circuit substrate 34, between projection 24 and circuit pad 38, forms the conduction contact with enough power, and make adhesive 26 wetting and fill projection 24 and circuit substrate 34 around.
Projection 24 will be out of shape in engaging process.Make projection 24 distortion, reduce the distance between chip 20 and the substrate 34 and make adhesive 26 complete wetting and seal the surface topography of chip circuit, get rid of the air of bringing into.Adhesive 26 can solidify in joint technology or additional heat may curing afterwards.After the curing, adhesive 26 provides the mechanical bond between IC chip 20 and the substrate 34, stress is distributed on the solder joints again, and seals projection 24 and prevent that they are subjected to the influence of environment.
In the experimental example aspect explanation the present invention is above-mentioned, use the IC chip of making by the flip-over type technology.Diameter is that many solder projections of 4 mils are positioned on the zone of chip.Use covers described solder projection by the adhesive of the commodity Pyralux LF by name that DuPont makes.Specifically, adhesive is pressed in is being heated on the hot plate on 100 ℃ the chip, thereby make the adhesive layer of 3 mil thick place chip surface with projection.Fig. 3 A is the microphotograph figure of the chip after the adhesive coating.The high projection of 4 mils makes that than the thickness height of adhesive layer the suitable major part of these projections is outstanding from the adhesive basic surface of chip surface.The fine grinding film of Imperial that uses 3M Corporation to make is removed the adhesive at projection top, and projection is revealed.Fig. 3 B makes projection expose the microphotograph figure of chip afterwards through abrasion.Parts after the abrasion are checked do not have to find to exist by any sign of the electric conducting material under the abrasion on the processing component.The material of described adhesive of being denuded and projection is all obviously taken away by fine abrasion film.
Fig. 4 A-4C has illustrated and has been used for IC chip conduction is connected in the other method of circuit substrate in accordance with the principles of the present invention.As can be seen, the method shown in Fig. 4 A-4C has and the similar feature of method shown in Fig. 3 A-3C.For example, Fig. 4 has shown and has comprised many conductivity projections 124 that are deposited on chip 120 passivated surfaces 122.The bumping surface of chip 120 is coated with one deck adhesive material 126, and the thickness of described material is equal to or greater than the height of projection 124.Adhesive 126 is covered with projection 124, and the exposed basic surface 130 parallel with passivated surface 122 arranged basically.
Shown in Fig. 4 B, use cutting or abrasion process to remove the adhesive material at projection 124 tops, conductivity projection 124 is exposed, in order to contact with enclosed chip conductivity better.In erosion process, use abrasive material 132 to polish adhesive 126 whole basic surface 130, projection 124 is exposed be used for conduction.Fig. 4 C has shown the chip 120 that projection 124 is exposed by abrasion.After described projection exposes, can use the guard cover of film, belt or other type to cover chip 120, be used for protecting adhesive layer 126 and exposed projection 124.
Shown in Fig. 4 C, each projection 124 penetrates adhesive layer 126 in vertical direction fully.Like this, the height of the projection 124 of each experience wear make peace greatly that the thickness of adhesive layer 126 at least a portion equates or.In addition, the exposed region 136 of projection 124 flushes substantially with adhesive basic surface 130.Should be appreciated that chip 120 can be to be connected on the circuit substrate with the described identical mode of above-mentioned Fig. 2 A and 2B.
Fig. 5 A has to be coated with the microphotograph figure of exemplary chip of the projection of adhesive with the 120 identical modes of chip shown in Fig. 4 A.In addition, Fig. 5 B is that adhesive segment is ground, and makes the conductivity projection expose the microphotograph figure of Fig. 5 A chip afterwards.
For above-mentioned execution mode,, may not pass adhesive without the projection that grinds and contact with bonding pad if adhesive coating is mobile low in adhesion process.Fig. 6 A has shown that use Pyralux (by the not flowable adhesive of DuPont manufacturing) is bonded to the sectional view without the abrasion chip on the PR4 plate.Described sectional view shows that described projection does not contact with substrate, and this is because described adhesive is very thick, and has covered described projection.Fig. 6 B has shown that use Pyralux is bonded to the sectional view through polishing/abrasion chip on the PR4 plate.Different with the chip shown in Fig. 6 A, the sectional view shown in Fig. 6 B shows that projection all contacts with substrate, and this is because use glossing to remove the unnecessary adhesive in projection top.
If described adhesive coating can be significantly mobile, then described projection can pass adhesive to a certain extent in the bonding process.But adhesive 126 can flow not smooth in the zone that is lower than projection, hinders thus to form the excellent metallurgical combination.Even when using the high fluidity adhesive, still will grind usually therefore, to adhesive layer.
Fig. 7 A-7B has shown another feature of the present invention, and it relates to the method that is used for making z axle conductive strips.Described method comprises the step that forms 120 1 arrays of many conductive particles.Exemplary particle size distribution scope is the 20-75 micron.Described method also comprises shown in Fig. 7 A, uses one deck adhesive 214 to come coated particle 210.Described adhesive 214 can be coated on the particle 210 by various technology.For example, described adhesive can hot melt applies, solution applies or engage as film laminating.In addition, these particles may be combined in becomes suspension in the adhesive, adhesive suspension is sprawled to form one deck adhesive or film then, wherein contains many particles.
The basic thickness of adhesive 214 is less than the granularity of particle 210.Therefore, have many and particle 210 corresponding grand pieces 218 on the upper surface 216 of adhesive layer 214 up, also have many on its lower surface 217 and particle 210 is corresponding swells 219 down.Certainly, in alternative execution mode of the present invention, the basic thickness of adhesive layer can be equal to or greater than the granularity of particle.In this embodiment, described adhesive just forms flat substantially upper surface and lower surface.
After adhesive 210 is applied on the particle 210, remove the part of grand piece 218 up at least, the last contact area 220 of particle 210 is exposed.Similarly, remove the part of grand piece 219 down at least, the following contact area 220 of particle 210 is exposed.Particle 210 can expose particle 210 by for example using abrasive material to polish or grinding the upper surface 216 and the lower surface 217 of adhesive layer 214.
In some execution mode of the present invention, particle 210 can be supported on earlier on the release liner (not shown), then adhesive is applied on the particle 210.In these execution modes, when particle 210 is covered by adhesive layer 214, and used as the abrasion technology contact area 220 is exposed after, be that remove bottom surface 217 with liner from the back side of adhesive layer 214, can handle the bottom surface 217 of adhesive layer.
Fig. 7 B has shown that last contact area 220 and following contact area 224 have exposed adhesive layer 214 afterwards.The product of describing among Fig. 7 B is one and is applicable to the conductive strips 226 that the contact of z axis conductivity is provided.The granularity of the particle 210 with 226 is equal to or greater than the thickness of adhesive 214 substantially.Therefore, each particle 210 penetrates the thickness of adhesive 214 in vertical direction fully.Can use diaphragm or covering to protect exposed last contact area 220 and following contact area 224, for being with 226 to be actually used in the conductivity connection is provided.
The method of using conductive strips 226 to provide the z axle to connect between first and second electric components 228 and 230 has been provided for Fig. 8 A and 8B.Shown in Fig. 8 A, conductive strips 226 are placed between some conductive spacers 232 of electric component 228 and 230.Then, shown in Fig. 8 B, use enough power will be with 226 to be pressed between electric component 228 and 230, between particle 210 and circuit pad 232, form the conduction contact.To being with for 226 whens pressurization, around making adhesive 214 wetting particles 210 and filling, between electric component 228 and 230, form combination also to being with 226 heating.Described adhesive can solidify in this cohesive process or additional heat may curing later on.
The illustrative methods of integrated circuit (IC) chip is made in Fig. 9 A-9D explanation according to the principle of the invention.Fig. 9 A shows the wafer 320 with passivated surface 322, and many conductivity projections 324 are arranged on it.Adhesive film 326 with protection backing 328 is placed near the passivated surface on surface 322.
Fig. 9 B shows that adhesive film 326 just is being crushed on the passivated surface 322 of wafer 320.When adhesive film 326 was pressed on the wafer 320, adhesive film 326 was covered with projection 324, thus and the space around the distortion filling projection 324.And adhesive film 326 is attached on the passivated surface 322 of wafer 320.
Then, shown in Fig. 9 C, the wafer 320 that is coated with adhesive in advance is cut or is separated into integrated circuit 330 one by one.At last, shown in Fig. 9 D, remove the back sheet 328 on the integrated circuit 330, adhesive layer is exposed.After removing backing 328, described integrated circuit just can be used for being connected on the substrate.
In above detailed explanation, remove step that adhesive segment on the projection forms exposed contact area use the strong abrasive material of active force, scrape off adhesive with blade or with adhesive ironed finally split or otherwise remove have in the mechanical means of adhesive material at projection top illustrated.But as illustrated among Fig. 1 C, 2A, 2B, 3B, 4C and the 5B, the adhesive that uses the method for these types to remove the solder projection surface also can cause removing some solder materials.Clearly demonstrate as above, the encapsulating material that uses abrasive material to remove the solder projection top shows that such friction meeting together with removing some scolders, forms flat projection shape, like this projection basically with regard to and surface of pressure-sensitive adhesive flush.
For several reasons, should not remove the scolder of projection.These reasons are, if remove bumped solder, so from the projection to the projection and chip to the volume of scolder between the chip with regard to bad control, and this can influence the reliability of IC.In addition, the scolder chip can be provided and delivered on the surface of encapsulation agent, produces pollution problem thus.At last, the disappearance of solder projection spherical surface can make the auto arrangement of IC chip on printed circuit board substrate and place more complicatedly.Therefore, when removing the lip-deep encapsulation agent of solder projection, should not remove the scolder of solder projection, also not make the upper flat of solder projection, promptly solder projection should keep its original spheric profile.
Have been found that the end underfill material that to remove the scolder top by wiping action rather than corrasion.That is to say, can use soft material as weaving or non-weaving cloth or perforated foams.Before using, come moistening described cleaning pad to soften encapsulation agent with a small amount of appropriate solvent.Also can use harder micro-structure surface to replace cleaning pad.When using harder micro-structure surface, before using, the solvent of appropriate amount is applied in the recessed position on the micro-structure surface.By using the auxiliary gentle wiping action of this solvent, encapsulation agent is filled out at the end that can remove on the projection top, can not change the size and the shape of projection simultaneously in any significant mode.The solvent assisted burnishing of solder projection or wiping embodiment are as described below.
Solvent assisted burnishing embodiment
For each embodiment of the following stated, fill out encapsulation agent at the bottom of the use epoxy radicals.In all cases, prepare described encapsulation agent, form pliable and tough form of film.All materials all are the powder 2 weight portion fillers that 1 weight portion adhesive solid is added with the amorphous silica spheric granules.SiO 2 powder typically have a diameter from the 2-10 micron.In all embodiment of the following stated, adhesive solid is the mixture of epoxy resin and essentially no reactivity thermoplastic component basically.The ratio of epoxy resin and thermoplastic component is 7: 3-8: 2.In all cases, use the solvent of acetone as adhesive.Can use other suitable solvent, concrete adhesive used when needing only it is fit to.
Embodiment 1:(contrast, the dry grinding erosion)
Use a slice to be about 2 * 2 inches silicons that 9 * 9 projection chip arrays are arranged on it.Described solder projection diameter is 100 microns, is the Sn-Pb eutectic of 63-37.Each chip contains 68 projections in the array zone.Chip uses heat lamination technology to seal with uncured a epoxy radicals adhesive film in advance, and described adhesive film initial thickness is a bit larger tham 100 microns.
It has facing up of projection to be contained on the aluminium dish with the wafer sealed in advance, it is faced down to put in the Struers Metallurgical polishing machine (from Struers, Inc.of Westlake, Ohio buys) then.Load onto the diamond dust sand paper of one 1200 granularity on the turntable that its diameter is 8 inches.Total force with 5N makes the wafer part contact with diamond dust sand paper.Turntable and wafer part were rotated 35 seconds with 150rpm under the condition that does not add lubricant separately.
After the dry wear operation, it is very smooth that the surface of described adhesive becomes.Many but be not that whole solder projections has revealed to come out.The thickness profile figure of adhesive has disclosed crown shape as shown in figure 10.Photo explanation shown in Figure 11, the bad situation that flattens has taken place in projection, and is entrained with the pollutant that is caused by scolder chip and residual abrasive media in the adhesive layer.
Embodiment 2:(contrast, plasma etching)
Come lamination one monolithic chip with uncured a epoxy radicals adhesive film.There is diameter to be roughly 100 microns solder projection on the described chip.Adhesive is to exert pressure lamination 60 ℃ temperature with hand.The position of projection is visible, but projection does not expose.Use PS0524 type (Plasma Science) device, it is a RF type system of operating under 13.5MHz, can carry out plasma etching with the maximum power of matching network capacity transmission 500W.Use oxygen gas plasma.Chip is placed the middle part that is sapphire plasma place.Use the maximum power of quota power 60%, expose about 15 minutes of chip.Afterwards, surface of pressure-sensitive adhesive is checked with SEM.The adhesive matrix corrosion of not half only appears in the outward appearance on surface, but the basic not corrosion of silica filler particle itself.Find that through scrutiny after corrosion was exposed, projection was mostly covered by silica filler and some adhesive residues.
Embodiment 3:(the present invention, the influence of Wiping material)
Use about 0.8 * 0.8 inch silicon that 4 * 4 chip arrays are respectively arranged on it.Each chip contains 88 SnPb eutectic projections that are about 100 micron diameters.Described chip array is not cut in advance.Use heat lamination technology, the uncured a epoxy radicals adhesive film that is about 100 microns with thickness is sealed each chip array in advance.
Concerning each chip array, use a kind of encapsulation agent of removing the projection top in the listed pad material series of following table 1.Described pad material can be from Struers, Inc.of westlake, Ohio, Allied HighTech Products, Inc.of Rancho Domingo, California and Texwipe Company LLC ofUpper Saddle River, New Jersey buys.
For each experiment, polishing pad is tightly wetting a little with small amount of acetone before using.To carefully avoid residual liquid on polishing pad.Each mat size is 8 inches, is fit to cooperate Struers Metalographic polishing machine.Chip array bumping surface to be processed up places on the aluminium circle of heavy 83 grams, then the aluminium dish is put into polishing machine, and its chip upper protruding block surface is towards polishing pad.The weight of aluminium dish is to affact only z axle active force on the test film.Time shown in turntable and test film rotate one with 150rpm separately.
The uniformity that the assess sample adhesive is removed, polishing pad remain in the amount that amount on the sample and adhesive are removed.The uniformity that adhesive is removed and the residual quantity of residue are qualitative evaluations.In Figure 12, shown the presentation graphs of the sample that has a large amount of residues and lack of homogeneity, and shown that in Figure 13 residue seldom and the sample that has good uniformity.All results list in Table I.From these were a series of, embodiment 3H and 3I thought best, and this mainly is because sample presents best uniformity, produces minimum residue simultaneously.
Table I
Solvent assisted burnishing, polishing pad screening test result
The type of pad The explanation of pad Polishing time (s) Final adhesive thickness (mm) Pad residue amount The surface of pressure-sensitive adhesive uniformity
A Felt Allied“Billiard” 25 75 In a large number Well
B Felt Allied“Blue Felt” 28 75 Minimum Well
C Compound Allied“XT” 28 5 In a large number Difference
D Paper Clean clean chamber usefulness, indigo plant, 100 grades In a large number Difference
E Foam Allied“Chem-Pol” 25 75 Middle amount Well
F Foam Struers“POCTA” 28 75 Middle amount Difference
G Foam Struers“POCTA” 28 62 Middle amount Difference
H Weave cotton cloth Texwipe“TX309” 28 75 Minimum Well
I Compound Struers“MD Plan” 25 75 Minimum Well
Embodiment 4:(the present invention, the influence of adhesive thickness)
Use the preferred pad sheet material of embodiment 3H and 3I, estimate of the influence of adhesive thickness the thickness evenness and the appearance of the encapsulant material of required polishing time and coated wafers.Except changing adhesive thickness and required thus polishing time, all other details has explanation in embodiment 3.After finishing polishing, 16 chips of every kind of test piece are carried out the adhesive thickness measure.And the situation of surface smoothness and lug surface has been carried out qualitative examination.The results are shown in down in the Table II.For embodiment 4H, only fail to finish polishing process with the MD-Plan pad, this be because compare plate its lower position adhesive volume that can hold, have too many adhesive.In this embodiment, and then use second polishing step that utilizes the Texwipe fabric, finish the exposed of projection.
Table II
Solvent assisted burnishing, the adhesive thickness effect
The explanation of pad Adhesive is thickness (micron) originally Need the polishing time (s) of usefulness Adhesive layer final thickness (micron) The standard deviation of final thickness (micron) The surface of polished situation Projection top, polishing back situation
A Texwipe “TX309” 90 3 61 9.9 Smooth Smooth, sphere
B Texwipe “TX309” 100 3 80 6.4 Smooth Smooth, sphere
C Texwipe “TX309” 116 5 80 6.8 Smooth Smooth, sphere
D Texwipe “TX309” 125 8 71 11 Smooth Smooth, sphere
E Struers “MD Plan” 90 10 87.5 2.3 Inhomogeneous Flat slightly
F Struers “MD Plan” 100 5 87.5 1.2 Inhomogeneous Flat slightly
G Struers “MD Plan” 116 5 87.5 2.8 Smooth Flat slightly
H Struers “MD Plan” 125 ＞20 76 6.7 Flat slightly
Embodiment 5:(the present invention, the polishing of wafer)
Use the evaluation of Texwipe " TX309 " pad material to carry out the ability of solvent assisted burnishing near the wafer level.In this case, use has about 1.8 * 1.8 inches chip of 9 * 9 projection arrays.This is successfully to put into the used maximum wafer of Metalographlic polishing machine.Used identical among this chip type and the embodiment 3 and 4.In embodiment 5A and embodiment 5B, two kinds of different uncured a epoxy radicals adhesive films have been adopted in test.Adhesive thickness is about 100 microns.Reuse acetone as solvent.After finishing solvent assisted burnishing, draw the surface thickness distribution map of explanation gained adhesive thickness evenness degree from the dial indicator reading.Shown this result among figure below 14A and the 14B.In these embodiments, after the polishing not the average thickness of end packing course be about 80 microns, and the height of projection is about 100 microns.The standard deviation of embodiment 5A and 5B thickness measure is respectively 15 millimeters and 11 millimeters.
Shown in Figure 15 A-15C and 16A-16C, the integrated circuit (IC) chip 420 of using the described solvent assisted burnishing technology of the foregoing description to make has at filler at the bottom of the adhesive and removes the solder projection 424 that significantly change or distortion take place in the process.Treated IC chip 420 has passivated surface 422, and the conductivity projection is arranged in the above.Passivated surface 422 and projection 424 are covered with by adhesive 426.
In Figure 15 A-15C, there is the thickness of the adhesive layer 426 on the IC chip 420 of conductivity projection 424 to be equal to or greater than the height of projection 424.Adhesive material 426 covers projection 424 and has exposed basic surface 430, and this is substantially parallel with passivated surface 422.Shown in Figure 15 B, the solvent 434 that polishing pad 432 usefulness are suitable is used for softening adhesive 426.Described then softening adhesive is removed with polishing pad 432 wipings or polishing, up to the circular contour that exposes projection 424.After projection 424 exposes, can be shown in embodiment 2A and 2B (for example), remove the described identical mode of technology they are attached on the printed circuit board substrate with just grinding end filler.
In Figure 16 A-16C, the thickness of adhesive material 426 is less than the height of projection 424.As a result, the exposed surface of adhesive 426 has the grand piece 428 of adhesive of many and projection 424 correspondences.Grand piece 428 is covered with projection 424, and from protruding on the adhesive basic surface 430 between the projection 424.As acetone or other wet with solvent polishing pad 432, be used for softening adhesive 426 with suitable solvent 434.Shown in Figure 16 C, solvent 434 makes adhesive 426 softening, so polishing pad 432 can be removed adhesive 426, and can not influence the circular contour of projection 424.As mentioned above, after projection 424 has exposed, film, band or other guard cover can be covered on the chip 420, in order to protection adhesive 426 and exposed projection 424.
Shown in Figure 15 A-15C and 16A-16C, the use of polishing pad 432 and solvent 434 makes the exposed region 436 of projection 424 can keep its original circle.Keep the circular contour of projection that combined process is had extra benefit, this is because the distortion of projection 424 is more prone in bonding process.As mentioned above,, can reduce the spacing between IC chip 420 and the substrate, and make the adhesive complete wetting can seal the surface topography of chip circuit by the distortion of projection 424.In deformation process, the face checking of solder projection 424 also exposes the scolder of not oxidation and cleaning, is convenient to be connected with substrate, forms better combination thus between IC chip and substrate.
As can be seen, solvent assisted burnishing technology as herein described provide compare other adhesive seal the material technology of removing have significant advantage.This solvent assisted burnishing can allow solder projection shape invariance and indeformable before being connected to circuit substrate, guarantees the bigger uniformity of solder projection and the reliability of the higher connection that is formed by solder projection thus.
Should be appreciated that other technology also can be used for adhesive is applied on the wafer.For example, described adhesive can apply or the solution coating by hot melt.In addition, said method also can comprise the some parts of removing adhesive on the projection that is disclosed as in the above detailed description, so that form the step of exposed contact area.
About above explanation, be to be understood that under the condition that does not deviate from the scope of the invention and can all making change aspect shape, size and the arrangement of details, especially used structural material and part.Illustrate and described execution mode all only be exemplary, the real scope and spirit of the present invention are represented by the broad sense of following claims.

Claims (17)

1. integrated circuit (IC) chip is connected to the method on the circuit substrate, described integrated circuit (IC) chip comprises the face with many conductivity projections, and described method comprises the steps:
Adhesive is applied directly on the face that projection is arranged of integrated circuit (IC) chip;
Remove the some parts of adhesive, the contact area of conductivity projection is exposed, removing of described adhesive some parts is by with the softening adhesive of solvent, and will remove from the conductivity projection through softening adhesive;
The bumping surface of integrated circuit (IC) chip is placed on the circuit substrate, makes projection between integrated circuit (IC) chip and circuit substrate, form conductivity and connect,
The some parts that it is characterized in that described adhesive is by removing with the wiping from the conductivity projection of the softening adhesive of solvent and adhesive that this is softening.
2. the described method of claim 1 is characterized in that removing after the adhesive some parts, the rounded profile of contact area that the conductivity projection is exposed.
3. the described method of claim 1 is characterized in that removing after the adhesive some parts, and the height of conductivity projection is greater than the thickness of adhesive.
4. the described method of claim 1 is characterized in that by being selected from following technology adhesive being applied on the integrated circuit (IC) chip: hot melt coating, solution application of adhesive, adhesive film is carried out lamination and adhesive film is pressed onto on the bumping surface of integrated circuit (IC) chip.
5. the described method of claim 1 is characterized in that before removing the adhesive some parts, the height of described conductivity projection is greater than the thickness of adhesive.
6. the described method of claim 1 is characterized in that before removing the adhesive some parts, the height of described conductivity projection is less than the thickness of adhesive.
7. make the method for integrated circuit (IC) chip, described method comprises the steps:
The wafer that comprises the face with many conductivity projections is provided;
Adhesive is applied to wafer to be had on the face of projection, and the conductivity projection is covered by adhesive;
Cutting the wafer that is coated with adhesive on it becomes integrated circuit (IC) chip one by one,
It is characterized in that applying after the adhesive and before cut crystal, also carry out following step:
Make adhesive softening with a kind of solvent;
The softening adhesive that covers on the conductivity projection top is wiped, the contact area of conductivity projection is exposed;
8. the described method of claim 7, it is characterized in that softening adhesive on covering conductivity projection top is wiped after, the rounded profile of exposed contact area of conductivity projection.
9. the described method of claim 7 is characterized in that by being selected from following technology adhesive being applied on the integrated circuit (IC) chip: hot melt coating, solution application of adhesive, adhesive film is carried out lamination and adhesive film is pressed onto on the bumping surface of integrated circuit (IC) chip.
10. the described method of claim 7 is characterized in that the height of described conductivity projection is greater than the thickness of adhesive before removing some cover parts of adhesive.
11. the described method of claim 7 is characterized in that the height of described conductivity projection is less than the thickness of adhesive before removing some cover parts of adhesive.
12. the described method of claim 7 is characterized in that the height of described conductivity projection is greater than the thickness of adhesive after removing some cover parts of adhesive.
13. the described method of claim 7 is characterized in that after removing some cover parts of adhesive, before the cut crystal, uses guard cover to come rubber cover stick and exposed contact area.
14. by the integrated circuit (IC) chip that the described method of claim 7 is made, it comprises:
Bumping surface with passivated surface has many conductivity projections on the described surface;
Cover the adhesive layer of conductive substrate bumping surface, described adhesive layer has basic surface, it is parallel with passivated surface basically, and described conductivity projection has the exposed contact area that is not covered by adhesive, it is characterized in that the exposed contact area of described conductivity projection has circular contour.
15. the described integrated circuit (IC) chip of claim 14, the basic surface that it is characterized in that described adhesive layer is polished.
16. the described integrated circuit (IC) chip of claim 14 is characterized in that the thickness of the height of described conductivity projection greater than adhesive.
17. the described integrated circuit (IC) chip of claim 14 is characterized in that described conductivity projection is protruding from the adhesive basic surface, makes between conductivity projection and the adhesive basic surface and forms spacing.
CNB018173675A 2000-10-17 2001-01-25 Solvent assisted burnishing of pre-underfilled solder-bumped wafers for flipchip bonding Expired - Fee Related CN1270375C (en)

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