CN1258231C - 双位多值弹道monos存储器及其制造方法以及编程、动作过程 - Google Patents
双位多值弹道monos存储器及其制造方法以及编程、动作过程 Download PDFInfo
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- CN1258231C CN1258231C CNB01803926XA CN01803926A CN1258231C CN 1258231 C CN1258231 C CN 1258231C CN B01803926X A CNB01803926X A CN B01803926XA CN 01803926 A CN01803926 A CN 01803926A CN 1258231 C CN1258231 C CN 1258231C
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
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- 239000004408 titanium dioxide Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Vd0320 | Vcg0330 | Vw1340 | Vd1321 | Vcg1331 | Vw1341 | Vd2322 | Vcg2332 | Vw1342 | Vd3323 | Vcg3333 |
0* | 0 | 2.5 | 1.2 | 5 | 2.5 | ~0 | 2.5 | 2.5 | 0* | 0 |
Vt数据 | Vd0320 | Vcg0330 | Vw1340 | Vd1321 | Vcg1331 | Vw1341 | Vd2322 | Vcg2332 | Vw1342 | Vd3323 | Vcg3333 |
00 | 0 | 0 | 2.0 | ~0 | 5 | 2.0 | 5 | 5 | 2.0 | 0 | 0 |
01 | 0 | 0 | 2.0 | ~0 | 5 | 2.0 | 4.5 | 5 | 2.0 | 0 | 0 |
10 | 0 | 0 | 2.0 | ~0 | 5 | 2.0 | 4.0 | 5 | 2.0 | 0 | 0 |
Vt数据 | Vd0320 | Vcg0330 | Vw1340 | Vd1321 | Vcg1331 | Vw1341 | Vd2322 | Vcg2332 | Vw1342 | Vd3323 | Vcg3333 |
00 | 0 | 0 | 2.0 | ~0 | 5 | 2.0 | 5 | 5 | 2.0 | 0 | 0 |
01 | 0 | 0 | 2.0 | ~0 | 4.5 | 2.0 | 4.5 | 4.5 | 2.0 | 0 | 0 |
10 | 0 | 0 | 2.0 | ~0 | 4.0 | 2.0 | 4.0 | 4.5 | 2.0 | 0 | 0 |
Claims (76)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP354722/2000 | 2000-11-21 | ||
JP2000354722A JP2002170891A (ja) | 2000-11-21 | 2000-11-21 | デュアルビット多準位バリスティックmonosメモリの製造、プログラミング、および動作のプロセス |
JP354722/00 | 2000-11-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1395747A CN1395747A (zh) | 2003-02-05 |
CN1258231C true CN1258231C (zh) | 2006-05-31 |
Family
ID=18827253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB01803926XA Expired - Fee Related CN1258231C (zh) | 2000-11-21 | 2001-11-21 | 双位多值弹道monos存储器及其制造方法以及编程、动作过程 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1345273A4 (zh) |
JP (1) | JP2002170891A (zh) |
KR (1) | KR100884788B1 (zh) |
CN (1) | CN1258231C (zh) |
WO (1) | WO2002043158A1 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE392698T1 (de) * | 2000-12-05 | 2008-05-15 | Halo Lsi Design & Device Tech | Programmier- und löschverfahren in zwilling-monos-zellenspeichern |
EP1215680B1 (en) | 2000-12-15 | 2008-03-19 | Halo Lsi Design and Device Technology Inc. | Fast program to program verify method |
DE10238784A1 (de) | 2002-08-23 | 2004-03-11 | Infineon Technologies Ag | Nichtflüchtiges Halbleiterspeicherelement sowie zugehöriges Herstellungs- und Ansteuerverfahren |
JP2004186663A (ja) | 2002-10-09 | 2004-07-02 | Sharp Corp | 半導体記憶装置 |
JP2004186452A (ja) * | 2002-12-04 | 2004-07-02 | Renesas Technology Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP3873908B2 (ja) | 2003-02-28 | 2007-01-31 | セイコーエプソン株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
KR100518583B1 (ko) * | 2003-07-02 | 2005-10-04 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조방법 |
US6958939B2 (en) | 2003-09-15 | 2005-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory cell having multi-program channels |
GB2436271B (en) | 2005-01-24 | 2010-06-16 | Spansion Llc | Semiconductor device and fabrication method thereof |
JP4915904B2 (ja) * | 2006-02-16 | 2012-04-11 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
US7656704B2 (en) | 2006-07-20 | 2010-02-02 | Winbond Electronics Corp. | Multi-level operation in nitride storage memory cell |
WO2008059768A1 (fr) * | 2006-11-14 | 2008-05-22 | Nec Corporation | Dispositif à semi-conducteur |
JP2011014920A (ja) * | 2010-08-30 | 2011-01-20 | Renesas Electronics Corp | 不揮発性半導体記憶装置 |
JP5563109B2 (ja) * | 2013-01-28 | 2014-07-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2017045947A (ja) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05145080A (ja) * | 1991-11-25 | 1993-06-11 | Kawasaki Steel Corp | 不揮発性記憶装置 |
JPH05326976A (ja) * | 1992-05-20 | 1993-12-10 | Rohm Co Ltd | 半導体記憶装置およびその製法 |
DE4422791C2 (de) * | 1993-06-29 | 2001-11-29 | Toshiba Kawasaki Kk | Halbleitervorrichtungen mit einem eine Inversionsschicht in einem Oberflächenbereich eines Halbleitersubstrats induzierenden leitenden Film |
DE19600422C1 (de) * | 1996-01-08 | 1997-08-21 | Siemens Ag | Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung |
US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
JP4547749B2 (ja) | 1999-09-29 | 2010-09-22 | ソニー株式会社 | 不揮発性半導体記憶装置 |
US6177318B1 (en) * | 1999-10-18 | 2001-01-23 | Halo Lsi Design & Device Technology, Inc. | Integration method for sidewall split gate monos transistor |
US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
JP2001357681A (ja) | 2000-06-12 | 2001-12-26 | Sony Corp | 半導体記憶装置およびその駆動方法 |
-
2000
- 2000-11-21 JP JP2000354722A patent/JP2002170891A/ja active Pending
-
2001
- 2001-11-21 EP EP01997853A patent/EP1345273A4/en not_active Withdrawn
- 2001-11-21 CN CNB01803926XA patent/CN1258231C/zh not_active Expired - Fee Related
- 2001-11-21 KR KR1020027009298A patent/KR100884788B1/ko not_active IP Right Cessation
- 2001-11-21 WO PCT/JP2001/010156 patent/WO2002043158A1/ja not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR20030020259A (ko) | 2003-03-08 |
EP1345273A4 (en) | 2007-05-09 |
EP1345273A1 (en) | 2003-09-17 |
JP2002170891A (ja) | 2002-06-14 |
WO2002043158A1 (fr) | 2002-05-30 |
CN1395747A (zh) | 2003-02-05 |
KR100884788B1 (ko) | 2009-02-23 |
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Effective date of registration: 20060609 Address after: American New York Patentee after: Glorious LSI design and device technology, Inc. Address before: Tokyo, Japan Patentee before: New Halo Inc. |
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Granted publication date: 20060531 Termination date: 20101121 |