CN1239576A - Memory with processing function - Google Patents
Memory with processing function Download PDFInfo
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- CN1239576A CN1239576A CN98801358A CN98801358A CN1239576A CN 1239576 A CN1239576 A CN 1239576A CN 98801358 A CN98801358 A CN 98801358A CN 98801358 A CN98801358 A CN 98801358A CN 1239576 A CN1239576 A CN 1239576A
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- memory element
- storer
- ferro
- handling function
- tape handling
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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Abstract
A memory with processing function, comprising a small number of transistor etc., allowing simple-operation processing, and causing little troubles. A W cell (34) has a ferroelectric capacitor (CF). One end (40) of the ferroelectric capacitor (CF) is connected to a data line (D) through a transistor (T1) and also to an internal data line (MW) through a transistor (T2). The configuration of Q cell (36) is almost the same. Through the data line (D), reading or writing of data from outside is performed. The contents of the W cell (34) and the Q cell (36) are sent to an adder (28) through internal data lines (MW, MQ), and the operation results are written in the Q cell (36) through a buffer circuit (32). Thus, by using a ferroelectric capacitor (CF), a functional memory can be realized with a simple configuration.
Description
The reference of related application
By means of with reference to being included in whole disclosed content in the disclosed instructions of Japanese kokai publication hei 9-193828 communique (applying date is on July 18th, 1997), claims, accompanying drawing and the summary, and merge among the application.
Technical field
The present invention relates to storer.Be particularly related to the storer of the tape handling function of memory element that comprises canned data and the inter-process means of memory element institute canned data being carried out predetermined processing.
Background technology
In order to carry out the calculation process of view data etc., functions of use storer.Functional memory is not only stored data, and comprises the function of the data of storage being carried out simple operation.For example, a kind of functional memory is arranged, have the memory of data unit of a plurality of words of storage, also have computing circuit for each word simultaneously.If use this functional memory, then needn't use imput output circuit (I/O circuit) and outside primary processor, need only computing circuit with interior dress, in a single day just can handle each word side by side for the data that write.Therefore, can handle the lot of data of storage at high speed.In addition, because of the burden of primary processor reduces, so can be and reduce other processing significantly owing to the calculation process of view data etc.
But there is following problem in functional memory in the past.In order to reduce the area of storer, functional memory in the past uses DRAM (Danamic Random Access Memory) as memory component.Therefore, because of must carrying out refresh activity etc., thus transistor that must be a lot of and wiring, and also trouble of action.In addition, because of DRAM is the storer of volatibility, so because the fault of power supply etc. probably can make the mass data in the processing all disappear.
Summary of the invention
The present invention is for addressing this is that, and its objective is that the quantity of transistor that use is provided etc. is few, can be with the storer of the tape handling function that simple action is handled and fault is few.
Based on the storer of tape handling function of the present invention, comprise the memory element of canned data and carry out the inter-process means of predetermined process for the information in the memory element of being stored in, it is characterized in that,
The ferroelectric memory device of hysteresis characteristic canned data that utilizes strong dielectric is as memory element.
As previously mentioned, though can represent feature of the present invention very fully, its formation and content and purpose and feature, on the basis of reference accompanying drawing, disclosed according to aftermentioned will be further clearer.
Brief Description Of Drawings
Fig. 1 is the integrally-built figure of expression based on the functional memory 10 of the storer of the tape handling function of the present invention's one example.
Fig. 2 is the figure of the part of presentation function storer 10 at length.
Fig. 3 is the structural drawing of expression W unit 34.
Fig. 4 is an example of the structural drawing of expression sensor amplifier 30.
Fig. 5 is an example of the structural drawing of expression buffer circuits 32.
Fig. 6 A is the sequential chart of each signal line states when representing from outside writing information.
Fig. 6 B is the sequential chart of each signal line states of expression when outside sense information.
Fig. 7 A is the sequential chart of each signal line states when being illustrated in inside and carrying out under the situation of addition process from W unit 34 sense informations.
Fig. 7 B is the sequential chart of each signal line states when being illustrated in inside and carrying out under the situation of addition process from Q unit 36 sense informations.
Fig. 8 is the sequential chart of each signal line states when being illustrated in inside and carrying out being written to addition results in the Q unit 36 under the situation of addition process.
Fig. 9 be illustrated in voltage and electric charge that ferro-electric materials capacitor CF go up to produce, be the graph of a relation of polarized state.
Figure 10 is the structural drawing of expression conduct based on the FET50 of other example memory element of the present invention.
The best mode that carries out an invention
Below, describe implementing best example of the present invention with reference to accompanying drawing.
Fig. 1 is the one-piece construction figure of expression based on the functional memory 10 of the storer of the tape handling function of the present invention's one example.Functional memory 10 comprises: cell matrix portion 12, word decoder 14, driving circuit 16, data decoder 18, sensor amplifier 20, position demoder 22, as a plurality of transistors 24 of read-write switch means, read-write control unit 26 and as a plurality of totalizers 28 of inter-process means.
In cell matrix portion 12, ranks configurations is as the W unit 34 of the 1st memory element with as the Q unit 36 of the 2nd memory element.Alternate configurations with W unit 34 as the row of key element with the row of Q unit 36 as key element.
As shown in Figure 2,, constitute the W word LW1 of portion as the 1st word portion with the row of W unit 34 as key element, LW2 ...With the row of Q unit 36 as key element, constitute the Q word LQ1 of portion as the 2nd word portion, LQ2 ...Utilize adjacent W word portion and Q word portion, constitute a pair of word L of portion.For example, utilize the LW1 of W word portion and the LQ1 of Q word portion, constitute a pair of 1 L1 of word portion.
The W unit 34 and the Q unit 36 of the correspondence of a pair of word portion constitute a pair of unit 38 as a pair of memory component.
Fig. 3 shows the structure of W unit 34.W unit 34 comprises ferro-electric materials capacitor CF.By means of sandwich strong dielectric film (PZT (PbZr for example with 2 cube electrodes
xTi
1-xO
3)), form ferro-electric materials capacitor CF.By as the external transistor T 1 of switch means, the end 40 of the ferro-electric materials capacitor CF that forms like this is connected on the data line D.In addition, between data line D and ground G, form load electricity consumption container C B1.In this example, load electricity consumption container C B1 is formed by the stray capacitance of data line D.The grid of transistor T 1 is connected on the word line WW.
By transistor T 2, the end 40 of ferro-electric materials capacitor CF is connected on the internal data line MW as the internal switch means.In addition, between internal data line MW and ground G, form load electricity consumption container C B2.In this example, load electricity consumption container C B2 is formed by the stray capacitance of internal data line MW.The grid of transistor T 2 is connected on the bit line Bit.
The other end 42 of ferro-electric materials capacitor CF is connected on the drive wire Drive.
The structure of Q unit is also basic identical with the structure of W unit 34.Wherein, in Q unit 36, the grid of transistor T 1 is connected on the word line WQ, in addition,, the end 40 of ferro-electric materials capacitor CF is connected on the internal data line MQ by transistor T 2.
Get back to Fig. 1, utilize word decoder 14 to select any word line WW or WQ, select desired W word portion or Q word portion.Utilize data decoder 18 to select any data line D, select desired position B.That is to say, utilize word decoder 14 and data decoder 18,, carry out reading in of information from the outside for selecteed W arbitrarily unit 34 or Q unit 36.At this moment, driving circuit 16 supplies to the voltage of regulation on the drive wire Drive.Sensor amplifier 20 is as from W unit 34 or amplification means during Q unit 36 sense informations and write means again.
Utilize position demoder 22, select bit line Bit, to select desired position B.That is to say, for whole L1 of word portion, L2 ...,, carry out internal arithmetic and handle for the position of selecting by position demoder 22 arbitrarily.Identical with the occasion (aforementioned) from the Card read/write of outside, at this moment, driving circuit 16 supplies to the voltage of regulation on the drive wire Drive.
As shown in Figure 2, by transistor 24 and sensor amplifier 30, internal data line MW and MQ are connected on the totalizer 28.In internal arithmetic is handled, read into the last and appearance output of internal data line MW and MQ.Sensor amplifier 30 as from W unit 34 and Q unit 36 sense informations the time the amplification means and write means again.By buffer circuits 32, the output of totalizer 28 is connected on the internal data line MQ.A pair of sensor amplifier 30 and 1 buffer circuits 32 are set at each on to word portion.Utilization is used for the totalizer 28 and the buffer circuits 32 of whole word portion, constitutes read-write control unit 26 (with reference to Fig. 1).The grid of transistor 24 is connected on the read-write control line R/W.
Internal arithmetic handle read the time, utilize read-write control line R/W to make transistor 24 become conducting (ON) state, by sensor amplifier 30 will be from W unit 34 or Q unit 36 output of reading deliver to the totalizer 28.Fashionable writing of handling of internal arithmetic, utilize read-write control line R/W to make transistor 24 become disconnection (OFF) state, by buffer circuits 32, internal data line MQ, the output of totalizer 28 is written in the Q unit 36.
Fig. 4 shows an example of the structure of sensor amplifier 30.Constitute this sensor amplifier 30 with 4 transistors.In addition, be connected with outside with 4.1 is connected on the internal data line MW, and 1 is connected on the reference voltage line MWBar (in the drawings horizontal line being attached on the MW) in addition.In addition, reference voltage line MWBar is connected on the equivalence element (dummy cell) (not shown) that produces reference voltage.2 of other of sensor amplifier are connected respectively on line SAP, the SANBar (in the drawings horizontal line being attached on the SAN).By means of suitable voltage is supplied on line SAP, the SANBar, can make sensor amplifier 30 actions.
Fig. 5 shows an example of the structure of buffer circuits 32.Sort buffer device circuit 32 is made of 4 transistors, and is connected on the output terminal and internal data line MQ of totalizer 28.In addition, be connected to the read-write control reverse signal line R/WBar (in the drawings horizontal line being attached on the R/W) that imports as control.
When the signal of read-write control reverse signal line R/WBar during for " 0 " when reading (internal arithmetic handle), internal data line MQ is a high impedance status.When the signal of read-write control reverse signal line R/WBar is " 1 " (writing of internal arithmetic processing is fashionable), the output counter-rotating of totalizer 28, and supply on the internal data line MQ.In addition, the totalizer 28 of formation is to consider the addition of carry, with addition results counter-rotating and output.
Below, just describe for the read-write motion of functional memory 10 from the outside.Fig. 6 A is the sequential chart of each signal line states when representing from outside writing information.Fig. 6 B is the sequential chart of each signal line states of expression when outside sense information.
Below, the action to from outside writing information the time describes with reference to Fig. 2, Fig. 6 A.From outside writing information the time, at first, make whole bit line Bit and read-write control line R/W be " 0 ".Thus, because of whole transistor T 2 and whole transistors 24 are " OFF " state, so whole internal data line MW and MQ become high impedance status.
In this state, make the word line WW or the WQ that are connected to the unit of wanting writing information become " 1 " (with reference to (a) of Fig. 6 A).Below, for the purpose of illustrating, suppose that the unit of wanting writing information is W unit 34 shown in Figure 2.By means of making described word line WW be " 1 ", the transistor T 1 that is connected with this word line WW becomes the ON state.Thus, by transistor T 1, will want the end 40 of ferro-electric materials capacitor CF of the unit of writing information to be connected on the data line D.At this moment, because of drive wire Drive and data line D are " 0 " (with reference to Fig. 6 A (b)), the two ends of ferro-electric materials capacitor CF become idiostatic.Therefore, in this state, the polarized state of ferro-electric materials capacitor CF is constant.
Then, make drive wire Drive become " 1 " (with reference to (c) of Fig. 6 A).By means of making drive wire Drive become " 1 ", the other end 42 of ferro-electric materials capacitor CF becomes " 1 ".At this moment, still to keep intact be " 0 " to the end 40 of ferro-electric materials capacitor CF.Therefore, on the other end 42 of ferro-electric materials capacitor CF, apply positive voltage with respect to an end 40.
Fig. 9 is the graph of a relation that is illustrated in the voltage that ferro-electric materials capacitor CF go up to produce (being the voltage of the other end 42 under the situation of benchmark with the end 40 of ferro-electric materials capacitor CF) and electric charge (being located at the electric charge that produces on ferro-electric materials capacitor CF when applying positive voltage on the other end 42 of ferro-electric materials capacitor CF just is), polarized state.As shown in Figure 9, by means of apply positive voltage on the other end 42 of ferro-electric materials capacitor CF, ferro-electric materials capacitor CF presents polarized state P1.
In the occasion of wanting writing information " 0 ", be maintained to data line D former state " 0 " (with reference to (d) of Fig. 6 A).
Then, make drive wire Drive become " 0 " (with reference to (e) of Fig. 6 A).Thus, the two ends of ferro-electric materials capacitor CF become idiostatic once more.Therefore, ferro-electric materials capacitor CF becomes polarized state P2 shown in Figure 9 (corresponding to information " 0 ").
In the occasion of wanting writing information " 1 ", data line D becomes " 1 " (with reference to (f) of Fig. 6 A).Thus, the two ends of ferro-electric materials capacitor CF become idiostatic.Therefore, ferro-electric materials capacitor CF becomes polarized state P2 shown in Figure 9 for the time being.
It is constant further data line D to be held in " 1 " again, and drive wire Drive becomes " 0 " (with reference to (e) of Fig. 6 A).Thus, on the other end 42 of ferro-electric materials capacitor CF, apply negative voltage with respect to an end 40.Therefore, ferro-electric materials capacitor CF becomes polarized state P3 shown in Figure 9.
Then, making data line D is " 0 " (with reference to (g) of Fig. 6 A).Thus, the two ends of ferro-electric materials capacitor CF become idiostatic once more.Therefore, ferro-electric materials capacitor CF becomes polarized state P4 shown in Figure 9 (corresponding to information " 1 ").
Like this, after writing desired information, making word line WW is " 0 " (with reference to (o) of Fig. 6 A), becomes the OFF state by such transistor T 1.Therefore, the end 40 of ferro-electric materials capacitor CF is a high impedance status, finishes to write processing.
Like this, (W unit 34, Q unit 36) is can write desired information " 0 " or " 1 " on the desired position of desired word portion (W word portion, Q word portion) in desired unit.
Below, with reference to Fig. 2, Fig. 6 B to the action when the outside sense information describes from desired unit.Identical with situation about writing, to outside sense information the time, at first, make whole bit line Bit and read-write control line R/W be " 0 ".Thus, because of whole transistor T 2 and whole transistors 24 are " OFF " state, so whole internal data line MW and MQ become high impedance status.
In this state, make to be connected to that to want the data line D of the unit read be " 0 " (with reference to (h) of Fig. 6 B).By means of making data line D be " 0 ", make the load electricity consumption container C B1 precharge that is connected with this data line D.In addition, precharge makes data line D become high impedance status after finishing.
Then, make and be connected to that to want the word line WW or the WQ of the unit read be " 1 " (with reference to (i) of Fig. 6 B).Below, for the purpose of illustrating, suppose that the unit of wanting sense information is W unit 34 shown in Figure 2.By means of making described word line WW be " 1 ", the transistor T 1 that is connected with this word line WW becomes the ON state.Thus, by this transistor T 1, the precharge load electricity consumption container C B1 and the ferro-electric materials capacitor CF of the unit of wanting to read are connected in series.
Then, make drive wire Drive become " 1 " (with reference to (j) of Fig. 6 B).Become " 1 " by means of drive wire Drive, on the two ends of load electricity consumption container C B1 that is connected in series and ferro-electric materials capacitor CF, apply the voltage of regulation.One applies the voltage of this regulation, then just change of the current potential of the data line D that links to each other with the tie point of load electricity consumption container C B1 and ferro-electric materials capacitor CF.The current potential of data line D changes corresponding to the information content (polarized state) that is stored among the ferro-electric materials capacitor CF.
When the information content in being stored in ferro-electric materials capacitor CF is " 0 " (corresponding to polarized state P2 shown in Figure 9), the current potential of data line D almost constant (with reference to (k) of Fig. 6 B).
Then, the sensor amplifier (not shown) of sensor amplifier unit 20 (with reference to Fig. 1) action.Sensor amplifier detects the variation of the current potential of data line D, judges that the information content is " 0 ", makes the voltage of data line D be " 0 " forcibly.By means of the information of reading from sensor amplifier at this moment, can know this unit canned data " 0 ".
By means of the voltage that makes data line D forcibly is " 0 ", and ferro-electric materials capacitor CF presents polarized state P1 shown in Figure 9.Then, make drive wire Drive turn back to " 0 " (with reference to (m) of Fig. 6 B), become polarized state P2 shown in Figure 9 by such ferro-electric materials capacitor CF.So, will write back in the unit once more with the information " 0 " of the information identical content of reading.This is to write processing again.
On the other hand, the information content in being stored in ferro-electric materials capacitor CF is under the situation of " 1 " (corresponding to polarized state P4 shown in Figure 9), when applying the voltage of aforementioned regulation for the load electricity consumption container C B1 that is connected in series and ferro-electric materials capacitor CF, the current potential of data line D slightly changes (with reference to (n) of Fig. 6 B).
Therefore, the sensor amplifier of sensor amplifier unit 20 (with reference to Fig. 1) judges that the information content is " 1 ", and the voltage that makes data line D forcibly by means of the information of reading from sensor amplifier at this moment, can be known this unit canned data " 1 " for " 1 ".
By means of the voltage that makes data line D forcibly remain " 1 " constant, then, make drive wire Drive turn back to " 0 " (with reference to (m) of Fig. 6 B).Ferro-electric materials capacitor CF becomes polarized state P3.Like this, will write back in the unit once more with the information " 1 " of the information identical content of reading.
Like this, after end was read and write, making word line WW was " 0 " (with reference to (p) of Fig. 6 B), and transistor T 1 becomes the OFF state.Therefore, the end 40 of ferro-electric materials capacitor CF is a high impedance status, finishes to read processing.
Below, the action when carrying out addition process in the inside of functional memory 10 describes.Fig. 7 A is the sequential chart of each signal line states when being illustrated in inside and carrying out under the situation of addition process from W unit 34 sense informations.Fig. 7 B is the state sequential chart of each signal wire when being illustrated in inside and carrying out Q unit 36 sense informations under the situation of addition process.Fig. 8 is the state sequential chart of each signal wire when being illustrated in inside and carrying out being written to addition results in the Q unit 36 under the situation of addition process.
Action when addition process is carried out in the inside of functional memory 10 can separately be considered to from W unit 34 and Q unit 36 sense informations till carry out additive operation action and the additive operation result is written to action in the Q unit 36.
At first, with reference to Fig. 2, Fig. 7 A, Fig. 7 B to describing to the action of carrying out till the additive operation from W unit 34 and Q unit 36 sense informations.When carrying out additive operation, at first, make whole word line WW and WQ become " 0 " in advance in inside.Thus, because of whole transistor T 1 is the OFF state, so unit and whole data line D cut-outs.
Carry out concurrently from the processing of W unit 34 sense informations with from the processing of Q unit 36 sense informations.At first, making read-write control line R/W is " 1 " (with reference to (a) of Fig. 7 A and Fig. 7 B).Thus, because of whole transistor 24 becomes the ON state, so, whole internal data line MW and MQ are linked to each other with totalizer 28 with sensor amplifier 30 by transistor 24.
Then, making whole internal data line MW and MQ is " 0 " (with reference to (b) of Fig. 7 A and Fig. 7 B).By means of making whole internal data line MW and MQ be " 0 ", the whole load electricity consumption container C B2 precharge that then is connected with internal data line MW and MQ.In addition, precharge makes internal data line MW after finishing, and MQ becomes high impedance status.
Then, make and constitute the bit line Bit that the unit of wanting to carry out the position that additive operation handles links to each other and become " 1 " (with reference to (c) of Fig. 7 A and Fig. 7 B).Below, for the purpose of illustrating, suppose that wanting to carry out the position that additive operation handles is position B1 shown in Figure 2.In addition, though for a plurality of word L1 of portion, L2 ... handle concurrently simultaneously, but only describe for the 1st L1 of word portion.
By means of making bit line Bit become " 1 ", the transistor T 2 that is connected to this bit line Bit becomes the ON state, therefore, by this transistor T 2, with precharge load electricity consumption container C B2 and the ferro-electric materials capacitor CF that constitutes the unit want to carry out the position that additive operation handles be connected in series.
Then, make drive wire Drive become " 1 " (with reference to (d) of Fig. 7 A and Fig. 7 B).By means of making drive wire Drive become " 1 ", on the two ends of load electricity consumption container C B2 that is connected in series and ferro-electric materials capacitor CF, apply the voltage of regulation.One applies the voltage of this regulation, then just change respectively of the current potential of internal data line MW that links to each other with the tie point of load electricity consumption container C B2 and ferro-electric materials capacitor CF and MQ.The current potential of internal data line MW and MQ corresponds respectively to the information content (polarized state) that is stored among the ferro-electric materials capacitor CF and changes.
When the information content in being stored in ferro-electric materials capacitor CF is " 0 " (corresponding to polarized state P2 shown in Figure 9), the internal data line MW of storage " 0 " and the current potential almost constant (with reference to (e) of Fig. 7 A and Fig. 7 B) of MQ.
Then, sensor amplifier 30 actions.Sensor amplifier 30 detects the variation of the current potential of internal data line MW and MQ, judges that the information content is " 0 ", makes the voltage of internal data line MW and MQ be " 0 " forcibly.The information that at this moment totalizer 28 obtains from a pair of sensor amplifier 30.
By means of the voltage that makes internal data line MW and MQ forcibly is " 0 ", and ferro-electric materials capacitor CF presents polarized state P1 shown in Figure 9.Then, by means of making drive wire Drive turn back to " 0 " (with reference to (g) of Fig. 7 A and Fig. 7 B), ferro-electric materials capacitor CF becomes polarized state P2.Like this, will write back in the unit once more with the information " 0 " of the information identical content of reading.
On the other hand, the information content in being stored in ferro-electric materials capacitor CF is under the situation of " 1 " (corresponding to polarized state P4 shown in Figure 9), when applying the voltage of aforementioned regulation for the load electricity consumption container C B2 that is connected in series and ferro-electric materials capacitor CF, the internal data line MW of storage " 1 " and the current potential of MQ slightly change (with reference to (h) of Fig. 7 A and Fig. 7 B).
Therefore, sensor amplifier 30 judges that the information content is " 1 ", and the voltage that makes internal data line MW and MQ forcibly is " 1 " (with reference to (f) of Fig. 7 A and Fig. 7 B), the information that at this moment totalizer 28 obtains from a pair of sensor amplifier 30.
By means of the voltage that makes internal data line MW and MQ forcibly remain " 1 " constant, then, make drive wire Drive turn back to " 0 " (with reference to (g) of Fig. 7 A and Fig. 7 B).Become polarized state P3 by such ferro-electric materials capacitor CF.Like this, will write back in the unit once more with the information " 1 " of the information identical content of reading.
Like this, after end was read and write, making bit line Bit was " 0 " (with reference to (i) of Fig. 7 A and Fig. 7 B), and transistor T 2 becomes the OFF state.Therefore, the end 40 of ferro-electric materials capacitor CF is a high impedance status.
Then, read-write control line R/W turns back to " 0 " (with reference to (j) of Fig. 7 A and Fig. 7 B).Thus, because of transistor 24 at this moment is " OFF " state, so internal data line MW becomes high impedance status.In addition, because of the signal of read-write control reverse signal line R/WBar is " 1 ", so as previously mentioned,, the addition results of totalizer 28 is supplied to internal data line MQ (with reference to (k) of Fig. 7 A and Fig. 7 B) by buffer circuits 32.
Below, with reference to Fig. 2 and Fig. 8 the action that the aforesaid additive operation result that will supply to internal data line MQ is written in the Q unit 36 is described.Connection to the action of carrying out till the additive operation, makes word line WW and WQ and read-write control line R/W be " 0 " from W unit 34 and Q unit 36 sense informations.In addition as previously mentioned, the additive operation result with totalizer 28 supplies to internal data line MQ.On the other hand, internal data line MW becomes high impedance status.
At first in this state, making bit line Bit is " 1 " (with reference to (l) of Fig. 6).By means of making bit line Bit be " 1 ", the transistor T 2 that is connected on this bit line Bit becomes the ON state.Therefore, be connected on internal data line MW and the MQ by the end 40 of transistor T 2 ferro-electric materials capacitor CF.At this moment, because of internal data line MW is a high impedance status, so no matter the value of drive wire how, the memory contents that is connected to the W unit 34 on the internal data line MW is constant.
On the other hand, because of will supplying to internal data line MQ, so the memory contents that is connected to the Q unit 36 on the internal data line MQ rewrites according to the result of additive operation from the additive operation result of totalizer 28.
At first, the additive operation result is described for the situation of " 0 ".In this case, because of drive wire Drive and internal data line MQ are " 0 " (with reference to Fig. 8 (m), (n)), so the two ends of the ferro-electric materials capacitor CF of Q unit 36 are idiostatic.Therefore, in this state, the polarized state of ferro-electric materials capacitor CF is constant.
Then, make drive wire Drive become " 1 " (with reference to (o) of Fig. 8).By means of making drive wire Drive become " 1 ", the other end 42 of ferro-electric materials capacitor CF becomes " 1 ".At this moment, to be still " 0 " constant for the end 40 of ferro-electric materials capacitor CF.Therefore, on the other end 42 of ferro-electric materials capacitor CF, apply positive voltage with respect to an end 40.
As shown in Figure 9, by means of apply positive voltage on the other end 42 of ferro-electric materials capacitor CF, ferro-electric materials capacitor CF presents polarized state P1.Then, make drive wire Drive become " 0 " (with reference to (p) of Fig. 8).Thus, the two ends of ferro-electric materials capacitor CF become idiostatic once more.Therefore, ferro-electric materials capacitor CF presents polarized state P2 (corresponding to information " 0 ").
On the other hand, when the additive operation result was " 1 ", drive wire Drive was " 0 ", and opposite internal data line MQ is " 1 " (with reference to Fig. 8 (m), (n)).Therefore, on the other end 42 of the ferro-electric materials capacitor CF of Q unit 36, applied negative voltage with respect to an end 40.Therefore, ferro-electric materials capacitor CF presents polarized state P3 shown in Figure 9.
Then, make drive wire Drive become " 1 " (with reference to (o) of Fig. 8).Thus, the two ends of ferro-electric materials capacitor CF become idiostatic once more.Therefore, ferro-electric materials capacitor CF presents polarized state P4 shown in Figure 9 (corresponding to information " 1 ").
Further by means of making drive wire Drive become " 0 " (with reference to (p) of Fig. 8), ferro-electric materials capacitor CF presents polarized state P3 shown in Figure 9 once more again.Then, by means of placing ferro-electric materials capacitor CF at high impedance status, along with the time increases, a part of charge discharge becomes polarized state P4 shown in Figure 9.
Like this, after the additive operation result that will supply to internal data line MQ was written in the Q unit 36, bit line Bit was " 0 " (with reference to (r) of Fig. 8), and transistor T 2 becomes the OFF state.Therefore, the end 40 of ferro-electric materials capacitor CF becomes high impedance status.
Like this, for desired position, can for a plurality of word L1 of portion, L2 ... carry out simultaneously addition process concurrently.In order to carry out aforesaid addition process for whole position, as long as the position of carrying out addition process displacement is successively handled.
In addition, in aforementioned example, be that each is provided with a totalizer to word portion, but the configuration of totalizer and quantity are not limited thereto.It for example also may be the structure that each is provided with a totalizer.In addition, also can to memory element a totalizer be set to each.It also can be the structure that functional memory integral body only is provided with a totalizer.
In addition, in aforementioned example, be being that example is illustrated as the occasion of inter-process means with totalizer, but the inter-process means are not limited thereto, also can be with other arithmetical operation means, logical operation means and displacement means etc. of multiplier for example etc. as the inter-process means.
In addition, in aforementioned example, be to read the information that is stored in the 1st memory element and the information in the 2nd memory element of the being stored in row operation of going forward side by side is handled, and result is written to structure in the 2nd memory element, but the invention is not restricted to this structure.Also can for example be to read the information that is stored in the 1st memory element and the information in the 2nd memory element of the being stored in row operation of going forward side by side is handled, and result is written to structure in the 3rd memory element.In addition, also can be that the information that is stored in the 1st memory element is carried out square operation, and result is written to structure in the 2nd memory element.In addition, also can be to carry out square operation, and result of calculation is written to structure in the 1st original memory element being stored in the 1st memory element information.
In addition, in aforementioned example, as memory element is to be that example is illustrated with the load that comprises ferro-electric materials capacitor and be connected in series with ferro-electric materials capacitor with the memory element of capacitor, but memory element is not limited thereto, and also can use the FET (field effect transistor) with strong dielectric film shown in Figure 10.FET50 shown in Figure 10 is called the FET of MFMIS (metal Ferrorelectric Metal Insulator Silicon) structure, is sequentially to form grid oxidation film 54, floating boom 56, strong dielectric film 58 and control gate 60 on the CH of the channel formation region territory of semiconductor substrate 52.
Make substrate 52 ground connection of FET50 (N raceway groove), if positive voltage+V is supplied on the control gate 60, then polarization reversal just takes place in strong dielectric film 58.Even remove the voltage of control gate 60, because the remnant polarization of strong dielectric film 58 on the CH of channel formation region territory negative electric charge can take place.With it as for example one state.
On the contrary, if negative voltage-V is supplied on the control gate 60, then reverse polarization reversal just takes place in strong dielectric film 58.Even remove the voltage of control gate 60, because the remnant polarization of strong dielectric film 58 on the CH of channel formation region territory positive electric charge can take place.With it as " 0 " state.Like this, information (" 1 " or " 0 ") is written among the FET50.
In order to read the information that writes, read-out voltage Vr is supplied on the control gate 60.Read-out voltage Vr is set between the threshold voltage vt h0 of FET50 of the threshold voltage vt h1 of FET50 of one state and " 0 " state.Whether therefore, when supplying to read-out voltage Vr on the control gate 60, have the drain current of regulation to flow through by means of detecting, be " 1 " or " 0 " with regard to knowing the information that writes.When reading, the information that writes can not disappear.
Like this, adopt FET, then can so-called non-destructive read with strong dielectric film.Thus, when reading, destroy memory contents between can be not quickly.Quick action when therefore, reading action.In addition, consumed power is few.This external cause is the deterioration of strong dielectric film seldom, so further improved the reliability that keeps about memory contents.
Storer based on tape handling function of the present invention is characterized in that, the ferroelectric memory device of hysteresis characteristic canned data that utilizes strong dielectric is as memory element.
That is to say, because ferroelectric memory device is a non-volatile memory device, so do not want refresh activity etc.Therefore, can reduce transistor and the wiring number that uses.In addition, can read and write and calculation process with simple action.In addition, even the fault of generation power supply etc., the lot of data in the processing can not disappear yet.
Storer based on tape handling function of the present invention is characterized in that, comprises external switch means and internal switch means.
Therefore, be on-state by means of making external switch means, to make the internal switch means be off-state, can carry out the read-write to the information of memory element from the outside of storer.In addition, be off-state by means of making external switch means, to make the internal switch means be on-state, can carry out predetermined process to the information that is stored in the memory element with the inter-process means.
Storer based on tape handling function of the present invention, it is characterized in that, described inter-process means when the internal switch means are on-state from described memory element sense information, after the information of reading is carried out predetermined process, result is written in the memory element.
Therefore, can not carry out access, can handle the information that is stored in the memory element from the storer outside for memory element, and the information after the stores processor.Therefore, can carry out certain information processing, simultaneously the stores processor result in the inside of storer.
Storer based on tape handling function of the present invention is characterized in that, read-write switch means and buffer circuits are set,
When information being read into the internal processor means from described memory element, making internal switch means and read-write switch means is on-state, when being written to described result in the memory element, to make the internal switch means be on-state, make the read-write switch means simultaneously is off-state, and with described buffer circuits result is written in the memory component.
Therefore, by internal switch means and read-write switch means, when information being read into the internal processor means, can positively read,, when being written to described result in the memory element, can positively write by buffer circuits and internal switch means from described memory element.
Storer based on tape handling function of the present invention is characterized in that,
The 1st memory element and the 2nd memory element are set as described memory element,
Described inter-process means are read the information that is stored in the 1st memory element and the information in the 2nd memory element of being stored in is gone forward side by side, and row operation is handled, and result is written in the 2nd memory element.
Therefore, for must by means of 2 kinds of information of calculation process obtain new information and also in original information at least a kind of information under unwanted situation after the calculation process, can reduce the storage element number of packages, be more satisfactory.
Storer based on tape handling function of the present invention is characterized in that,
In a pair of word portion that each is made of the 1st word portion and the 2nd word portion, described inter-process means are set,
A pair of memory element unit with a pair of word portion correspondence carries out described calculation process, carries out side by side corresponding to many a plurality of calculation process to word portion simultaneously.
Therefore, energy bit serial and word carry out in parallel for many computings to word portion.Therefore, can carry out a large amount of information processings at high speed.
Storer based on tape handling function of the present invention is characterized in that,
Described inter-process means are totalizers.
Therefore, be particularly suitable in a large number and to carry out Flame Image Process of simple information processing etc. in real time.
Storer based on tape handling function of the present invention is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
Therefore, can make memory element with simple structure.Therefore, the storer of formation is small-sized, compact.
In aforesaid explanation, though describe the present invention with desirable example, be not limited to each used term, each term is used to illustrate, only otherwise depart from the scope of the present invention and spirit and within the scope of appended claim, can change.
Claims (20)
1. the storer of a tape handling function comprises the memory element of canned data and carries out the inter-process means of predetermined process for the information in the memory element of being stored in, it is characterized in that,
The ferroelectric memory device of hysteresis characteristic canned data that utilizes strong dielectric is as memory element.
2. the storer of tape handling function as claimed in claim 1 is characterized in that, comprises
Control whether can between the outside and described memory element of described storer, carry out message exchange external switch means and
Whether control can carry out message exchange between described inter-process means and described memory element internal switch means.
3. the storer of tape handling function as claimed in claim 2 is characterized in that,
Described inter-process means when the internal switch means are on-state from described memory element sense information, after the information of reading is carried out predetermined process, result is written in the memory element.
4. the storer of tape handling function as claimed in claim 3 is characterized in that,
Be arranged in the signal transmission pathway between described memory component and the inter-process means and read-write switch means internal switch means arranged in series and be used for described result is written to the buffer circuits of memory component,
When information being read into the internal processor means from described memory element, internal switch means and read-write switch means are on-state, when being written to described result in the memory element, the internal switch means are on-state, read while write switch means is off-state, and with described buffer circuits result is written in the memory component.
5. the storer of tape handling function as claimed in claim 3 is characterized in that,
The 1st memory element and the 2nd memory element are set as described memory element,
Described inter-process means are read the information that is stored in the 1st memory element and the information in the 2nd memory element of being stored in is gone forward side by side, and row operation is handled, and result is written in the 2nd memory element.
6. the storer of tape handling function as claimed in claim 5 is characterized in that,
Described the 1st memory element of a plurality of configurations is as the 1st word portion,
Described the 2nd memory element of a plurality of configurations is as the 2nd word portion,
In a pair of word portion that each is made of the 1st word portion and the 2nd word portion, described inter-process means are set,
A pair of memory element unit with a pair of word portion correspondence carries out described calculation process, carries out side by side corresponding to many a plurality of calculation process to word portion simultaneously.
7. the storer of tape handling function as claimed in claim 3 is characterized in that,
Described inter-process means are totalizers.
8. the storer of tape handling function as claimed in claim 1 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
9. the storer of tape handling function as claimed in claim 2 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
10. the storer of tape handling function as claimed in claim 4 is characterized in that,
The 1st memory element and the 2nd memory element are set as described memory element,
Described inter-process means are read the information that is stored in the 1st memory element and the information in the 2nd memory element of being stored in is gone forward side by side, and row operation is handled, and result is written in the 2nd memory element.
11. the storer of tape handling function as claimed in claim 4 is characterized in that,
Described inter-process means are totalizers.
12. the storer of tape handling function as claimed in claim 4 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
13. the storer of tape handling function as claimed in claim 10 is characterized in that,
Described the 1st memory element of a plurality of configurations is as the 1st word portion,
Described the 2nd memory element of a plurality of configurations is as the 2nd word portion,
In a pair of word portion that each is made of the 1st word portion and the 2nd word portion, described inter-process means are set,
A pair of memory element unit with a pair of word portion correspondence carries out described calculation process, carries out side by side corresponding to many a plurality of calculation process to word portion simultaneously.
14. the storer of tape handling function as claimed in claim 10 is characterized in that,
Described inter-process means are totalizers.
15. the storer of tape handling function as claimed in claim 10 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
16. the storer of tape handling function as claimed in claim 13 is characterized in that,
Described inter-process means are totalizers.
17. the storer of tape handling function as claimed in claim 13 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
18. the storer of tape handling function as claimed in claim 5 is characterized in that,
Described inter-process means are totalizers.
19. the storer of tape handling function as claimed in claim 6 is characterized in that,
Described inter-process means are totalizers.
20. the storer of tape handling function as claimed in claim 3 is characterized in that,
Described memory element comprises ferro-electric materials capacitor and the load capacitor that is connected in series with ferro-electric materials capacitor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19382897A JP4030076B2 (en) | 1997-07-18 | 1997-07-18 | Storage device with processing function |
| JP193828/97 | 1997-07-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1239576A true CN1239576A (en) | 1999-12-22 |
| CN1260735C CN1260735C (en) | 2006-06-21 |
Family
ID=16314428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB988013584A Expired - Fee Related CN1260735C (en) | 1997-07-18 | 1998-07-17 | Memory with processing function |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6055176A (en) |
| EP (1) | EP0928005B1 (en) |
| JP (1) | JP4030076B2 (en) |
| KR (1) | KR100561941B1 (en) |
| CN (1) | CN1260735C (en) |
| DE (1) | DE69833326T2 (en) |
| WO (1) | WO1999004398A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100345075C (en) * | 2001-12-20 | 2007-10-24 | 松下电器产业株式会社 | Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof |
| CN1697075B (en) * | 2004-05-14 | 2011-04-06 | 钰创科技股份有限公司 | Input buffer of low flucturation of input signal |
| CN101271728B (en) * | 2008-04-22 | 2011-05-11 | 清华大学 | Ferro-electric storage memory array structure for restraining small signal interference |
| CN1706001B (en) * | 2002-10-15 | 2012-03-21 | 索尼株式会社 | Memory device, motion vector detection device, and detection method |
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| KR100412992B1 (en) * | 2001-12-31 | 2003-12-31 | 주식회사 하이닉스반도체 | Ferroelectric random access memory |
| DE10323012B4 (en) | 2003-05-21 | 2005-06-02 | Austriamicrosystems Ag | Programmable integrated circuit and method of programming an integrated circuit |
| JP3898152B2 (en) | 2003-05-27 | 2007-03-28 | ローム株式会社 | Storage device with operation function and operation storage method |
| GB0705733D0 (en) * | 2007-03-26 | 2007-05-02 | Calrec Audio Ltd | Digital signal processing |
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| JP3191468B2 (en) * | 1993-01-13 | 2001-07-23 | 日本電気株式会社 | Video display memory integrated circuit |
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| JPH098247A (en) * | 1995-06-15 | 1997-01-10 | Hitachi Ltd | Semiconductor storage device |
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- 1998-07-17 KR KR1019997002275A patent/KR100561941B1/en not_active IP Right Cessation
- 1998-07-17 WO PCT/JP1998/003220 patent/WO1999004398A1/en active IP Right Grant
- 1998-07-17 CN CNB988013584A patent/CN1260735C/en not_active Expired - Fee Related
- 1998-07-17 EP EP98932568A patent/EP0928005B1/en not_active Expired - Lifetime
- 1998-07-17 DE DE69833326T patent/DE69833326T2/en not_active Expired - Fee Related
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100345075C (en) * | 2001-12-20 | 2007-10-24 | 松下电器产业株式会社 | Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof |
| CN1706001B (en) * | 2002-10-15 | 2012-03-21 | 索尼株式会社 | Memory device, motion vector detection device, and detection method |
| CN1697075B (en) * | 2004-05-14 | 2011-04-06 | 钰创科技股份有限公司 | Input buffer of low flucturation of input signal |
| CN101271728B (en) * | 2008-04-22 | 2011-05-11 | 清华大学 | Ferro-electric storage memory array structure for restraining small signal interference |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0928005B1 (en) | 2006-01-25 |
| US6055176A (en) | 2000-04-25 |
| DE69833326D1 (en) | 2006-04-13 |
| KR20000068584A (en) | 2000-11-25 |
| KR100561941B1 (en) | 2006-03-21 |
| JP4030076B2 (en) | 2008-01-09 |
| JPH1139883A (en) | 1999-02-12 |
| CN1260735C (en) | 2006-06-21 |
| WO1999004398A1 (en) | 1999-01-28 |
| DE69833326T2 (en) | 2006-09-28 |
| EP0928005A1 (en) | 1999-07-07 |
| EP0928005A4 (en) | 2000-08-16 |
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