CN1224301C - 高频模块 - Google Patents
高频模块 Download PDFInfo
- Publication number
- CN1224301C CN1224301C CNB028009339A CN02800933A CN1224301C CN 1224301 C CN1224301 C CN 1224301C CN B028009339 A CNB028009339 A CN B028009339A CN 02800933 A CN02800933 A CN 02800933A CN 1224301 C CN1224301 C CN 1224301C
- Authority
- CN
- China
- Prior art keywords
- module
- mentioned
- secondary module
- cavity
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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Abstract
一种能抑制整体合格率下降的高频模块。它包括:有第1高频电路,并且,至少一部分是由装在多层基板内的导体图形构成的主模块、以及有第2高频电路的次模块,上述次模块***到设在上述主模块内的空腔内。按照本发明,则具有第1高频电路的主模块和具有第2高频电路的次模块分别构成单个零件。另一方面通过把次模块***到主模块内的空腔内而形成一体化,所以,能够只利用通过制造后的检查而确定为合格品的主模块和次模块。因此,能大大提高高频模块整体的合格率。
Description
技术领域
本发明涉及高频模块,进一步详细来说是涉及合格率高而且通用性强的高频模块。
背景技术
最近,以手机为代表的信息通信终端的小型化迅猛发展。对此,组装在信息通信终端内的各种零件的小型化发挥了重大作用。组装在信息通信终端内的重要零件,除了进行收发信号切换的高频开关外,在发送侧电路中有功率放大器和电压控制振荡器(VCO)等,在接收侧电路中有低噪声放大器和混频器等。
为了使组装在这些信息通信终端中的零件进一步小型化,对2个或2个以上的零件实现一体化进行了大量试验。这样,如果使2个或2个以上的零件一体化,构成模快,那么与这些零件分别安装到母电路板上时相比,能减小安装面积,能达到整体小型化。
这样,虽然如果使2个以上的零件一体化,构成模快,那么能达到整体小型化,但是在对太多的零件进行一体化时,该模块的合格率会大幅度降低。也就是说,在2个以上零件进行一体化构成模块的情况下,如果组装在这些模块中的零件中即使有一个不合格,就会使整个模块不合格,所以,该模块的合格率是其中组装的各个零件的合格率的积。例如,合格率分别为95%的5个零件进行一体化构成模块时,模块整体的合格率约下降到77%(0.955)。这样,过去存在的问题是:许多零件一体化构成模块时,模快整体的合格率降低。
再者,对多个零件进行一体化构成模块的情况下,要求一部分零件更改特性的情况下,必须重新设计整体模块本身,所以,也存在通用性较差的问题。
发明内容
所以,本发明的目的在于提供一种能抑制整体合格率降低的高频模块。
并且,本发明的另一目的在于提供通用性强的高频模块。
本发明的上述目的是利用这样一种高频模块来达到的,即其特征在于具有:有第1高频电路,并且,至少一部分是由装在多层基板内的导体图形构成的主模块、以及有第2高频电路的次模块,上述次模块***到设在上述主模块内的空腔内。
按照本发明,提供了一种高频模块,其特征在于包括:主模块,包括:第一基板,在其正面上形成有空腔,在其背面上形成有用于与天线连接的天线端子;在上述空腔的底表面上形成的第一电极;和形成的连接上述第一电极和天线端子的阻抗匹配电路,该阻抗匹配电路包括第一基板内设置的导体图形,次模块,包括:形成有高频电路的第二基板,和在该第二基板背面上形成的与上述高频电路连接的第二电极,其中,上述次模块被***到上述主模块中的空腔内,上述第一和第二电极相互电连接。
在本发明的良好实施例中,上述第1高频电路是由装在多层基板内的导体图形、以及装在多层基板上的电子元件构成。
在本发明的另一良好实施例中,上述次模块由多层基板构成。
在本发明的另一良好实施例中,构成上述主模块的多层基板和构成上述次模块的多层基板,由互不相同的材料构成。
在本发明的另一良好实施例中,构成上述主模块的多层基板由多块树脂基板的积层体构成。
在本发明的另一良好实施例中,构成上述次模块的多层基板由多层陶瓷基板的积层体构成。
在本发明另一良好实施例中,设置在上述主模块的上述空腔的底面上的多个电极、以及设置在上述次模块的底面上的多个电极,分别进行电连接。
在本发明另一良好实施例中,设置在上述主模块的上述空腔的底面上的多个电极、以及设置在上述次模块的底面上的多个电极,分别用锡焊方法进行电连接。
在本发明另一良好实施例中设置在上述主模块的上述空腔的底面上的多个电极、以及设置在上述次模块的底面上的多个电极,分别通过各向异性导电片进行电连接。
在本发明另一良好实施例中 ***了上述次模块的上述空腔的上部用金属板堵盖。
在本发明另一良好实施例中 上述金属板与设置在上述主模块上面的接地图形相连接。
在本发明另一良好实施例中构成上述主模块的多层基板内还装有阻抗匹配部,用于对上述第1高频电路和上述第2高频电路进行阻抗匹配。
在本发明另一良好实施例中 上述第1高频电路是从前端模块部、功率放大器模块部、合成器模块部、LSI部、SAW滤波器模块部构成的组中选择的至少一个电路。
在本发明另一良好实施例中上述第2高频电路是前端模块部、功率放大器模块部、合成器模块部、、LSI部、SAW滤波器模块部构成的组,是从构成上述第1高频电路的电路除外的组中选择的至少一个电路。
本发明的上述目的是利用这样一种高频模块而达到的,该高频模块具有第1和第2空腔,其中分别能***第1和第2次模块,其特征在于:规定的高频电路实现了一体化,同时内部装有阻抗匹配电路,用于对上述第1次模块和第2次模块进行阻抗匹配。
按照本发明,则第1和第2次模块能分别***到第1和第2空腔内,所以,能够仅利用通过制造后的检查而被认定为合格品的次模块。因此,能大大提高高频模块整体的合格率。并且,若按照本发明,则在要求对各个次模块内的电路进行特性更改的情况下,也只重新设计需要更改的次模块即可,所以能提高通用性。并且,由于内部装有阻抗匹配电路,用于对第1次模块和第2次模块进行阻抗匹配,所以,不需要附加阻抗匹配电路,能达到整体小型化。
在本发明的良好实施例中,还在内部装有阻抗匹配电路,以便对上述高频电路和上述第1次模块进行阻抗匹配。
附图说明
图1是本发明良好实施例中的高频模块1的电路结构的概要方框图。
图2是本发明良好实施例中的高频模块1结构中的主模块60的形状图。(a)是平面图,(b)和(c)分别是沿(a)所示的a-b线的断面图,以及沿c-d线的断面图。
图3是构成合成器模块部6的电压控制振荡器33和阻抗匹配部11(一部分)的电路结构一例的具体电路图。
图4(a)是构成前端模块部4的次模块80从背面看的概要斜视图,图4(b)是其断面图。
图5(a)是构成功率放大器模块5的次模块90从背面看的概要斜视图,图5(b)是其断面图。
图6是构成LSI部7的半导体芯片封装品100从背面看的概要斜视图。
图7(a)是构成SAW滤波器模块部8的次模块110从背面看的概要斜视图。图7(b)是其断面图。
图8是表示高频模块1的形状的图,其结构是次模块80、次模块90,半导体芯片封装品100和次模块110分别被***在主模块60中的第1~第4空腔61~64内。(a)是平面图,(b)是沿(a)所示的a-b线的断面图。
图9是本发明另一良好实施例中的高频模块120的形状图,(a)是平面图,(b)是沿(a)所示的e~f线的断面图。
图10(a)是各向异性导电片121的概要平面图,图10(b)是表示(a)所示g-h断面的概要断面图。
具体实施方式
以下参照附图,详细说明本发明的良好实施例。
图1是本发明良好实施例中的高频模块1的电路结构的概要方框图。这并非特意限定的。本发明实施例中的高频模块1组装和使用于能用2种方式通话的所谓双频带手机内。在此,所谓2种方式,是指例如GSM方式和DCS方式,二者均为欧洲采用的移动电话方式。在GSM方式中,接收频率为925~960MHz,发射频率为880~915MHz,在DCS方式中,接收频率为1805~1880MHz,发射频率为1710~1785MHz。
如图1所示,本实施例中的高频模块1设置在双频带手机的天线2和基带电路3之间,其作用是:把由天线2接收的接收信号供给到基带电路3内,同时把由基带电路部3供给的发送信号发送到天线2内。
更具体来说,高频模块1具有:前端模块部4、功率放大器模块部5、合成器模块部6、LSI部7、SAW(表面波)滤波器模块部8、和阻抗匹配部9~14。
前端模块部4具有:对用于GSM方式的频带信号和用于DCS方式的频带信号进行分离的天线分离滤波器(DPX)15、在GSM侧对收发信号进行切换的高频开关(SW)16,在DCS侧对收发信号进行切换的高频开关(SW)17、分别连接在高频开关16和17的发送侧节点(TX)上的低低通滤波器(LPF)18和19、分别连接在高频开关16和17的接收侧节点(RX)上的SAW滤波器(SAW)20和21。如下所述,这些天线分离滤波器15、高频开关16和17、低通滤波器18和19,SAW滤波器20和21作为一个次模块,构成一体化。
再者,前端模块部4,作为外部端子具有:天线端子22、GSM侧发射端子23、DCS侧发射端子24、GSM侧接收端子25、DCS侧接收端子26。天线端子22被连接在天线分离滤波器15的天线节点上,GSM侧发射端子23连接在低通滤波器18上,DCS侧发射端子24连接在低通滤波器19上,GSM侧接收端子25连接在SAW滤波器20上,DCS侧接收端子26连接在SAW滤波器21上。
功率放大器模块部5具有:放大GSM侧的发射信号的GSM侧功率放大器(GMS PA)27、以及放大DCS侧的发射信号的DCS侧功率放大器(DCS PA)28。如下所述,这些作为一个次模块构成一个整体。再者,功率放大器模块部5,其外部端子有:分别向GSM侧功率放大器27和DCS侧功率放大器28供给输入信号的输入端子29和30、分别从GSM侧功率放大器27和DCS侧功率放大器28供给输出信号的输出端子31和32。
合成器模块6具有:对GSM方式的声音信号等进行调制的电压控制振荡器(VCO)33、以及对DCS方式的声音信号等进行调制的电压控制振荡器(VCO)34,如下所述,他们被装在主模块内。再者,合成器模块部6,其外部端子有:分别向电压控制振荡器33和34供给输入信号的输入端子35和36。输入端子35和36如图1所示,连接在基带电路部3上。
LSI部7具有:放大GSM侧的接收信号的GSM侧低噪声放大器(LNA)37、放大DCS的接收信号的DCS侧低噪声放大器(LNA)38、根据GSM侧的接收信号来合成中频的GSM侧混频器(M1X)39、以及根据DCS侧的接收信号来合成中频的DCS侧混频器(M1X)、40。如下所述,这些都集成在一个半导体芯片内。再者,LSI部7,其外部端子有:分别向GSM侧低噪声放大器37和DCS侧低噪声放大器38供给输入信号的输入端子41和42、分别从GSM侧低噪声放大器37和DCS侧低噪声放大器38供给输出信号的输出端子43和44、分别向GSM侧混频器39和DCS侧混频器40内供给输入信号的输入端子45和46、以及分别从GSM侧混频器39和DCS侧混频器40中供给输出信号的输出端子47和48。其中,输出端子47和48如图1所示连接在基带电路部3上。
SAW滤波器模块部8具有:从GSM侧的接收信号中取出所需的频带(925~960MHz)的信号的GSM侧SAW滤波器(SAW)49、以及从DCS侧的接收信号中取出所需频带(1805~1880MHz)的信号的DCS侧SAW滤波器(SAW)50。如下所述,它们作为一个次模块构成一个整体,再者,SAW滤波器模块部8,其输出端子有:分别把输入信号供给到GSM侧SAW滤波器49和DCS侧SAW滤波器50内的输入端子52和53、以及分别从GSM侧SAW滤波器49和DCS侧SAW滤波器50中供给输出信号的输出端子54和55。
而且,对于上述前端模块部4、功率放大器模块部5、合成器模块部6、LSI部7、SAW滤波器模块部8说明了的外部端子,是仅表示其具有的主要外部端子,此外,也还有电源端子和各种控制端子(例如,对高频开关16进行切换控制用的控制端子)等其他外部端子。
并且,高频模块1具有与天线2相连接的天线端子56,阻抗匹配部9连接在所用天线端子56和前端模块部4的天线端子22之间,对两者进行阻抗匹配。
同样,阻抗匹配部10连接在前端模块部4和GSM侧发射端子23和DCS侧发送端子24、以及功率放大器模块部5的输出端子31和32之间,对其进行阻抗匹配。阻抗匹配部11连接在功率放大器模块部5的输入端子29和30、以及合成器模块部6的电压控制振荡器33和34的输出接点之间,对其进行阻抗匹配。阻抗匹配部12连接在前端模块部4的GSM侧接收端子25和DCS侧接收端子26以及LSI部7的输入端子41和42之间,对其进行阻抗匹配。阻抗匹配部13连接在LSI部7的输出端子43和44以及SAW滤波器模块部8的输入端子52和53之间,对其进行阻抗匹配。阻抗匹配部14连接在LSI部7的输入端子45和46、以及SAW滤波器模块部8的输出端子54和55之间,对其进行阻抗匹配。
以下说明涉及本实施例的高频模块1的具体形状。
图2是涉及本实施例的构成高频模块1的主模块60的形状图,(a)是平面图,(b)和(c)分别表示沿(a)所示a-b线的断面图、以及沿c-d线的断面图。
如图2(a)~(c)所示,涉及本发明实施例的构成高频模块1的主模块60的平面形状为约18mm×约20mm的长方形,其厚度约为2.0mm。主模块60由以下多层基板和各种电子元件(二极管等)76构成;上述多层基板由多个树脂基板积层而成,其内部形成了:构成规定的元件(电感等)、和布线的导体图形74以及穿通孔电极75;上述各种电子元件安装在上述多层基板上。如图2(a)和(b)所示,主模块60的一部分构成合成器模块部6,该部分的平面尺寸约为11mm×10mm。主模块60中,构成合成器模块部6的部分以外的位置上,设置了第1~第4空腔61~64。并且,主模块60中,构成合成器模块部6的部分上面,设置了切断电磁波用金属帽盖77。
第1空腔61用于***为构成前端模块部4的次模块,其平面形状为3.5mm×8.5mm,深为0.6mm。并且,第2空腔62用于***为构成功率放大器模块部5的次模块。其平面形状为11.5mm×8.5mm,深为0.6mm。第3空腔63用于***为构成LSI部7的半导体芯片封装品,其平面形状为5.5mm×4.5mm,深度为0.6mm。第4空腔64用于***为构成SAW滤波器模块部8的次模块,其平面形状为3.5mm×3.0mm,深度为0.6mm。
如图2(c)所示,在第1空腔61的底面上设置了多个焊点65,这样一来,若把构成前端模块部4的次模块***到第1空腔61内,则该次模块上的天线端子22、GSM侧发送端子23、DCS侧发送端子24、GSM侧接收端子25和DCS侧接收端子26等外部端子就和焊点65进行牢靠的电气连接。
同样,如图2(b)所示,在第2空腔62的底布,设置了多个焊点66,这样一来,若把构成功率放大器模块部5的次模块***到第2空腔62内,则该次模块上的输入端子29、30和输出端子31、32等外部端子就与焊点66进行牢靠的电气连接。
如图2(c)所示,在第3空腔63的底面上,设置多个焊锡凸点67,这样一来,若把构成LSI部7的半导体芯片封装品***到第3空腔63内,则设置在该次模块上的输入端子41、42、45、46和输出端子43、44、47、48等外部端子就和焊锡凸点67牢靠地进行电连接。
再者,同样,如图2(c)所示,在第4空腔64的底面上设置多个焊锡凸点68,这样一来,若把构成SAW滤波器模块8的次模块***到第4空腔64内,则设置在该次模块上的输入端子52、53和输出端子54、55等外部端子就与焊锡凸点68进行可靠的电连接。
再者,在主模块60的背面上设置了天线端子56等多个外部端子69,若把主模块60安装到母板(无图示)上,则该外部端子69就和设置在母板上的端子可靠地进行电连接。
再者,如图2(b)和(c)所示,在主模块60内,除了合成器模块部6以外,还装入了用导体图形74构成的阻抗匹配部9~14(在图2(b)、 (c)中,仅表示出了阻抗匹配部11和13)。
图3是电路结构一例的具体电路图,它表示构成合成器模块部6的电压控制振荡器33和阻抗匹配部11(一部分)。
如图3所示,电压控制振荡器33具有:电压可调谐振电路71、振荡电路72、输出放大电路73。控制电压和调制电压通过输入端子35(35-1、35-2)从基带电路部3供给到电压可调谐振电路71内,振荡电路72和输出放大电路73根据从电压可调谐振电路71供给的输出信号以及从电源端子70供给的电源电压,生成作为输出的调制信号。
输出放大电路73的输出供给到阻抗匹配部11内,阻抗匹配部11的输出供给到焊锡凸点66上。如上所述,焊点66是形成在第2空腔62底面上的电极,若把构成功率放大器模块部5的次模块***,则与设置在该次模块上的外部端子(输入端子29)进行电连接。
构成合成器模块部6的电压控制振荡器34,其电路结构也与图3所示的电压控制振荡器33相同,其输出和电压控制振荡器33一样供给到阻抗匹配部11内。
这种电路结构的电压控制振荡器33和34的一部分,如图2(a)和(b)所示,由设置在主模块60内部的导体图形74构成,其余部分由安装在主模块60上面的电子元件75构成。这样一来,在主模块60中把合成器模块部6和阻抗匹配部9~14构成一个整体,同时能够***高频模块1的功能所需要的其他部分(前端模块部4等)。
这样,作为主模块60本身,只是合成器模块部6和阻抗匹配部9~14实现了一体化,所以,主模块60的合格率实质上等于合成器模块部6本身的合格率。
图4(a)是构成前端模块部4的次模块80从背面观看时的大体斜视图,图4(b)是其断面图。
如图4(a)和(b)所示,构成前端模块部4的次模块80的平面形状约为3.0mm×8.0mm的长方形,其厚度约为1.5mm。次模块80由许多块陶瓷基板重叠而成,基板内部形成了构成规定元件和布线的导体图形81以及穿通孔电极82,基板的上面安装了各种电子元件83。在该多层基板的上面设置了为屏蔽电磁波所需的金属帽盖84。
构成次模块80的陶瓷基板如图4(b)所示,由介电常数不同的2种陶瓷基板构成,介电常数高(例如εr=11)的陶瓷基板布置在上层部分和下层部分,其上形成的导体图形81主要构成电容器电极;介电常数低(例如εr=5)的陶瓷基板布置在中层部分,其上形成的导体图形81主要构成电感器电极。
并且,在次模块80的背面上,设置了许多外部电极85,用于构成天线端子22、GSM侧发送端子23、DCS侧发送端子24、GSM侧接收端子25和DCS侧接收端子26等。该平面布置对应于设置在第1空腔61底面上的焊点65的布置。所以,若把该次模块80***到第1空腔61内,则如上所述,可以实现这些外部电极85和焊点65的电连接。
而且,构成前端模块部4的次模块80与主模块60分开,单独设计、制造,在***到第1空腔61内之前,独立地进行检查。因此,次模块80的合格率实质上与主模块60的合格率没有关系。
图5(a)是构成功率放大器模块部5的次模块90从背面观看时的大体斜视图,图5(b)是其断面图。
如图5(a)和(b)所示,构成功率放大器模块部5的次模块90的平面形状约为11.0mm×8.0mm的长方形,其厚度约为1.5mm。次模块90,由许多块树脂基板重叠而成,其内部在多层基板上形成了构成规定元件和布线的导体图形91和穿通孔电极92;在多层基板内部埋入了半导体芯片(MMIC)93;在多层基板的上面安装了各种电子元件94。在该多层基板的最上面,设置了对电磁波进行屏蔽用的金属帽盖95,而且,作为构成次模块90的树脂基板,既可以采用与构成主模块60的树脂基板相同种类的树脂基板,也可以采用不同种类或不同介电常数的树脂基板。
并且,在次模块90的背面,设置了构成输入端子29、30和输出端子31、32等的许多外部电极96、以及用于对半导体芯片93进行散热的散热电极97。外部电极96的平面布置对应于设置在第2空腔62底面上的焊点66的布置。所以,若把该次模块90***到第2空腔62内,则如上所述,这些外部电极96和焊点66就能实现电连接。
而且,构成功率放大器模块部5的次模块90,和次模块80一样,与主模块60分开,单独设计、制造,在***到第2空腔62内之前单独进行检查,所以,次模块90的合格率实质上与主模块60和次模块80的合格率没有关系。
图6是构成LSI部7的半导体芯片封装品100从背面观看时的大体斜视图。
如图6所示,构成LSI部7的半导体芯片封装品100的平面形状约为5.0mm×4.0mm的长方形,其厚度约为0.5mm。半导体芯片封装品100是为了实现GSM侧低噪声放大器37、DCS侧低噪声放大器38,GSM侧混频器39和DCS侧混频器40的各功能,将其电路集成在一块半导体芯片上,用树脂封装而形成的。其背面上设置了阵列状的许多外部电极101,用于构成输入端子41、42、45、46和输出端子43、44、47、48等。这些外部电极101的平面布置对应于设置在第3空腔63底面上的焊点67的布置。所以,该半导体芯片封装品100若***到第3空腔63内,则如上所述,这些外部电极101和焊点67就能实现电连接。
而且,构成LSI部7的半导体芯片封装品100,与次模块80和90一样,与主模块60分开,单独设计、制造,在***到第2空腔62内之前单独检查,所以,半导体芯片封装成品100的合格率,实际上与主模块60和次模块80及90的合格率没有关系。而且,在本说明书中,半导体芯片封装品也称为“次模块”。也就是说,所谓“次模块”,其概念包括半导体芯片封装品在内。
图7(a)是构成SAW滤波器模块部8的次模块110从背面观看时的大体斜视图,图7(b)是其断面图。
如图7(a)和(b)所示,构成SAW滤波器模块8的次模块110的平面形状约为3.0mm×2.5mm的长方形,其厚度约为1.0mm。次模块110,由内部形成了导体图形111和穿通孔电极112的多层陶瓷基板,安装在多层陶瓷基板上的SAW滤波器20、21,以及封装用帽盖113构成。SAW滤波器20、21由密封用帽盖113进气密封。
并且,次模块110的背面上设置了多个外部电极115,用于构成输入端子52、53和输出端子54、55等。这些外部端子115的平面布置对应于设置在第4空腔64底面上的焊点68的布置。所以,若把该次模块110***到第4空腔64内,则如上所述,这些外部电极115和焊点68就实现电接触。
而且,构成SAW滤波器模块部8的次模块110,和次模块80、90和半导体芯片封装品100一样,与主模块60分开,单独设计、制造,在***到第4空腔64内之前单独检查,所以,次模块110的合格率,实质上与主模块60和次模块80、90以及半导体芯片封装品100的合格率没有关系。
涉及本实施例的高频模块1,是分别把次模块80、次模块90、半导体芯片封装品100和次模块110***到设置在主模块60上的第1~第4空腔61~64中,进行电连接后而制成的。在该***作业中,把分别设置在各次模块80、90和100的上部的金属帽盖84、95和113的表面、以及半导体芯片封装品100的表面卡住(固定),使其容易处理,并且,在将其***后,通过回流焊接工序,使第1~第4空腔61~64底面上的焊点65~68一旦熔化,这样,与对应的外部电极85、96、101和115进行电气和机械的连接。
图8表示高频模块1的形状,这是把次模块80、次模块90、半导体芯片封装品100和次模块110分别***到设置在主模块60上的第1~第4空腔61~64中而构成的,图中(a)是平面图,(b)是沿(a)所示的a~b线的断面图。
如图8所示,若把次模块80、次模块90、半导体芯片封装品100和次模块110分别***到第1~第4空腔61~64中进行电气和机械连接,则主模块60可以作为整体的大规模模块使用,其中具有图1所示的高频模块1的全部功能。
这样,采用本实施例的高频模块1是一种大规模的模块,其中具有:前置模块部4,功率放大器模块部5、合成器模块部6、LSI部7、SAW滤波器模块部8和阻抗匹配部9~14。另一方面,作为其主体的主模块60中,仅仅使这些电路的一部分即合成器模块部6和阻抗匹配部9~14进行一体化或装入内部,其他电路部分,即前端模块部4、功率放大器模块部5、LSI部7和SAW滤波器模块,作为次模块在事后***,所以,只能使用通过制造后的检查被认定为合格的产品。因此,能大幅度提高高频模块1整体的合格率。
再者,在采用本实施例的高频模块1中,分别构成前端模块部4、功率放大器模块部5、合成器模块部6、LSI部7和SAW滤波器模块部8的、次模块80、次模块90、主模块60、半导体芯片封装品100和次模块110、分别是单个的零件,所以即使在要求其中的一部分电路更改特性的情况下,仅重新设计构成相应电路的次模块即可,所以,能提高通用性。
而且,在采用本实施例的高频模块1中,前端模块部4、功率放大器模块部5、合成器模块部6、LSI部7和SAW滤波器模块部8,其互相连接的布线、以及设置在他们之间的阻抗匹配部9~14,与合成器模块部6一起安装在主模块60内,所以,不需要在母板上设置该布线,不需要设置阻抗匹配部。这样一来,与在母板上单独安装前端模块部4等的情况相比较,能大幅度减小安装面积。
再者,次模块80、90、半导体芯片封装品100和次模块110的外部电极85、96、101、115,均设置在其底面上,所以,可以把第1~第4空腔61~64的内径设定成与次模块80、90、半导体芯片封装品100和次模块110的外径大体相同,这样,能控制主模块60的平面尺寸。
以下说明本发明的其他良好实施例。
图9是涉及本发明其他良好实施例的高频模块120的形状图,(a)是平面图,(b)是沿(a)所示的e-f线的断面图。
涉及本实施例的高频模块120,在主模块60和各次模块80、90、110及半导体芯片封装品100的连接方法方面,不同于涉及上述实施例的高频模块1。
也就是说,在涉及本实施例的高频模块120中,如图9(b)所示,在主模块60与各次模块80、90、110和半导体芯片封装品100的连接部分,设置了各向异性导电片121,使两者的电气连接通过该各向异性导电片121来进行。
图10(a)是各向异性导电片121的概要平面图,图10(b)是图10(a)所示的g h断面的概要断面图。
如图10(a)和(b)所示,各向异性导电片121,其结构是在厚度约0.2mm的绝缘性薄膜122上设置了从一个面向另一个面穿通的多个穿通孔123。各穿通孔123的直径和相邻的穿通孔之间的间隔,其设定值远远小于次模块80、90、半导体芯片封装品100和次模块110的外部电极85、96、101和115的直径以及电极之间的间隔。并且,在各穿通孔123内填入了导电性材料124,利用从穿通孔123的一端向另一端连续填入的导电性材料124,使各向异性导电片121的一个面向另一个面形成导电性。对导电性材料124没有特别限制,但最好采用金。
另一方面,作为各向异性导电片121的主体的绝缘性薄膜122由绝缘性材料构成,所以,各向异性导电片121在平面方向上有绝缘性。也就是说,各向异性导电片121在其厚度方向上有导电性,在其平面方向上有绝缘性。
并且,如图9(b)所示,在本实施例中,在次模块90本身没有设置金属帽盖,在把次模块90***到第2空腔62内后,通过固定垫片126放置(按压)的金属板127具有帽盖的作用。也就是说,在把次模块90***到第2空腔62内后,在次模块90的上面部分上放置固定垫片126,然后用金属板127来关闭第2空腔62。这时,在主模块60的上面部分中,在与金属板127的端部相连接的部分形成接地图形,这样,使金属板127上出现接地电位。该结构对于其他次模块80、110也是一样。
在通过这种各向异性导电片121的连接中,利用金属板127通过固定垫片126来按压次模块80、90、110,在此状态下,金属板127的端部和设置在主模块60上面的接地图形利用焊接等方法进行固定。这样一来,主模块60和各次模块80、90、110通过各向异性导电片121进行压接,实现电连接。
若按照本实施例,则除上述实施例的效果外,因为主模块60、与次模块80、90、半导体芯片封装品100和次模块110通过各向异性导电片121进行连接,所以不需要在主模块60的第1~第4空腔61~64的底面上形成焊点65~68。并且,因为主模块60和次模块80、90、半导体芯片封装品100和次模块110没有焊接,所以在将其***到第1~第4空腔61~64内,用金属板127封闭后,当发现故障时,很容易对其进行更换。
再者,在本实施例中,利用金属板127来对第1~第4空腔61~64进行封闭,其中被***的次模块80、90、半导体芯片封装品100和次模块110大体上呈密封状态,所以,异物不易进入,这也是一个优点。
本发明并非仅限于上述实施例,而是不言而喻,在权利要求书中所述的各项发明的范围内,可以进行各种更改,这些更改也应当包括在本发明的范围内。
例如,在涉及上述实施例的高频模块1和120中,在主模块60内安装合成器模块部6,而把前置模块部4、功率放大器模块部5、LSI部7和SAW滤波器模块部8作为单个零件制成次模块或半导体芯片封装品。应当装入主模块60内的电路部分并非仅限于合成器模块部6,也可以装入其他电路部分。但是,主模块60的尺寸大于次模块和半导体芯片封装品,所以,为了减轻总体重量,最好采用树脂基板等轻质材料来制作主模块60,考虑到这一点,最好选择能安装到由树脂等构成的多层基板内的电路部分。
并且,在主模块60内也可以安装2个以上的电路部分,它们可以选自前置模块部4、功率放大器模块部5、合成器模块部6、LSI部7和SAW滤波器模块部8。如果把这2个以上的电路部分安装到主模块60内,那么,能使整体尺寸小型化,相反,合格率会下降,所以,内部安装的电路部分的数量,最好对要求的尺寸和合格率考虑后加以决定。
再者,在涉及上述实施例的高频模块1和120中,把阻抗匹配部9~14全部安装到构成主模块60内的多层基板内,但是,并不是必须把它们全部装入到多层基板内,而是也可以根据安装在主模块60上面的电子元件的情况,仅把阻抗匹配部的一部分安装在内部。
并且,在涉及上述实施例的高频模块1中,在第1~第4空腔61~64的底面上设置了焊点65~68,但也可以不在第1~第4空腔61~64侧设置焊点,而在被***的次模块和半导体芯片封装品侧设置焊点。
如上所述,本发明从结构上在构成高频模块的多个电路部分中,能把一部分电路部分安装在主模块内,把其他电路部分作为次模块或半导体芯片封装品***到主模块上的空腔内,所以能抑制包括多个电路部分的高频模块的合格率下降,同时能提高其通用性。
Claims (7)
1、一种高频模块,其特征在于包括:
主模块,包括:第一基板,在其正面上形成有空腔,在其背面上形成有用于与天线连接的天线端子;在上述空腔的底表面上形成的第一电极;和形成的连接上述第一电极和天线端子的阻抗匹配电路,该阻抗匹配电路包括第一基板内设置的导体图形,
次模块,包括:形成有高频电路的第二基板,和在该第二基板背面上形成的与上述高频电路连接的第二电极,
其中,上述次模块被***到上述主模块中的空腔内,上述第一和第二电极相互电连接。
2、如权利要求1所述的高频模块,其特征在于:构成上述主模块的第一基板由多块树脂基板的叠层体构成。
3、如权利要求1所述的高频模块,其特征在于:构成上述次模块的第二基板由多块陶瓷基板的叠层体构成。
4、如权利要求1所述的高频模块,其特征在于:上述主模块的第一基板和上述次模块的第二基板通过焊接而电连接。
5、如权利要求1所述的高频模块,其特征在于:上述主模块的第一基板和上述次模块的第二基板通过各向异性导电片而电连接。
6、如权利要求1所述的高频模块,其特征在于:***了上述次模块的上述空腔的上部由金属板覆盖。
7、如权利要求6所述的高频模块,其特征在于:上述金属板与形成在上述主模块上表面上的接地图形相连接。
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EP (1) | EP1381258A4 (zh) |
JP (1) | JP3612031B2 (zh) |
CN (1) | CN1224301C (zh) |
WO (1) | WO2002080634A1 (zh) |
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DE102006022580B4 (de) * | 2006-05-15 | 2014-10-09 | Epcos Ag | Elektrisches Bauelement |
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DE102007039618B4 (de) * | 2007-08-22 | 2021-06-02 | Vitesco Technologies GmbH | Modul für eine integrierte Steuerelektronik mit vereinfachtem Aufbau |
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US9172131B2 (en) * | 2013-03-15 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure having aperture antenna |
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-
2001
- 2001-03-29 JP JP2001097027A patent/JP3612031B2/ja not_active Expired - Lifetime
-
2002
- 2002-03-27 CN CNB028009339A patent/CN1224301C/zh not_active Expired - Lifetime
- 2002-03-27 US US10/473,019 patent/US6980066B2/en not_active Expired - Lifetime
- 2002-03-27 EP EP02713202A patent/EP1381258A4/en not_active Withdrawn
- 2002-03-27 WO PCT/JP2002/002961 patent/WO2002080634A1/ja not_active Application Discontinuation
Also Published As
Publication number | Publication date |
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JP2002299785A (ja) | 2002-10-11 |
EP1381258A1 (en) | 2004-01-14 |
US20040113719A1 (en) | 2004-06-17 |
EP1381258A4 (en) | 2007-11-21 |
JP3612031B2 (ja) | 2005-01-19 |
CN1460397A (zh) | 2003-12-03 |
WO2002080634A1 (en) | 2002-10-10 |
US6980066B2 (en) | 2005-12-27 |
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