CN1212536C - 电发光屏板 - Google Patents
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Abstract
一种能够改善画面质量的电发光屏板。在该屏板中,第一和第二开关响应通过栅极线提供的选通信号向电容器施加数据线上的信号。第一和第二开关的阈值电压设定成彼此不同。由此就可以避免反冲现象,并能最大限度地减小泄漏电流,从而改善了画面质量。
Description
本申请要求2001年6月22日申请的韩国专利申请第2001-35662号的权益,因而,为达到所有目的而将该申请在此如同其已在此处全文引述的那样作为参考文献加以结合。
技术领域
本发明涉及一种电发光显示器(ELD),更具体地说,是涉及一种能够改善画面质量的电发光屏板。
背景技术
近来,业界已经开发了各种能够消除那些与阴极射线管(CRT)有关的缺点,且重量轻和体积小的平板显示器装置。这类平板显示器装置通常包括:液晶显示器(LCD)、场发射显示器(FED)、等离子显示屏板(PDP)、和电发光(EL)屏板等。
为提高平板显示装置的显示质量和提供具有大型显示屏的平板显示器,现已积极地进行了大量的研究。这种显示装置中的EL屏板是自发射装置。EL屏板利用诸如电子和空穴等载流子激励荧光物质显示视频图象。EL屏板的优点在于,可以使用低直流电压驱动,且响应速度快。
正如图1所示,这种EL屏板包括:以彼此交叉方式设置的栅极线GL和数据线DL、以及在栅极线GL和数据线DL之间的交叉点上设置的象元108。当栅极线GL上起动一个选通信号时,驱动每个象元108,由此产生与数据线DL上的象素信号电流量相对应的光。
另外,EL屏板104包括:与数据线DL相连的电流驱动器106。每个电流驱动器106响应象素信号,控制电流从象元108经数据线DL流到自身内,由此向每个象元108施加了象素信号。电流驱动器106使电子充电电流流入象元108。随象素信号变化的电流信号借助于电流驱动器106流入象元108。
EL屏板104的栅极线GL与栅驱动器100相连,而电流驱动器106与数据驱动器102相连。栅驱动器100顺序地驱动栅极线GL。数据驱动器102向电流驱动器106施加一根线的象素电压信号。每个电流驱动器106将来自数据驱动器102的象素电压信号转换成反向象素电流信号,并将转换后的象素电流信号施加至象元108。换句话说,电流驱动器106可控制在从象元108通过数据线D的电流流路上的电流量,由此提高了象元108上的最大电流量和与灰度级对应的电流量的差别。结果,EL屏板104能够显示灰度画面。
参照图2,象元108包括:与第一低压线FVL相连的EL单元(ELC)和连在EL单元(ELC)与数据线DL之间的EL单元驱动电路110。第一低压线FVL能够与接地电压源GND相连,或能与产生负电压的第一低压源相连。在栅极线GL上起动控制信号的时段内,EL单元驱动电路110向EL单元(ELC)施加一正向电流信号,该信号随数据线DL上的反向电流量变化。为此,EL单元驱动电路110包括:在EL单元(ELC)、第一节点N1和电源电压线VDDL间连接成电流反射镜的第三和第四PMOS TFT Q3和Q4,以及与第二节点N2和电源电压线VDDL相连的电容器C,所述的第二节点N2与第三和第四PMOS TFT Q3和Q4的栅电极共连。
当电源电压线VDDL与数据线DL相连时,电容器C充入数据线DL上的信号电流,并向第三和第四PMOS TFT Q3和Q4的栅电极施加充入的信号电流。第三PMOS TFT Q3由电容器C中充入的信号电流启动,从而将电源电压线VDDL上的电源电压VDD施加至EL单元(ELC)。与此同时,第三PMOSTFT Q3根据电容器C中充入的信号电流量而改变其沟道宽度,从而可以控制从电源电压线VDDL耦合到EL单元(ELC)的电流量。然后,EL单元(ELC)发出与从电源电压线VDDL经第三PMOS TFT Q3施加的电流量相对应的光。第四PMOS TFT Q4也控制从电源电压线VDDL流到数据线DL上的电流,由此决定经第三PMOS TFT Q3流入EL单元(ELC)的电流量。
另外,EL单元驱动电路110还包括:第一和第二PMOS TFT Q1和Q2,它们共同响应栅极线GL上的选通信号。在从栅极线GL施加低逻辑选通信号的时段内使第一PMOS TFT Q1接通,于是将与第一节点N1相连的第一PMOSTFT Q1的源极与数据线DL相连。换句话说,第一PMOS TFT Q1扮演响应低逻辑选通信号形成从电源电压线VDDL经第四PMOS晶体管Q4、第一节点N1和其自身延伸到数据线DL的电流通路的角色。第二PMOS TFT Q2也在低逻辑选通信号由栅极线GL向其栅电极施加的时段内接通,由此通过第二节点N2和与电容器C的一个端子相连的第一节点N1将第三和第四PMOS TFT Q3和Q4的栅电极与数据线DL连接起来。换句话说,在栅极线GL上的选通信号保持在低逻辑态的时段内接通第一和第二PMOS TFT Q1和Q2,以将数据线DL与电源电压线VDDL以及第二节点N2相连,由此充入一个与数据线DL中流动的电流量相对应的电荷量(或信号电流)。
当选通信号从低逻辑态变为高逻辑态时,接通该EL单元驱动电路110的第一PMOS TFT Q1,同时接通具有相同阈值电压的第二PMOS TFT Q2。于是会产生反冲(kick-back)现象,即其中充入电容器C的电荷量会在选通信号的下降边缘处泄漏。结果,EL单元(ELC)不能精确地产生与数据线DL上的电流量相对应的光,于是引起了画面劣化或失真。
发明内容
于是,本发明涉及这样一种电发光屏板,其基本上能避免由于相关技术的局限和缺点导致的一个或多个问题。
本发明的优点是提供一种能够改善画面质量的电发光屏板。
将在下面的描述中阐述本发明的其他特征和优点,由这些描述会使其变得更明了,或者可通过实践本发明来学到这些特征和优点。通过书面描述和权利要求以及所附附图中具体指出的结构能够实现并得到本发明的目的和其他优点。
正如具体例举的和广义描述的那样,为了实现依照本发明目的的这些和其他优点,根据本发明一个实施例的电发光屏板包括:多条栅极线;多条与栅极线交叉的数据线;多个设置在栅极线与数据线之间交叉点上的电发光单元;多个用于从数据线充入信号的电容器;连接在电发光单元和电容器之间的第三开关;与第三开关相连形成电流反射镜的第四开关;以及用于响应通过栅极线提供的选通信号而向电容器施加数据线上的信号的第一和第二开关,所述第一开关的阈值电压设定成低于第二开关的阈值电压。在电发光屏板中,第一开关具有与栅极线相连的栅极端子、与数据线相连的源极端子和与第二开关的源极端子相连的漏极端子。
第二开关具有与栅极线相连的栅极端子、与第一开关的漏极端子相连的源极端子和与电容器相连的漏极端子。
第一开关的阈值电压和第二开关的阈值电压之间的差值约大于0.5V。
在电发光屏板中,第三开关用于响应电容器中充入的信号电流向电发光单元施加数据线上的信号;以及第四开关用于控制施加给每个电发光单元的电流。第一到第四开关中的每一个都包括沟道极性相同的薄膜晶体管。
第一和第二开关包括沟道极性彼此不同的薄膜晶体管,而第三和第四开关包括沟道极性相同的薄膜晶体管。
第二开关的栅极绝缘膜厚度大于第一开关的栅极绝缘膜厚度。
第二开关的保护层厚度要大于第一开关的保护层厚度。
第二开关的中间层绝缘膜厚度要大于第一开关中间层绝缘膜的厚度。
第二开关的栅电极具有单层结构,而第一开关的栅电极具有多层结构。
第二开关的源极和漏极具有单层结构,而第一开关的源极和漏极具有多层结构。
第二开关的源极和漏极由与第一开关的材料不同的材料制成。
第二开关的半导体层由与第一开关的半导体层材料不同的材料制成。
注入第二开关半导体层的离子浓度设定成高于注入第一开关半导体层的离子浓度。
第二开关的半导体层包括氢杂质。
第二开关的半导体层经受利用等离子体进行的表面处理。
第一开关下基板的结晶方向与第二开关的结晶方向不同。
第二开关的栅电极是由与第一开关栅电极材料不同的材料制成的。
需要理解的是,前面的一般性描述和下面的详细描述都是示范性和说明性的,意欲提供对所要求保护的本发明作进一步的说明。
附图的简要说明
将用以提供对本发明进一步理解的附图结合进来构成本说明书的一部分,这些附图用于说明本发明的实施例,并连同说明一起用于解释本发明的原理。
在附图中:
图1是表示传统电发光屏板结构的示意性方框图;
图2是图1所示象元的详尽电路图;
图3是依照本发明实施例的电发光屏板的象元的详尽电路图;
图4是表示图1所示象元的另一开关示例的详尽电路图;
图5是图3所示第一和第二开关的缓冲绝缘层截面图;
图6是图5所示缓冲绝缘层的详尽视图;
图7是图3所示第一和第二开关的有源层截面图;
图8是图3所示第一和第二开关的栅电极和栅极线的截面图;
图9是表示图3所示第一和第二开关上离子注入过程的截面图;
图10是图3所示第一和第二开关的中间层绝缘膜的截面图;
图11是图3所示第一和第二开关的源极和漏极的截面图;
图12是图3所示第一和第二开关的保护层截面图;以及
图13是图3所示第一和第二开关的象素电极的截面图。
具体实施方式
现在将对本发明的实施例作详尽参引,这些实施例的例子示于附图中。
参照图3,其示出了依照本发明实施例的EL单元驱动电路。
EL单元驱动电路120包括:以在EL单元(ELC)、第一节点N1和电源电压线VDDL中形成电流反射镜的方式连接的第三和第四开关S3和S4;连接在第二节点N2和电源电压线VDDL之间的电容器C,所述的第二节点N2与第三和第四开关S3和S4的栅电极共连;与第一节点N1和栅极线GL相连的第二开关S2;连接在第一节点N1和数据线DL之间的第一开关S1。在此,第一到第四开关中的每一个都由PMOS型TFT制成。
当电源电压线VDDL与数据线DL相连时,将数据线DL上的信号电流充入电容器C,并将所充入的信号电流共同送入第三和第四开关S3和S4的栅电极。通过电容器C中充入的信号电流接通第三开关S3,由此将电源电压线VDDL上的电源电压VDD施加到EL单元(ELC)。与此同时,第三开关S3根据电容器C中充入的信号电流量而改变其沟道宽度,从而可以控制由电源电压线VDDL耦合到EL单元(ELC)的电流量。然后,EL单元(ELC)发出与由电源电压线VDDL经第三开关S3施加的电流量相对应的光。第四开关S4也控制从电源电压线VDDL流入数据线DL的电流,由此确定经第三开关S3流入EL单元(ELC)的电流量。
在从栅极线GL施加低逻辑选通信号的时段内接通第一开关S1,从而将与第一节点N1相连的第一开关S1的源极连接到数据线DL上。换句话说,第一开关S1扮演着响应低逻辑选通信号形成从电源电压线VDDL经第四开关S4、第一节点N1和自身延伸到数据线DL的电流流路的角色。在将来自栅极线GL的低逻辑选通信号送入其栅电极的时段内还接通第二开关S2,由此通过第二节点N2和与电容器C的一个端子连接的第一节点N1将第三和第四开关S3和S4的栅电极与数据线DL相接。换句话说,在栅极线GL上的选通信号保持低逻辑状态的时段内接通第一和第二开关S1和S2,以便将数据线DL与电源电压VDDL以及第二节点N2相连,从而向电容器C充入与数据线DL中流动的电流量相对应的电荷量(或信号电流)。
该单元驱动电路120有差别地设定第一和第二开关S1和S2的阈值电压V第一和V第二。也就是说,可通过下面将要提到的制造方法将第一开关S1的阈值电压V第一设定成低于第二开关S2的阈值电压V第二。最理想的条件是将第二开关S2的阈值电压V第二与第一开关S1的阈值电压V第一之间的差值(V第二-V第 一)设定为约0.5V以上。当选通信号从低逻辑态变到高逻辑态时,第一开关S1会在第二开关S2之后断开。于是,电容器C中充入的电荷量就不会在选通信号的下降边缘泄漏。其结果是,EL单元(ELC)能够准确地发出与数据线DL上的电流量相对应的光,从而显示出与EL屏板的视频信号(或图像信号)相对应的画面,而没有任何劣化或失真。
参照图4,依照本发明另一个实施例的EL单元驱动电路120包括:以在EL单元(ELC)、第一节点N1和接地电压GND中形成电流反射镜(current mirror)的方式连接的第三和第四开关S3和S4;连接在第二节点和电源电压线VDDL之间的电容器C,所述的第二节点与第三和第四开关S3和S4的栅电极共连;与第一节点N1和栅极线GL相连的第二开关S2;以及连接在第一节点N1和数据线DL之间的第一开关S1。在此,第一到第四开关S1到S4中的每一个都由NMOS型TFT制成。
当接地电压GND与数据线DL相连时,将数据线DL上的信号电流充入电容器C,并将所充入的信号电流共同施加到第三和第四开关S3和S4的栅电极。通过电容器C中充入的信号电流接通第三开关S3,由此向EL单元(ELC)施加接地电压GND。与此同时,第三开关S3根据电容器C中充入的信号电流量而改变其沟道宽度,从而控制从接地电压GND耦合到EL单元(ELC)的电流量。然后,EL单元(ELC)产生与从接地电压GND经开关S3施加的电流量相应的光。第四开关S4也控制从电源电压线VDDL流入数据线DL的电流,从而确定经第三开关S3流入EL单元(ELC)的电流量。
在从栅极线GL施加高逻辑选通信号的时段内接通第一开关S1,由此将与第一节点N1相连的第一开关S1的源极与数据线DL相连。也就是说,第一开关S1扮演着响应低逻辑选通信号形成从电源电压线VDDL经第四开关S4、第一节点N1和自身延伸到数据线DL的电流通路的角色。在将来自栅极线GL的高逻辑选通信号施加到其栅电极的时段内还接通第二开关S2,从而通过第二节点和与电容器C的一个端子相连的第一节点N1将第三和第四开关S3和S4的栅电极与数据线DL相连。也就是说,在栅极线GL上的选通信号保持在高逻辑态的时段内接通第一和第二开关S1和S2,以将数据线DL与接地电压线GND以及第二节点N2相连,由此在电容器C中充入了与数据线DL中流动的电流量相对应的电荷量(或信号电流)。
该单元驱动电路120有差别地设定第一和第二开关S1和S2的阈值电压V第一和V第二。换句话说,通过下面将要提到的制造方法将第一开关S1的阈值电压V第一设定成低于第二开关S2的阈值电压V第二。最理想的状态是将第二开关S2的阈值电压V第二与第一开关S1的阈值电压V第一之间的差值大设定成约0.5V以上。当选通信号从低逻辑态变到高逻辑态时,第一开关S1后于第二开关S2断开。由此,电容器C中充入的电荷量不会在选通信号的下降边缘处泄漏。结果,EL单元(ELC)能够精确地产生与数据线DL上的电流量相对应的光,从而能显示出与EL屏板的视频信号(或图像信号)相对应的画面,而不会存在任何劣化或失真。
如图3和4所示,在依照本发明的EL屏板中,第一到第四开关S1到S4分别由沟道极性相同的TFT制成。另一方面,第一和第二开关S1和S2可用沟道极性(polarity channel)彼此不同的薄膜晶体管替代。在该情况下,第三和第四开关S3和S4都由沟道极性相同的薄膜晶体管制成。实际上,如果第一开关S1是PMOS型TFT,则第二开关S2就可变成NMOS型TFT。另外,所有的第三和第四开关S3和S4都可变成PMOS型或NMOS型TFT。
图5-13是表示具有不同阈值电压的第一和第二开关的制造过程的示意图。
参照图5,在基板31上形成第一和第二开关S1和S2的第一和第二缓冲绝缘膜32和62。第一和第二缓冲绝缘薄膜32和62可通过将诸如氧化硅(SiO2)的绝缘材料沉积到基板31上来形成。
接着,在第一和第二缓冲绝缘膜32和62上形成非晶硅薄膜。可通过连续横向固化(SLS)技术来结晶非晶硅薄膜。由此,提供了硅晶粒显著生长的第一和第二连续横向固化(SLS)硅薄膜34A和64A。在第一缓冲绝缘薄膜32上设置的第一SLS硅薄膜34A沿水平方向生成,而第二缓冲绝缘膜62上设置的第二SLS硅薄膜沿纵向生成。
如图6所示,在第一SLS硅薄膜34A上沿水平方向设置的源极和漏极此后具有沿与第一SLS硅薄膜34A的方向相同的方向结晶的状态。由此提高了电子迁移率,从而提高了接通电流(on-current)。由于接通电流的增大,第一开关S1的阈值电压V第一相对较低。另一方面,在第二SLS硅薄膜64A上沿纵向设置的源极和漏极沿垂直于第二SLS硅薄膜64A的方向结晶,从而降低了电子的迁移率,减小了接通电流。由于接通电流的减小,第二开关S2的阈值电压V第二相对较高。
参照图7,在第一和第二缓冲层32和62上形成第一和第二有源层34和64。第一和第二有源层34和64是通过为第一和第二硅薄膜34A和64A形成图案来形成的。
用于形成第一和第二有源层34和64的多晶硅有四个电子,其任何一个都具有不能与周围的原子键合的悬空键。为了减少这种悬空键,对第一有源层34进行加氢处理。由于该加氢处理,就能减少第一有源层34的悬空键,从而能增大与周围原子的键合力。由此增强了电特性,从而可将第一开关S1的阈值电压V第一设定得相对低于第二开关S2的第二阈值电压第二。
可供选择的另一方案是,第二有源层64和第一有源层34可由成分不同的非晶硅制成。制造第二有源层64的非晶硅中包含的缺陷数量要大于第一有源层34中包含的缺陷数量。由此将第二开关S2的阈值电压V第二设定成相对高于第一开关S1的阈值电压V第一。
另外,对第一有源层34的表面进行等离子处理,从而形成表面相对粗糙的第一有源层34。于是,表面粗糙的第一有源层34内的电子结构变得不同,由此可将第一开关S1的阈值电压V第一设定成相对低于第二开关S2的阈值电压V第二。
参照图8,在第一和第二缓冲绝缘膜32和62的上部设置第一和第二栅极绝缘膜36和66以及第一和第二栅电极38和68。
第一和第二栅极绝缘膜36和66以及第一和第二栅电极38和68都是通过顺序地将绝缘材料和金属层沉积到第一和第二缓冲绝缘膜32和62上、然后使其形成图案来形成的。第二栅极绝缘膜66的厚度G2设定成大于第一栅极绝缘膜36的厚度G1。换句话说,第二栅极绝缘膜66中所含的缺陷数量变得大于第一栅极绝缘膜36中包含的缺陷数量。于是,与第二栅极绝缘膜66对应的栅极电压增大,由此将第二开关S2的阈值电压V第二设定成相对高于第一开关S1的阈值电压V第一。
可供选择的另一方案是,第一栅电极38具有多层结构,而第二栅电极68具有单层结构。第一栅电极38由第一和第二金属层38a和38b构成,而第二栅电极68由第一和第二金属层38a和38b中的任一金属层构成。具有多层结构的第一栅电极38的导电性要高于具有单层结构的第二栅电极68的导电性。换句话说,第二栅电极68的电压增大,由此将第二开关S2的阈值电压V第二设定成相对高于第一开关S1的阈值电压V第一。
另外,第一栅电极38和第二栅电极68可由不同的金属材料制成。由于第一和第二开关S1和S2的频带特性因金属类型而变得不同,因此第二开关S2的阈值电压V第二也变得不同于与第一开关S1的阈值电压V第一。
参照图9,在第一缓冲绝缘层32上设置第一源极区和漏极区34S和34D,而在第二缓冲绝缘层62上设置第二源极区和漏极区64S和64D。
第一源极区和第二源极区34S和34D是通过将n+离子注入到所暴露的第一有源层34的每个侧面中并向其照射激光以激活缺陷来形成的。第二源极区和漏极区64S和64D是通过将n+离子注入到所暴露的第二有源层64的每个侧面中并向其照射激光以激活缺陷来形成的。
如果注入到第二有源层64的离子浓度高于注入到第一有源层34的离子浓度,则第一开关S1的阈值电压V第一就设定成相对低于第二开关S2的阈值电压V第二。
参照图10,在基板31上设置了第一和第二中间层绝缘膜40和70。
第一中间层绝缘膜40是通过在基板31上以覆盖第一栅电极38和第一有源层34的方式沉积绝缘材料来形成的。第二中间层绝缘膜70是通过在基板31上以覆盖第二栅电极68和第二有源层64的方式沉积绝缘材料形成的。
第二中间层绝缘膜70的厚度I2设定成大于第一中间层绝缘膜40的厚度I1。第二中间层绝缘膜70内所含的缺陷数量变得大于第一中间层绝缘膜40内所含的缺陷数量。由此,与第二中间层绝缘膜70相对应的第二开关S2的栅电压增大,于是使第二开关S2的阈值电压V第二设定成相对高于第一开关S1的阈值电压V第一。
在第一和第二中间层绝缘膜40和70内都限定了第一和第二接触孔42a、42b、72a和72b。第一接触孔42a、42b由源极接触孔42a和漏极接触孔42b构成,在源极接触孔中暴露用作源极区的缺陷区,而在漏极接触孔中暴露用作漏极区的缺陷区。第二接触孔72a和72b由源极接触孔72a和漏极接触孔72b构成,在源极接触孔中暴露用作源极区的缺陷区,而在漏极接触孔中暴露用作漏极区的缺陷区。
参照图11,在第一中间层绝缘膜40上设置了第一源极和漏极44和46,而在第二中间层绝缘膜70上设置了第二源极和漏极74和76。
第一源极和漏极44和46是通过在第一中间层绝缘膜40上沉积金属层然后使其形成图案来形成的,而第二源极和漏极74和76是通过将金属层沉积到第二中间层绝缘膜70上然后使其形成图案来形成的。分别通过第一接触孔42a和42b使第一源极和漏极44和46与第一有源层34的源极和漏极34S和34D电连接。分别通过第二接触孔72a和72b使第二源极和漏极74和76与第二有源层64的源极和连接64S和64D电连接。
第二源极和连接74和76中的每一个都具有单层结构,而第一源极和漏极44和46中的每一个都是多层结构。具有多层结构的第一源极和漏极44和46是由第一和第二金属层45a和45b形成的。第二源和漏极74和76是由第一和第二金属层45a和45b中的任一个形成的。由此,第二源极和漏极74和76的导电性要分别相对低于第一源极和漏极44和46的导电性。换句话说,由于第二开关S2的栅极电压增大,所以使第二开关S2的阈值电压V第二设定成高于第一开关S1的阈值电压V第一。
参照图12,在第一和第二中间层绝缘膜40和70上分别设置了第一和第二保护层48和78。
第一保护层48是通过以覆盖第一源极和漏极44和46的方式沉积诸如氧化硅(SiO2)的绝缘材料来形成的。第二保护层78是通过以覆盖第二源极和漏极74和76的方式沉积诸如氧化硅(SiO2)的绝缘材料来形成的。
将第二保护层78的厚度P2设定成大于第一保护层48的厚度P1。换句话说,第二保护层78中所含的缺陷数量变得大于第一保护层48中的缺陷数量。由此,与第二保护层78相对应的第二开关S2的栅电压增大,从而使第二开关S2的阈值电压V第二设定成高于第一开关S1的阈值电压V第一。
在第一和第二保护层48和78内限定了第三和第四接触孔50和80。第三接触孔50穿过第一保护层48暴露出第一漏极46的表面。第四接触孔80穿过第二保护层78暴露出第二漏极76的表面。
参照图13,分别在第一和第二保护层48和78上设置了第一和第二透明电极52和82。
第一和第二透明电极52和82是通过将透明导电材料沉积到第一和第二保护层48和78上、然后使其形成图案来形成的。第一透明电极52通过第三接触孔50与第一漏极46电接触,而第二透明电极82通过第四接触孔80与第二漏极76电接触。
第一和第二透明电极52和82由氧化铟锡(ITO)、氧化铟锌(IZO)和氧化铟锡锌(ITZO)中的任何一种制成。
通过图5到图12中建议的各种方法中的任何一种制造的第一和第二开关S1和S2都具有彼此不同的阈值电压V第一和V第二以减少反冲现象。
正如上面所述,依照本发明,可将第一和第二开关的阈值电压设定成彼此不同。由此就可以避免反冲现象,并能最大限度地减少电流泄漏,从而改善了画面质量。
对本领域普通技术人员来说显而易见的是,在脱离本发明的精神和范围的情况下,可对本发明作出各种改进和变化。因此,本发明的保护范围包括所有落入所附权利要求和其等同物范围内的任何对本发明作出的改进和变化。
Claims (19)
1.一种电发光屏板,其包括:
多条栅极线(GL);
多条与栅极线(GL)交叉的数据线(DL);
多个设置在栅极线(GL)与数据线(DL)之间交叉点上的电发光单元(ELC);
多个用于充入来自数据线(DL)的信号的电容器(C);
连接在电发光单元(ELC)和电容器(C)之间的第三开关(S3);
与第三开关(S3)相连形成电流反射镜的第四开关(S4);以及
第一和第二开关(S1和S2),用于响应通过栅极线(GL)提供的选通信号将数据线(DL)上的信号施加给电容器(C),所述第一开关(S1)的阈值电压(Vth1)设定成低于第二开关(S2)的阈值电压(Vth2)。
2.根据权利要求1所述的电发光屏板,其中所述第一开关(S1)具有与栅极线(GL)相连的栅极端子(38)、与数据线(DL)相连的源极端子(44)、与第二开关(S2)的源极端子(74)相连的漏极端子(46)。
3.根据权利要求1所述的电发光屏板,其中所述第二开关(S2)具有与栅极线(GL)相连的栅极端子(68)、与第一开关(S1)的漏极端子(46)相连的源极端子(74)、以及与电容器(C)相连的漏极端子(76)。
4.根据权利要求1所述的电发光屏板,其中第一开关(S1)的阈值电压(Vth1)和第二开关(S2)的阈值电压(Vth2)之间的差值约大于0.5V。
5.根据权利要求1所述的电发光屏板,其中第三开关(S3)用于响应电容器(C)中充入的所述信号电流将数据线(DL)上的信号施加给电发光单元(ELC);以及第四开关(S4)用于控制施加给每个电发光单元(ELC)的电流。
6.根据权利要求1所述的电发光屏板,其中所述第一到第四开关(S1到S4)中的每一个都包括相同极性沟道的薄膜晶体管。
7.根据权利要求1所述的电发光屏板,其中所述第一和第二开关(S1和S2)包括极性沟道彼此不同的薄膜晶体管,所述第三和第四开关(S3和S4)包括极性沟道相同的薄膜晶体管。
8.根据权利要求1所述的电发光屏板,其中第二开关(S2)的栅极绝缘膜(66)厚度大于第一开关(S1)的栅极绝缘膜(36)厚度。
9.根据权利要求1所述的电发光屏板,其中第二开关(S2)的保护层(78)厚度大于第一开关(S1)的保护层(48)厚度。
10.根据权利要求1所述的电发光屏板,其中第二开关(S2)的中间层绝缘膜(40)厚度要大于第一开关(S1)的中间层绝缘膜(70)厚度。
11.根据权利要求1所述的电发光屏板,其中第二开关(S2)的栅电极(68)具有单层结构,而第一开关(S1)的栅电极(38)为多层结构。
12.根据权利要求1所述的电发光屏板,其中第二开关(S2)的源极(74)和漏极(76)为单层结构,而第一开关(S1)的源极(44)和漏极(46)为多层结构。
13.根据权利要求1所述的电发光屏板,其中第二开关(S2)的源极(74)和漏极(76)是由与第一开关(S1)材料不同的材料制成。
14.根据权利要求1所述的电发光屏板,其中第二开关(S2)的半导体层(64)是由与第一开关(S1)材料不同的材料制成。
15.根据权利要求1所述的电发光屏板,其中注入第二开关(S2)半导体层(64)的离子浓度设定成高于注入第一开关(S1)半导体层(34)的离子浓度。
16.根据权利要求1所述的电发光屏板,其中第二开关(S2)的半导体层(64)包括氢杂质。
17.根据权利要求1所述的电发光屏板,其中第二开关(S2)的半导体(64)经受利用等离子体的表面处理。
18.根据权利要求1所述的电发光屏板,其中第一开关(S1)下基板(31)的结晶方向与第二开关(S2)的结晶方向不同。
19.根据权利要求1所述的电发光屏板,其中第二开关(S2)的栅电极(68)是由与第一开关(S1)材料不同的材料制成。
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US10714018B2 (en) | 2017-05-17 | 2020-07-14 | Ignis Innovation Inc. | System and method for loading image correction data for displays |
US11025899B2 (en) | 2017-08-11 | 2021-06-01 | Ignis Innovation Inc. | Optical correction systems and methods for correcting non-uniformity of emissive display devices |
US10971078B2 (en) | 2018-02-12 | 2021-04-06 | Ignis Innovation Inc. | Pixel measurement through data line |
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KR100205259B1 (ko) * | 1996-03-04 | 1999-07-01 | 구자홍 | 액티브매트릭스 액정디스플레이의 구동회로 |
US6268842B1 (en) * | 1998-04-13 | 2001-07-31 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor circuit and semiconductor display device using the same |
GB9812742D0 (en) * | 1998-06-12 | 1998-08-12 | Philips Electronics Nv | Active matrix electroluminescent display devices |
JP2000174282A (ja) * | 1998-12-03 | 2000-06-23 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
TW518650B (en) * | 1999-04-15 | 2003-01-21 | Semiconductor Energy Lab | Electro-optical device and electronic equipment |
EP1130565A4 (en) * | 1999-07-14 | 2006-10-04 | Sony Corp | ATTACK CIRCUIT AND DISPLAY INCLUDING THE SAME, PIXEL CIRCUIT, AND ATTACK METHOD |
GB9923591D0 (en) * | 1999-10-07 | 1999-12-08 | Koninkl Philips Electronics Nv | Current source and display device using the same |
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2001
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2002
- 2002-06-19 US US10/173,674 patent/US6690115B2/en not_active Expired - Lifetime
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Publication number | Publication date |
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US6690115B2 (en) | 2004-02-10 |
KR100743103B1 (ko) | 2007-07-27 |
KR20030000047A (ko) | 2003-01-06 |
CN1395141A (zh) | 2003-02-05 |
US20020195967A1 (en) | 2002-12-26 |
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