CN1206328A - Method of forming interconnections on electronic modules - Google Patents
Method of forming interconnections on electronic modules Download PDFInfo
- Publication number
- CN1206328A CN1206328A CN98102528A CN98102528A CN1206328A CN 1206328 A CN1206328 A CN 1206328A CN 98102528 A CN98102528 A CN 98102528A CN 98102528 A CN98102528 A CN 98102528A CN 1206328 A CN1206328 A CN 1206328A
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- CN
- China
- Prior art keywords
- flange
- metal
- pad
- substrate
- tin
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.
Description
The present invention relates to a kind of interconnective method that on the printed wire board electronic module, forms.Interconnecting of the present invention comprises the upside-down method of hull-section construction that can use with printed substrate reliably.
Along with further developing of semi-conductor industry, circuit is designed to occupy the little space of trying one's best usually.Circuit space has the value of saving, and the miniaturization of circuit energy raising speed reduces noise simultaneously, and brings other some feature performance benefits.In conjunction with the needs of preserving circuit space, circuit interconnection should be designed to can reliably working under the desired procedure condition.
Path often and integrated circuit (IC) be utilized internal circuit and external interface so that integrated circuit to be provided, for example connection of the necessity between the printed wire board electronic module together.This interconnection can be finished with two kinds of methods.In first method, path is by finishing with the metal bond pad of lead frame wire-bonded.If necessary, the back side or the metallization of inoperative one side with semiconductor device make this device can be soldered on the radiator and dispel the heat that whole then device will be by moulding in a Plastic Package.In the assembling, extend to outside lead frame from Plastic Package inside and be soldered on the printed substrate (PWB).Yet terminal conjunction method is the main cause of signal stray inductance, and especially loop wire length is by strictly minimum the time.Such stray inductance has upset signal frequency.
The second method that is commonly called " upside-down method of hull-section construction " is to adopt traditional metal deposition process to make the metallization structure with suitable layering to the path pad, form metal rim (bump) thereon, then semiconductor device can by this flange directly and substrate engage.Upside-down method of hull-section construction or direct small pieces connection technology are used for increasing current densities.The upside-down mounting mounting technique relates to the upset die and also directly effective the or top surface of semiconductor device is connected to printed substrate.Because actual semiconductor die size is much smaller than typical semiconductor package, this has just saved the space of integrated circuit and substrate greatly.This method has been saved actual packaging cost, the space of integrated circuit and substrate.
Flip chip technology uses conduction flange such as tin-kupper solder or gold that the circuit on the silicon chip and the interconnection of the I/O between the suprabasil circuit of electronic module are provided.Basic connectivity scenario comprises die I/O (I/O) pad that is applied with flange, adds that one group of substrate solder-wettable pad of coupling is formed.By the passivation layer etch via, form these die I/O pads by the suitable material layer of mask evaporation to seal this path again.The deposit solder alloy forms the scolder flange on this pad then.Simultaneously, for example by refluxing, form substrate solder-wettable pad to be connected with flange on the integrated circuit.Utilize solder flux to remove the oxide of metal surface to improve firm metallurgical binding.Reflow step can be finished in vapour phase or infrared oven or by the thermal source of location.Because its simplicity is cheap, high density and reliability, it is desired using upside-down method of hull-section construction on printed substrate.
Yet traditional flip chip technology also comes with some shortcomings, and a bigger problem is that handle assembly directly is connected with printed substrate, can only provide very little chance for the relative motion of device and printed substrate.Traditional printed substrate is to make with substrate, and base material for example is glass fiber reinforced epoxy resin or polyurethane, and they have and constitute the very big thermal coefficient of expansion of silicon difference of most of semiconductor devices.Therefore when the circuit occurrence temperature changed, printed substrate was different with the flexible speed of semiconductor device.Owing to different coefficient of thermal expansions produces the result of stress, make and the pad breakage cause the inefficacy of electronic product.
Another problem relevant with traditional flip chip technology is the metallurgical incompatibility of semiconductor device and printed substrate, and semiconductor device typically is combined with the aluminium pad, and this pad relatively is easy to deposition, is applicable to melts combine.Yet aluminium pad and tin-kupper solder can not weld.Therefore, flip chip technology has guaranteed that at first the geometry of the pad of semiconductor device meets the needs of printed substrate; Secondly deposition one barrier metal on pad covers layer of copper again on barrier metal.Barrier metal protection aluminium device pad separates with copper.On the copper layer, form flange to interconnect with printed substrate.Traditional upside-down method of hull-section construction forms this flange with tin-kupper solder, but adopts weld flange, must keep certain distance between the flange, in case the connection between the backflow welding flange, so limited I/O density or " spacing " of device.In order to satisfy the needs to the high density electronic building brick, golden flange is used to be connected on the brazing contact of printed substrate by thermocompression bonding and is connected with tin.Yet the costliness of price of gold makes the extensive use of this product be restricted.So this just needs a kind of reliable upside-down mounting flange to connect, it has looked after the problem that is run under the variations in temperature condition, both can provide highdensity good pitch interconnections, and price is suitable.
Therefore, the purpose of this invention is to provide a kind of semiconductor device and interconnective method of printed substrate of being suitable for.Another purpose provides a kind of semiconductor device and printed substrate of making and interconnects to solve and the do not match method of any problem of being brought of thermal coefficient of expansion.
A further object of the invention provides a kind of be used to make semiconductor device and the interconnective method of printed substrate, and not only price is suitable, and occupies very little space, does not need to use wire-bonded.
Above and other advantage is verified in the present invention, the invention describes interconnective method between a kind of formation printed substrate and the integrated circuit, also comprised a kind of method that on integrated circuit, forms the metalized vias pad that upside-down mounting connects that is used for.
Fig. 1 has described and has utilized the interconnective upside-down mounting flange connector that is used with acquisition and printed substrate substrate.
Fig. 2 has described the hierarchy of metalized vias pad.
Fig. 3 has described printed substrate substrate and the interconnective formation of upside-down mounting flange connector eutectic phase.
Fig. 4 has described has a plurality of upside-down mounting flange connectors and and the perspective view of the interconnective integrated circuit of printed substrate substrate.
The purpose of this invention is to provide materials and methods forming inexpensive flip-chip interconnection, and this Plant connection for be connected connection with the printed wire board electronic module, for example be used for and automobile electronic module Connection be solid.
New feature of the present invention comprises: metallization (2) flange of (1) path pad and substrate weldering The metallurgy of coating on the contact, and in conjunction with the technology and the principle that form. According to the present invention, logical The metallization of road pad and flange metal system can separately be used or are used in combination, and change sentence Talk about, the metallization of said path pad here can be used with other flange metal systems, Similarly, said flange metal system also can make with other path pad metallization here With.
As shown in Figure 1, the metallization of the path pad 12 on integrated circuit silicon chip 10 comprises a diffusion impervious layer 14, is preferably the titanium-tungsten of sputter, is positioned on the initial metal layer, and preferably having thickness is 8-12KA
0, cooperate this initial metal layer that contacts storing to be preferably the composition of aluminium or aluminium and other metals with silicon chip 10, as Al/2%Cu or Al/1%Si/0.5%Cu, preferably having thickness is 10-20KA
0Titanium-the tungsten layer and the following aluminium lamination that are used as diffusion impervious layer are bonding fine.Cover one deck antioxidation coating on titanium-tungsten layer again, preferably thickness is 10KA
0 Sputter copper layer 16; This layer provides anti-oxidation for titanium-tungsten layer in follow-up electroplating process, and the bonding to " double-screw bolt (stud) " is provided.
Next step relates to the application of major metal layer, and this metal layer is to electroplate on the copper layer 16 of sputter and for flange 20 provides main metalation, preferably copper, silver or nickel double-screw bolt, and its preferred thickness is 25-45 μ m.The result has formed the metallization of path pad 12 and built up upside-down mounting flange connector 20 on it.
As shown in Figures 2 and 3, flip-chip interconnection method of the present invention relates to uses use second metal on first metal and the substrate pad 22 to flange 20, lead track on substrate pad 22 interconnected printed circuit boards 26, and form an eutectic phase by interface region 28 and form between first metal and second metal effectively metallurgical binding.Flange 20 forms technology by first metal by the good flange of determining such as electroplating technology obtains.On the pad 22 of the lead track in the interconnected printed circuit board substrate 26, second metal is employed as coating 24, also is to utilize the good method of determining to finish as electroplating.
In a preferred embodiment, the first metal zinc, the second metal tin.Also in this embodiment, when flange 20 was made of zinc, it highly was preferably between the 25-75 μ m according to concrete application.On zinc flange 20, before forming, interconnection preferably applies a Gold plated Layer by plating for anti-oxidation, and its preferred thickness is 5-20 μ in or 0.13-0.51 μ m.In the preferred embodiment, coating 24 on the substrate pad 22 in the printed substrate substrate 26 is made up of the tin layer, Wu Zexi preferably, its preferred thickness is 300-400 μ in (being 7.62-10.16 μ m), is placed on the copper substrate pad 22 of interconnecting conductor track 31.Between copper layer and tin layer, use one arbitrarily nickel dam prevent that as the barrier layer copper from passing through the diffusion of tin layer, its preferred thickness is 90-300 μ in (being 2.29-7.62 μ m), the employing of nickel dam can be decided according to the operating condition of module.One additional random layer, antioxidation coating, a best flash gold plating, having preferred thickness is 5-20 μ in (being 0.13-0.51 μ m), can be used to prevent the oxidation of before interconnection forms nickel and/or tin layer.
For the formation of interconnection between flange 20 and the pad 22, coating 24 contacts on flange 20 and the pad 22 are connected to form directly.In a preferred embodiment, will provide an energy to make the temperature of contact-making surface rise to 240-290 ℃.Preferred heating means of the present invention are to reflux or the method for hot pressing, and keeping 5-15 second in the hot-press method under the 0-250g pressure is crucial technological parameter.
When temperature rises to preferable range 240-290 ℃, this scope is on the fusing point of second metallic tin, under the fusing point of second metallic zinc.The fusing point of second metallic tin is 232 ℃, and forms eutectic phase 26 between tin and zinc, when eutectic temperature is 199 ℃.Eutectic phase 26 can provide stronger connection between flange and substrate.The fusing point of zinc and tin-zinc eutectic makes to interconnect and is suitable for automobile and other electronic application.
In this process, the gold on the zinc flange bottom surface only accounts for very little ratio, can be dissolved in the eutectic phase, can keep and continue as flange at the gold of zinc flange both sides and be provided at the corrosion-resisting function of module in using.
The thermal conductivity of zinc is 116W/ (mk), and resistance is 5.9 * 10
-8Ohm, these character have satisfied the functional requirement of the flange that is used for electronics connection and thermal losses.
Compare with interchangeable golden flange, zinc upside-down mounting flange connector of the present invention has also been saved sizable expense when equal Performance And Reliability is provided.For example, on March nineteen ninety-five U.S.'s metal market, price of gold is 381.40 dollars every ounce, and the zinc valency is 0.47 dollar every pound, and price difference is greater than 11800 times.
In another specific embodiment, zinc is used as first metal and indium is used as second metal, and the fusing point of zinc and indium is respectively 420 ℃ and 157 ℃, and indium/zinc eutectic temperature is 144 ℃.According to process described above, preferred technological temperature should be in 170-190 ℃ of scope, and other technology is identical with the first embodiment of the present invention with dimensional parameters.
In the third embodiment of the present invention, tin is used as first metal, and indium is used as second metal.The fusing point of indium and tin is respectively 157 ℃ and 232 ℃, and indium/tin eutectic temperature is 120 ℃.In the preferred embodiment, technological temperature is in 170-190 ℃ of scope, and other technology is identical with first embodiment with dimensional parameters.It should be noted that the tin thermal conductivity is 66.6W/ (mk), resistance is 11.5 * 10
-8Ohm.Therefore, the 3rd embodiment also is suitable for the application expected.
In the 4th embodiment, bismuth can be used as first metal, and tin is used as second metal, and the fusing point of bismuth and tin is respectively 271 ℃ and 232 ℃, and the temperature of bismuth/tin eutectic is 139 ℃.In the preferred embodiment, suitable technological temperature should be in 245-265 ℃ of scope.Technology and dimensional parameters that the first concrete scheme provides also are applicable to the 4th embodiment, and the thermal conductivity of bismuth is 7.87W/ (mk), and resistance is 107 * 10
-8Ohm.
In the practical application, the method that the flange interconnections that is provided among the present invention forms is very useful, because this method does not promptly relate to poisonous component, there be not the problem relevant in the technical process with environmental protection yet, and because interconnective formation does not need solder flux, in the technical process then of the present invention is fluxless, and this is quite favourable, because of the residual liquid of solder flux is harmful and mordant to the performance of circuit.
In order further to strengthen the reliability of flange interconnections, the upside-down mounting that the epoxy resin underfilling can be used on the electronic module connects.Like this, in the use of electronic module, greatly reduce the mechanical load on the upside-down mounting flange connector, this just makes that it is very reliable interconnecting in the useful life of product.This underfilling also can provide additional corrosion-resisting function for flange.
This method is specially adapted to use relevant use with automobile, the consumer goods, military affairs and other electronic building brick.
The front has been described in detail and has been realized various embodiment of the present invention and best mode, and the those of skill in the art in the technical field that the present invention is correlated with can understand by defined various design of the present invention and the scheme put into practice of following claim.
Claims (2)
1, a kind ofly between printed substrate and integrated circuit, form interconnective method, comprising:
On integrated circuit, form a path pad;
On said path pad, form a upside-down mounting flange connector with first metal;
A substrate pad is provided on printed substrate;
On said substrate pad, apply the coating of one second metal; And
Between said first metal and second metal, form combination with interconnected printed circuit board and integrated circuit.
2, the process of claim 1 wherein that said first metal is that zinc, second metal are tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98102528A CN1206328A (en) | 1997-06-23 | 1998-06-23 | Method of forming interconnections on electronic modules |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/880955 | 1997-06-23 | ||
| CN98102528A CN1206328A (en) | 1997-06-23 | 1998-06-23 | Method of forming interconnections on electronic modules |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1206328A true CN1206328A (en) | 1999-01-27 |
Family
ID=5217395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98102528A Pending CN1206328A (en) | 1997-06-23 | 1998-06-23 | Method of forming interconnections on electronic modules |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1206328A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295989A (en) * | 2012-02-29 | 2013-09-11 | 联发科技股份有限公司 | Flip chip package |
| CN103531559A (en) * | 2013-10-18 | 2014-01-22 | 上海纪元微科电子有限公司 | Flip chip bonding structure and forming method thereof |
| US9437534B2 (en) | 2012-02-29 | 2016-09-06 | Mediatek Inc. | Enhanced flip chip structure using copper column interconnect |
| CN107257736A (en) * | 2015-03-04 | 2017-10-17 | 精工爱普生株式会社 | MEMS device, record head and liquid injection apparatus |
-
1998
- 1998-06-23 CN CN98102528A patent/CN1206328A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295989A (en) * | 2012-02-29 | 2013-09-11 | 联发科技股份有限公司 | Flip chip package |
| CN103295989B (en) * | 2012-02-29 | 2016-08-03 | 联发科技股份有限公司 | Flip-Chip Using |
| US9437534B2 (en) | 2012-02-29 | 2016-09-06 | Mediatek Inc. | Enhanced flip chip structure using copper column interconnect |
| CN103531559A (en) * | 2013-10-18 | 2014-01-22 | 上海纪元微科电子有限公司 | Flip chip bonding structure and forming method thereof |
| CN107257736A (en) * | 2015-03-04 | 2017-10-17 | 精工爱普生株式会社 | MEMS device, record head and liquid injection apparatus |
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