CN1205815A - System related to transmission buffer - Google Patents

Abstract

The present invention relates to a system for checking and adjusting a transmission buffer (1), wherein a bit stream (11) incoming to the transmission buffer (1) has a first transmission frequency (f1) or bit rate, and wherein a bit stream outgoing fromthe transmission buffer (1) has a second transmission frequency (f2) or bit rate. A write-related pointer (15) is given a value which corresponds to a bit position into which a writing unit (13) writes from the incoming bit stream into the transmission buffer (1), and a read-related pointer (16) is given a value which corresponds to a bit position from which a reading unit (14) reads from the transmission buffer (1) into the outgoing bit stream. A checking and adjusting means includes a proportional part (2), and integrating part (3) and an adjusting part (5) and functions to check and adjust the bit distance between the writing unit (13) and the reading unit (14). The proportional part (2) operates at a first clock frequency and the integrating part (3) operates at a second clock frequency, wherein the second clock frequency is allocated a lower value than the first clock frequency.

Description

System about transmit buffer

Invention field

The present invention relates to one and checks and adjust the system that has the transmit buffer of digital information load signal in the transmission system, the bit stream that wherein enters this transmit buffer has first transmission frequency or bit rate, and the bit stream that comes out from this transmit buffer has second transmission frequency or bit rate.

Adjust transmit buffer and arrive buffering area so that can write every information distributing to incoming bit stream by a r/w cell, after this, same information can be read the unit by one and read and distribute to output bit flow.

Give write pointer a numerical value, the bit position of the transmit buffer that this value writes corresponding to r/w cell gives read pointer a numerical value, and this value is corresponding to the bit position of the transmit buffer of reading to read the unit.

First transmission frequency or bit rate can be different with second transmission frequency or bit rate, therefore check and method of adjustment for one, comprising a proportional parts, an integral part and an adjustment member, be modified to check the bit distance between write pointer and read pointer, and in case of necessity, adjust bit distance between read-write cell.

Proportional parts is relatively given write pointer value with first limiting value and is given poor between the read pointer value, and integral part is with tolerance value and a desired value addition of above-mentioned difference, and the summation that obtains can be compared with second limiting value.

Adjust by adjustment member between read-write cell apart from the time, these results one of relatively are useful.

Proportional parts and integral part are with specific clock frequency work.

Background technology is described

Using transmit buffering when being transformed into the another kind of transmission system of using another kind of host-host protocol from a kind of transmission system of using certain host-host protocol has been well-known for a long time.

Different transmission systems has been stipulated the different frequency tolerance limit in the transmission bit stream, and these different transmission systems also comprise the mechanism of handling these frequency tolerances.This bit rate that is to say first transmission system can be different with the bit rate of second transmission system.

We also know, even information is determined with one and stable bit rate transmission, when received signal and transmitted one section very long apart from the time because various distortions, bit rate has slight variation.Two different transmission systems can be different transmission rate work, and first transmission rate or bit rate slight variation can be arranged in time, these true making use transmit buffer to necessitate, to guarantee that second transmission system obtains determining and stable bit rate.

Information in first transmission system writes transmit buffer by a r/w cell, and reads the unit by one and read from same buffering area, to form the normal data frame of second transmission system.

Use two pointers, the buffer location that one of them expression information writes, one is the position that information is read, and check or measure distance between these positions, read and/or the speed of r/w cell so that can adjust, otherwise prevent from by this to read the unit covered r/w cell or, and the information that prevents is for example destroyed, r/w cell has write the too much information that has little time to read.(the read-write pointer has overlapped), this also is well-known.

We also expect to prevent to be present in first transmission system, and the High-frequency Interference of bit rate (shake), and low-frequency disturbance (drift) are imported second transmission system into.

The term shake is meant that the time migration between bit position and their nominal position changes the drift that surpasses 10Hz, and drift is meant that the tolerance variations of the time between bit position and their nominal position is lower than the tolerance limit of 10Hz.

Herein, used a kind of speed regulating method as everyone knows, this method this paper is called the filling method of adjustment, that is to say, distribute the Frame in those second transmission systems to give the adjuster bit that is called here, this adjuster bit is high or low according to first bit rate bit rate more desired than first transmission system, determines these adjuster bits to be fillings or to put sky.

This first bit rate and the tolerance limit of expection between bit rate will cause that a pointer is close to another pointer, and under certain situation, pointer even can overlap and destruction information.

Herein, filling is that the bit distance between read-write cell can be adjusted, and avoids pointer to overlap simultaneously, and the most general method of compensate for jitter and drift respectively.

In these areas, we also know the ratio adjustment that use is called here, and it participates in assesses continuously to the distance between the relevant read-write pointer in the transmit buffer, and when the distance between read-write cell drops to predetermined value, use to fill and adjust this distance.

This method of adjustment can be brought slight unbalanced filling, and this filling can then cause the shake in second transmission system.Therefore wish in time that balance is distributed filling as much as possible, to prevent the shake in second transmission system.

We also know, use so-called integration adjustment, that is to say, in transmit buffer, in one section preset time T, formed the mean value or the accumulated value of bit distance between relevant read-write pointer, and then passed through integration, we can obtain a numerical value with the range averaging value that this so forms, and it can compare with the distance of expection.This method is beneficial to and detects the trend that drift occurs, and according to the ratio adjustment, implements necessary filling before going beyond the limit of.

This adjustment provides more uniform filling, therefore can avoid the shake in second transmission system.

Usage ratio and integration adjustment also are well-known simultaneously.

The early stage system example that uses such inspection and adjust transmit buffer is at US-A-5,263,056, publication US-A-5,337,315, US-A-5,132,970, US-A-5,331,671 and WO-A1-9400935 in announce.

The mean value that obtains bit distance between two pointers needs a large amount of logical circuits, and with several mean value integrations/summation or add up mutually, needs the space successively, and use error is controlled, possible error correction and high-power input, the heat radiation that can bring device subsequently.

It also is well-known in the present technique field that different transmission systems has different host-host protocols.

A this host-host protocol, it is characterized in that the time location of bit position (shake and drift) is had high requirements, it allows to transmit mass data with high transfer rate, need not to use multiplexing and multichannel tap respectively when transmission and reception, and name is called SDH (synchronous digital system).

Need be in transmission and use the old host-host protocol of multiplexing and multichannel tap in receiving, can cause the tolerance limit in the time location of bigger bit position (shake and drift), this agreement is marked as PDH (plesiochronous digital system).

Therefore, from the PHD field to the conversion in SDH field, be not very important being present in that drift in the PHD field and shake pass in the SDH field.Therefore, realize that it is well-known that aforesaid transmit buffer and fill method are used in this conversion accurately.

Use in the node in a field and fill, to handle the frequency tolerance between different nodal clocks in the transmission system, this also is well-known.

Summary of the invention

Technical problem

When we consider aforesaid early stage viewpoint and technology, we can find out, angle from a system, it is intended to check and adjust a transmit buffer that this buffering area has following characteristics: incoming bit stream has first transmission frequency or bit rate and from the buffering area output bit flow second transmission frequency or bit rate is arranged; Wherein be contained in each bit that belongs to incoming bit stream and can write buffering area, also can read the unit and read and be contained in each bit that writes buffering area and distribute to output bit flow by one by a r/w cell; The corresponding read pointer of writing in buffering area bit position that will write with r/w cell He read to read the unit has been carried out assignment; First transmission frequency or bit rate are different with second transmission frequency or bit rate; Check and adjustment means and contains a proportional parts, an integral part and an adjustment member of checking and adjust bit distance between the read-write pointer; Proportional parts is relatively about the difference between the read-write pointer value and first limiting value; Integral part utilizes an adder or sum unit with aforesaid difference and a predetermined value addition; The summation that obtains and second limiting value compare; Beginning to adjust the result who uses one of them to compare in the aforesaid distance with adjustment member.System hereto when how realizing by simple relatively, energy-conservation, yet is again when circuit obtains an integral part efficiently, to have a technical problem.

Another technical problem is, implements one of fact that an integration adjusts recognizing to use than reaching the lower clock frequency of ratio adjustment, and will realize the possibility that this fact provides.

We it can also be seen that recognizing how to utilize known technology, when being increased in the shake that suppresses in the incoming bit stream and drift with a kind of simple and cost-effective method, also have technical problem.

Another technical problem is to recognize that integral part moves the possibility that realizes with the second clock frequency more much lower than the first clock frequency value to the permission proportional parts with the operation of first clock frequency.

Also having a technical problem is to recognize that integral part can be with the frequency operation required condition lower than the ratio part.

Another technical problem is a benefit of recognizing that the clock frequency of being determined by system when first clock frequency is provided when being constituted, and the possibility that is provided when the second clock changeable frequency.

Another technical problem that also will see is to recognize the possibility that allows the second clock changeable frequency to be produced.

Another technical problem that also will see be recognize distribute to numerical value of second clock frequency with respect to first clock frequency the technique effect that value obtained that should select.

Another technical problem be recognize proportional parts offer about drift and shake to read unit and/or r/w cell satisfied desired condition of adjustment and the bit rate between first and second bit rates poor.

Another technical problem be recognize integral part offer about drift and shake to read unit and/or r/w cell satisfied desired condition of adjustment and the bit rate between first and second bit rates poor.

Another technical problem that also will see is a benefit of recognizing that key components when some proportional parts and integral part are brought when identical with above-mentioned two parts, and the necessary condition of this situation.

Technical problem also is present in the meaning that allows incoming bit stream and output bit flow to derive from differing transmission protocols.

Another technical problem that also will see is to recognize to allow a host-host protocol to be made of the PDH agreement and benefit and the meaning that is provided is provided the SDH agreement remaining host-host protocol.

Technical problem also is present in, and the benefit that is provided when second transmission frequency or bit rate are that system determines and depend on the SDH agreement is provided.

Another technical problem that will see is the benefit that is provided when distributing second definite transmission frequency of first clock frequency and system or bit rate for same frequency.

Another technical problem that also will see is that the benefit that is provided when influencing the adjustment of reading distance between unit and r/w cell by said filling is provided.

Another technical problem that also will see provides the essential necessary condition of filling possibility.

Solution

In order to solve above-mentioned one or more technical problem, the present invention begins with a system in order to inspection and adjustment transmit buffering, the bit stream of wherein importing transmit buffering has first transmission frequency or bit rate, and the output bit flow of transmit buffering has second transmission frequency or bit rate.

According to prior art, the information that each bit comprised in the incoming bit stream can write transmit buffering by r/w cell, and the information that each bit comprised that writes in the transmit buffering can be distributed to output bit flow by reading the unit.

In addition, give a relevant write pointer numerical value, this value gives a read pointer numerical value corresponding to the bit position in the transmit buffering that r/w cell write, and this value is corresponding to the bit position in the transmit buffering of reading to read the unit.

First transmission frequency or bit rate can be different with second transmission frequency or bit rate, check with adjusting device and comprise a proportional parts, an integral part and an adjustment member and check and adjust r/w cell and be transmitted to second transmission frequency to avoid overlapping between the unit, to prevent from simultaneously to shake and drift about from first transmission frequency with the bit distance of reading between the unit.

According to prior art, proportional parts is used to the difference and first limiting value between comparison read pointer value and the write pointer value, integral part by adder unit or adder with tolerance limit and predetermined value mutually adduction with gained sum and second limiting value relatively, so wherein results' intention of these comparisons produces reading the adjustment of bit distance between unit and r/w cell in the intermediation by adjustment member.

Proposed integral unit according to the present invention particularly and comprised that is reduced a sampling unit, integral unit moves with the clock frequency lower than system remainder by it by this.

The result of making is that the ratio unit moves with first clock frequency like this, and integral unit is with second clock frequency operation, and the numerical value of numeric ratio first clock frequency of giving the second clock frequency is low.

It is adjustable the invention allows for the reduction sampling unit, guarantees the variable of second clock frequency like this.

The present invention proposes the second clock frequency for being lower than 500 to 1500 times of first clock frequencies, be generally 1000 times.

First clock frequency arrives in the 3MHz scope 2, be typical reference clock frequency in the prior art, than the second clock frequency of low 1000 times of first clock frequency according to Nyquist criterion will smoothly be positioned at 1 to 1.5KHz effectively～this be the zone that is positioned at of great majority shake and drifting about-frequency tolerance.

Proportional parts is used for relatively first comparing unit of this difference that obtains and first limiting value with first subtrator of a difference that is used for detecting read pointer and write pointer and one and sets up.

Integral part is with second subtrator that is used for detecting the difference between read pointer and the write pointer, the 3rd subtrator that is used for detecting the tolerance limit between second difference that the unit obtains and expection difference, the sum unit or the adder of a plurality of continuous tolerance limits that the 3rd subtrator that is used for adding up is obtained, one is intended to be used for that behavior is adjusted in second comparing unit that compares with adding up of being obtained with second limiting value and response second comparing unit initialization and sum unit or adder are put clear Unit 0 of 0 is that core is set up.

What can expect is reciprocally to merge into a public subtrator by first and second subtrator that belongs to integral part that will belong to proportional parts to make said method more simple and efficient.

When incoming bit stream comes from first host-host protocol and distribute output bit flow to give second host-host protocol, also can use this system.

The present invention also allows first host-host protocol to comprise that the PDH agreement and second host-host protocol comprise the SDH agreement.

In the SDH agreement, determine that the transmission frequency of system or bit rate can reach 2 easily, 304MHz is normal.

According to the present invention, be the purpose of simplifying, the clock frequency that has also proposed first clock frequency and definite system is consistent, and also is 2 therefore, 304MHz.

Adjustment member is used for respectively the result according to one of the comparison of proportional parts and integral part gained, by filling the distance of adjusting r/w cell and reading the unit.

Forming output bit flow according to employed agreement is the normal data frame, fills at least to go out to comprise in the bit stream that at each two constitute the adjustment position:

-show that first transmission frequency or bit rate are lower than second transmission frequency or bit rate and when starting adjustment process, adjust the position for two and do not comprise information when comparative result,

-show that first transmission frequency or bit rate are higher than second transmission frequency or bit rate and when starting adjustment process, adjust the position for two and all comprise information when comparative result, or

-when being not activated adjustment process, one does not comprise information, another one comprises information.

Whether distribute to each adjusts the check digit in position and is used for indicating corresponding adjustments and is filled.

Advantage

Those advantages of the essential characteristic of system according to the invention have been to set up verification and have adjusted the possibility that writes with the reading number transmit buffering, one of them starts the time location tolerance limit that adjustment process can be eliminated the bit position of relevant expection tolerance limit, adjustment can compensate and be present in from a host-host protocol to another agreement, especially transfer to from the PDH territory SDH territory or in a way SDH territory internal information transmit the transmission frequency the desired transfer process or the difference of bit rate.The present invention is by above-mentioned advantage occurring supporting than prior art part and more effective inhibition shake and drift still less.

The essential characteristic of system of the present invention proposes in the feature clause of following claim 1.

Summary of drawings

Below with the essential characteristic that come more detailed description system of the present invention to have by way of example and with reference to the accompanying drawings, wherein

Fig. 1 is a schematic sketch, has sketched information flow and how to be transferred to another territory from a territory;

Fig. 2 is a block diagram of schematically having described the transmit buffering of tape verifying and Adjustment System;

Fig. 3 has described the function of annular transmit buffering;

Fig. 4 has described the influence between the each several part that uses different frequency in cut-off frequency and relevant inhibition or the elimination system;

Fig. 5 illustrates the function of describing integral part among figure A and the B;

Fig. 6 has described the embodiment of the reduction sampling unit of a proposition;

Fig. 7 has described an optional embodiment of verification and Adjustment System part;

Fig. 8 has described the basic comprising of a Frame;

Fig. 9 has described an optional embodiment with a plurality of parallel transmission bufferings.

Embodiment describes

The present invention relates to a system, and this system is intended to as between two dissimilar host-host protocols or a buffering area between the host-host protocol of two mutually the same types of same intranodal.

In the later case, need to suppress or the appearance of eliminating shake and drift is propagated and the different clock frequencies of expanding and compensate different nodal clocks by system to prevent identical shake and drift.Performance requirement does not in this case have preceding kind situation height, and however, the present invention will use under latter event, because the invention provides the solution of high-performance and energy-conservation cost.

The requirement of former instance is higher, because exist sizable difference between transmission frequency in two differing transmission protocols or the bit rate.Also may be such, promptly agreement be a PDH agreement and another is the SDH agreement.In this case, high requirement has been proposed the buffering area of working between two agreements so that can satisfy the high time precision requirement of SDH agreement.

The open-and-shut information of having described is how from being positioned at the first territory A among Fig. 1, for example leaves among the transmitter A1 in PDH territory, wherein runs on first transmission frequency Af or the bit rate.

Receiver A ' 1 is positioned at the second territory A ', and for example the SDH territory wherein runs on second transmission frequency A ' f or the bit rate.In order to manage the conversion of transmitting desired packet or Frame from a territory to another territory, a conversion equipment B is provided, this installs as the interface between two territory A and A '.Briefly, device B comprises a buffering area B1, a receiving element B2, a decoding unit B3, a coding unit B4 and a transmitting element B5.

Receiving element B2 receives according to the digital information of the employed agreement of the first territory A with the normal data frame format of the first transmission frequency Af or bit rate arrival.Each frame comprises in the relevant agreement about the customizing messages of frame format and has indicated the address information of receiver.Decoding unit B3 selects to transmit successively to arrive the master data bit of receiver A ' 1 for informational needs, meanwhile removes the data bit of particular frame.

Basic bit writes buffering area B1, subsequently in reading these bits herein and be forwarded to coding unit B4 from buffering area.Information here is re-encoded according to the agreement of using in the second territory A ' and forms the normal data frame.

Frame transmits into the second territory A ' by transmitting element B5 with the second transmission frequency A ' f or bit rate subsequently, arrives receiver A ' 1 at last.

One skilled in the art will appreciate that information flow can be in another direction transmission, although following description only is the transmission of a direction for what speak of for simplicity.

This technology is a prior art, because the invention particularly relates to the function of buffering area B1, so will not be set forth in other unit among the conversion equipment B herein.Similarly, also be prior art according to the Frame of different agreement or the ad hoc structure of data cell, so this paper will not do detailed elaboration to this.

Fig. 2 has described a system that is suitable for detecting and adjusting at least one buffering area B1 according to Fig. 1.Wherein, buffering area B1 comprises that sends a buffering area 1, wherein enters the bit stream 11 that sends buffering area and has first transmission frequency f1 or the bit rate, and the bit stream 12 of output has second transmission frequency f2 or the bit rate from buffering area 1.

The information that each comprised of incoming bit stream 11 can write by r/w cell 13 and send buffering area 1, and the information that each comprised that writes buffering area 1 can be read to distribute to output bit flow 12 by reading unit 14.

Fig. 3 has described a transmission buffering area 1 that may have annular FIFO (first in first out) buffering form, distributes these buffering area 148 bits under described embodiment situation, numbering from 0 to 47.Constantly give a write pointer 15 1 corresponding values in bit position that write with r/w cell 13, constantly give 16 1 of read pointers and the corresponding value of reading to be read unit 14 in bit position.

Because the first transmission frequency f1 or bit rate may be because shake or drifts and also may be temporarily different with the second transmission frequency f2 or bit rate owing to install actual functional capability among the B continuously, buffering area B1 also comprises one at two unit 13 and 14 inspection and adjusting devices of checking and starting the adjustment of this distance, to prevent reading unit 14 and r/w cell 13 hypotelorisms or overlapping said units, vice versa.

Check and adjusting device comprises 2, one integral parts 3 of a proportional parts and an adjustment member 4, function for the bit distance of 16 of inspection write pointer 15 and read pointers so that can adjust r/w cell 13 and read the bit distance of 14 of unit.

In the embodiment of Fig. 2, proportional parts 2 comprise one first subtrator 21 be used for checking give to the value of write pointer 15 with give poor to the value of read pointer 16, and first comparing unit 22 is used for the difference and first limiting value " a " comparison that will be obtained.

If this comparison shows that the bit distance of 15,16 on pointer is too small, the distance between comparing unit 4 start units 13 and the unit 14 is adjusted so.

Fig. 2 also indicates integral part 3 and comprises that one second subtrator 31 is used for checking the value of giving read pointer 14 and gives poor between the value of write pointer 16, one the 3rd subtrator 32 is used for checking second subtrator 31 difference that obtains and expection or estimates tolerance limit between difference " b ", sum unit or adder 33 a plurality of continuous tolerance limits that are used for adding up, one second comparing unit 34 is used for more resulting and is used in the adjustment process that second comparing unit 34 is started sum unit 33 being put 0 with one second limiting value " c " and a zero clearing unit 35.

Integral part 3 comprises that one is reduced sampling unit 36 so that integral part can be to be lower than the clock frequency operation of system's other parts.

This means proportional parts 2 with the operation of first clock frequency, integral part 3 is with the operation of second clock frequency, and the value of distributing to the second clock frequency is lower than the value of first clock frequency.

This method provides a kind of circuit structure (combinational logic and adder) of fairly simple integral part 3, and inactivity requires and is necessary with the circuit that the mean value of high-frequency operation forms.

Fig. 4 shows that the lower cut-off frequency according to the Nyquist criterion integral part will cause higher inhibition or the smooth effect in the effective frequency range, because clock frequency can compare with sampling frequency in this case.

According to Nyquist criterion, the cut-off frequency of effective range is approximately corresponding with half of sampling frequency (clock frequency), makes integral part 3 obtain the cut-off frequency fl more much lower than the cut-off frequency fp of ratio part 2.Really can significantly reduce when lower sampling frequency (clock frequency) in the effective frequency range, but because the main purpose that integral part suppresses is to suppress or eliminate low-frequency disturbance, this minimizing has constituted unrestricted to function.

On the other hand, should suitably allow proportional parts with the clock frequency operation identical, so that can still can compensate two transmission frequency f1, the quick variation that difference caused between f2 or bit rate with employed system frequency.

R/w cell 13 is write continuously with the speed that data bit 11 arrives buffering area.Reading unit 14 reads continuously with the speed of desired formation Frame among the second territory A '.Yet, the space of the speed of reading unit 14 being carried out specific adjusted is arranged, i.e. the increase of speed or minimizing in the structure of the Frame in second territory.

Fig. 3 indicates first limiting value " a " of proportional parts 2 work and is made up of two boundaries, and an overflow boundary " a1 " and a underflow boundary " a2 " are used for indicating completely or the limit of buffer empty.

In described situation, selected first limiting value " a " to be distributed in positive and negative six bits that enclose on weekly duty of read pointer 16 equably.

If reading unit 14 arrives in six bits of r/w cell 13, buffering area 1 just has the danger of being put sky so, that is to say and be necessary to reduce to a certain extent read rate, if and r/w cell 13 arrives in reading six bits of unit 14, buffering area just has the danger of overflowing so, that is to say that necessity improves read rate to a certain extent.

Fig. 3 has shown the depth B d of the buffering area that is called simultaneously here, and in other words it, read and write the distance between buffering area exactly corresponding to the bit number that writes buffering area but also do not read.

Fig. 5 is intended to further illustrate the function of integral part, and has shown the second limit value C of the required correspondence of integral part work.

Fig. 5 has illustrated two curve chart A and B.Figure A is intended to show how buffer depth changes in time.Time shaft only shows the degree of depth of buffering area when integrating circuit is accepted a value, that is to say when the second clock frequency is the one thousandth of first clock frequency, figure A only shows that every kilobit a buffer depth is arranged, therefore at two continuous time points, buffer depth has obvious variation, yet what should be mentioned that is the variation that Fig. 5 just simulates for the purpose of principle that integral part 3 is described.

Figure A has shown the variation of the buffer depth that does not have the read rate adjustment with the solid yardage bar, and represents with the short side bar through the variation of adjusting accordingly.

Similarly, figure B represents sum unit not only not adjustment but also the sum unit of not zero setting or the value of adder 33 with the solid yardage bar; And when sum unit when the threshold value of appointment has been carried out adjustment and zero setting, represent the value of sum unit with the short side bar.The time point of figure among the B with scheme A in same time point corresponding.

Sum unit 33 has been stored the buffer depth B that has detected _dWith the tolerance limit of expectation buffer depth, it is the numerical value that comes from the 3rd subtrator 32.Among the figure A, the expectation buffer depth is 24, and this is normal for the employed fifo buffer that comprises 48 in actual applications.

Because sum unit 33 meets addition with continuous tolerance limit band, figure B meets each time period of expression with band, corresponding to figure A from the last sum unit 33 zero setting to the area below the buffer depth curve of current time point and.Therefore, being starting point at the 0th time point with adder unit zero setting, among the figure B the instantaneous value of the 10th time point adder unit corresponding to figure A in area under the 0th and the 10th time point half interval contour.

Another limiting value c is by a maximum or minimum threshold value c1 or c2 decision, uses positive and negative 65 bit representations for illustrative purposes in figure B.

Figure B shows, at the 13rd time point, add value reached higher threshold value c1, at this moment begin to adjust the distance between read-write cell, shown in the 14th time point among the figure A; Sum unit 33 is by 35 zero setting of zero setting unit, shown in the 14th time point of figure B.Further adjustment occurs in the 25th, 26 respectively; 31,32; With 48,49 time points.

Curve understands that under situation about slowly changing integral part had begun to adjust before the buffer depth value of reaching capacity a, this limiting value corresponds respectively to buffer depth 6 (a4 among Fig. 3) and 42 (a1 among Fig. 3) at figure A.In changing fast, buffer depth can reach these limiting values, therefore, at this moment needs proportional parts to carry out once or more times adjustment.

Fig. 6 has shown that reduction sampling unit 36 has comprised a frequency divider 36a, this frequency divider carries out frequency division to the frequency that system uses, for example, and two and a door 36b, 36b ' only allows to have and is passed through by that value in two pointers 15,16 of branch frequency fnd same frequency.To work with clock frequency fnd in those unit of working in integral part.

Reducing sampling unit can adjust by an adjustable frequency divider 36a, and this frequency divider can be chosen Frequency Dividing Factor arbitrarily.This can make the second clock frequency become variable and be changed to desired value.The suitable Frequency Dividing Factor of system frequency will carry out frequency division, make the second clock frequency be followed successively by the value in 500 to 1500, preferably be about the one thousandth of first clock frequency.

This frequency division makes in the integral part 3 employed element to comprise and compares under integral part 3 and the situation of other parts with same clock frequency work, and simpler, energy consumption is widget more.

In order to obtain a result that can compare with the expected results that obtains by method of the present invention by existing technology, constantly form a mean value in real time in the time T in integral unit (1/ use clock frequency) or summation is necessary, this has caused requiring these end points to use the logic of complexity.Therefore, a foundation reduction sampling of the present invention integral part can reduce the quantity of used complex logic and the loss of power greatly.

What deserves to be mentioned is that the saving of power is directly proportional with the quadratic relationship of Frequency Dividing Factor theoretically, that is to say, when Frequency Dividing Factor is 1000, can obtain 1 millionfold saving power.

Be locked to the frequency division of a low speed mainly due to the logic in foundation integral part of the present invention, it is according to prior art, when forming a mean value logic desired and that system clock (being generally the second clock frequency) is locked compare low, so energy-efficient primarily obtains.

In order to save more element, Fig. 7 illustrates a kind of like this embodiment, wherein belongs to first subtrator 21 of proportional parts 2 and belongs to second subtrator 31 of integral part 3, is made up of a public subtrator 17.Except having saved a subtrator, also can with two in reducing sampling unit 36 with a door 36b, 36b ' with one with a door 36b " replacement.

Under the situation of this embodiment, the incoming bit stream and the output bit flow that come from first host-host protocol are transmitted to second host-host protocol, are the PDH agreements at this first host-host protocol, and second host-host protocol is the SDH agreement.

According to this embodiment, a typical transmission frequency that enters and come from the bit stream of transmit buffer is 2,304MHz, it is corresponding to the PCM agreement (pulse code modulation) that has information bit (pay(useful) load) and agreement special bit (protocol overhead) of a standard.

So far, second transmission frequency or bit rate f2 are defined as 2 by system, 304MHz.

Therefore first clock frequency is changed to 2,304th, simple, because this frequency comprises system frequency fs, and be obtainable in system.

According to the embodiment of this proposition, adjustment member is that the result of one of two comparing units 22,34 of foundation realizes adjusting by the filling that is called here.

In the SDH agreement,, there be certain space between adjustment bit that is called and associated check bit here as a part that is used for forming data frame structure.As Fig. 8 explanation, in the SDH agreement, be called the data frame structure of TU2 (branch units 12).

In the frame structure of TU12, there are two bits to constitute the adjustment bit that this paper is called, i.e. S1 and S2.

When forming Frame, adjustment comprises following several respects:

-when since comparing unit 22,34 to show first transmission frequencies or bit rate f1 low than second transmission frequency or bit rate f2, and when beginning to adjust, will adjust bit S1, S2 all puts sky.

-when because comparing unit 22,34 shows first transmission frequencies or bit rate f1 than second transmission frequency or bit rate f2 height, and when beginning to adjust, information put into adjust bit S1, S2.

-when not adjusting, information is put into adjustment bit S1, put sky and will adjust bit S2.

Each adjusts bit S1, and S2 all interrelates with check bit, and these check bits are to be used for showing that the adjustment bit is completely or sky.

Fig. 8 has shown, according to existing protocol, is used for other a large amount of bit of construction data frame.Yet these bits and the present invention are irrelevant, therefore its function are not done detailed description yet here.

When implement adjusting, adjustment unit 4 according to the adjustment type of using, is read unit 14 by lead 41 orders, reads unnecessary bit to be higher than common reading rate, or stops and bit is read in inhibition.Simultaneously, coding unit B4 according to the adjustment implemented and current agreement, receives necessary information by lead 42 and packs into and adjust bit S1, S2, and give check bit C1, C2 gives correct value.

Select the second clock frequency so that in integral part 3, formed each Frame in the second territory A ' is once compared.Check buffer depth and in conjunction with writing bit S1 and S2 estimates necessary adjustment.

This makes can be according to current requirement by reading an added bit and increase the reading rate of some time simultaneously, and read a bit less and reduce At All Other Times reading rate simultaneously, can adjust the speed of reading unit 14.

For example can be applied in lock bit mapping, wherein with byte number, promptly n position bit number is one group and comes process information, and n is generally 8, wherein also uses parallel data to handle.System of the present invention also can be applicable to application as shown in Figure 9.

N transmit buffering 11,12,1n moves with parallel mode, and comprise and read the unit and r/w cell also moves with parallel mode, although transmit buffer 11 to all parallel runnings, 12 ... 1n must implement to check the adjustment that is started concurrently, and that checks parallel running independently comprises that one of transmit buffer of 11 is enough.

The present invention is not limited to embodiment as herein described, and is described as following claims, can carry out multiple modification in the concept and range of the present invention.

Claims (13)

1. system that checks and adjust at least one transmit buffer, the bit stream that wherein enters this transmit buffer has first transmission frequency or bit rate, the bit stream that comes out from the transmission buffering area has second transmission frequency or bit rate, each bit information of distributing to incoming bit stream can write buffering area by a r/w cell, distributing to each writes the bit information that sends buffering area and can read the unit by one and read and distribute to output bit flow, the bit position of the transmit buffer that the numerical value of giving write pointer writes corresponding to r/w cell, give the bit position of the numerical value of read pointer corresponding to the transmit buffer of reading to read the unit, first above-mentioned transmission frequency or bit rate are different with above-mentioned second transmission frequency or bit rate, check and adjusting device for one, comprising a proportional parts, an integral part and an adjustment member, adjustment member is used for checking the bit distance between between write pointer and read pointer, and in case of necessity, adjust above-mentioned r/w cell and the above-mentioned bit distance of reading between the unit, proportional parts compares the difference of write pointer value and read pointer value with first limiting value, integral part by sum unit with the tolerance value between the above-mentioned difference and a desired value addition, the summation that obtains can be compared with second limiting value, the result of one of above-mentioned comparison can be used to start the adjustment of above-mentioned distance by means of adjustment unit, proportional parts runs on first clock frequency, it is characterized in that integral part comprises that is reduced a sampling unit; Integral part moves with the second clock frequency; Above-mentioned second clock frequency values is lower than first clock frequency.

2. according to the system of claim 1, it is characterized in that first clock frequency is the clock frequency that system determines; It is adjustable reducing sampling unit; The second clock frequency is variable by this.

3. according to the system of claim 1 or 2, it is characterized in that the second clock frequency is preferably 1000 times for being lower than 500 to 1500 times of first clock frequencies.

4. according to the system of claim 1, it is characterized in that, proportional parts comprise one be used for detecting the numerical value of giving read pointer and give first subtrator of the difference between the numerical value of write pointer and one be used for relatively first comparing unit of this difference that obtains and first limiting value.

5. according to the system of claim 1 or 4, it is characterized in that, integral part comprises second subtrator that is used for detecting the numerical value of giving read pointer and gives the difference between the numerical value of write pointer, the 3rd subtrator that is used for detecting the tolerance limit between detected difference in Unit second and expection difference, the sum unit of the detected a plurality of continuous tolerance limits of the 3rd subtrator that are used for adding up, one is used for obtain second comparing unit that adds up and compare with second limiting value and one are put clear Unit 0 of 0 with sum unit being started under the situation about adjusting by above-mentioned second comparing unit.

6. according to the system of claim 4 or 5, it is characterized in that first subtrator that adheres to proportional parts separately comprises a public subtrator with second subtrator that belongs to integral part.

7. according to the system of claim 1, it is characterized in that incoming bit stream is from first host-host protocol; Output bit flow obtains according to second transport protocol conversion.

8. according to the system of claim 7, it is characterized in that first host-host protocol is the PDH agreement.

9. according to the system of claim 7, it is characterized in that second host-host protocol is the SDH agreement.

10. according to the system of claim 1, it is characterized in that second transmission frequency or bit rate are determined by system; This frequency or bit rate are preferably 2,304MHz between 2MHz and 3MHz.

11. the system according to claim 1 is characterized in that, first clock frequency arrives in the 3MHz scope 2, is preferably 2,304MHz.

12. the system according to claim 1 is characterized in that, adjustment member depends on one of result of comparison and implements adjustment process by filling.

13. the system according to claim 12 is characterized in that, output bit flow forms the normal data frame; Above-mentioned filling comprises dibit at least, and each output data frame comprises the adjustment bit, and

-show that above-mentioned first transmission frequency or bit rate are lower than above-mentioned second transmission frequency or bit rate and when starting adjustment process, it all be sky that dibit is adjusted bit when comparative result,

-show that above-mentioned first transmission frequency or bit rate are higher than above-mentioned second transmission frequency or bit rate and when starting adjustment process, dibit is adjusted bit and all comprised information when comparative result, or

-when being not activated adjustment process, a bit is empty, another bit comprises information; And

Whether be assigned to each adjusts check bit of bit and is used for indicating corresponding adjustment bit and is filled.

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