CN1204919A - Scanning device with image storage and grey level decoding output - Google Patents

Scanning device with image storage and grey level decoding output Download PDF

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CN1204919A
CN1204919A CN 97111960 CN97111960A CN1204919A CN 1204919 A CN1204919 A CN 1204919A CN 97111960 CN97111960 CN 97111960 CN 97111960 A CN97111960 A CN 97111960A CN 1204919 A CN1204919 A CN 1204919A
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马卓钊
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Abstract

A scanner with image storage and grey-scale decoded output is composed of input control circuit, output control circuit, image storage circuit unit, decoding and correcting circuit and output matrix circuit. The LED display screen of said scanner can be used to increase the number of fields to be refreshed per second, and the grey scales of display, and is easy to connect with multimedia part of computer.

Description

The scanning device of band Image storage and grey level decoding output
The present invention relates to a kind of scanning device, belong to the technical field of scanning means with Image storage and grey level decoding output.
The scanning device of so-called band Image storage and grey level decoding output is meant the pictorial data that can store in its scan control scope in this device, when these data outputs, carry out grey level decoding output, on LED (emitting semiconductor) display screen of its control, can show stratified image according to scanning sequency.This device have pictorial data handle simple, the Image storage address can with the calculator memory unified addressing, data write and show with image and not disturb advantage stable, levels are rich that image shows mutually.It comprises input control circuit, output control circuit, dual-port static memory, decoding correcting circuit and output matrix circuit.
The scanning device that existing LED display uses is to be replaced by general register, and Fig. 2 is that a kind of typical use 8 bit string types move into the 1/16 dynamic scan LED dot matrix display screen scanner circuitry of serial/parallel output register 74HC595 as scanning device.Every as can be seen demonstration one field pattern resembles, and the data in the 74HC595 will be refreshed 16 times.If show the image of 16 grades of gray scales, each grade gray scale all needs to show a field pattern elephant, just the refreshing frequency of 74HC595 need be improved 16 times on existing basis.Have only when scanning frequency reaches 60 of each seconds, people's eyes just can be seen a basicly stable image.In fact the many more images of unit interval interscan number of fields are just stable more, and the high more visual level of tonal gradation is just abundant more.Utilize circuit shown in Figure 2 to form 128 * 128 dot matrix LED displays, calculate the refreshing frequency that to see different scanning number of fields and different tonal gradation condition 74HC595 according to following formula and change.
Fm=m * n * ft * w is wherein: fm is a refreshing frequency, and m, n count for the LED display ranks, and ft is that per second shows number of fields, and w is a tonal gradation; Known: m * n=128 * 128fm: hertz (Hz) subordinate list 1
16 grades of gray scales 64 grades of gray scales 128 grades of gray scales 256 grades of gray scales
60/second ????15，728，640 ????62，914，560 ????125，829，120 ????251，658，240
120/second ????31，457，280 ????125，829，120 ????251，658，240 ????503，316，480
240/second ????62，914，560 ????251，658，240 ????503，316，480 ????1，006，632，960
Adopt conventional logical device, clock frequency is the highest can only reach 30 megahertzes for HC series.By subordinate list 1 as can be known, the scanning device that structure shown in Figure 2 adopted can only carry out 16 grades of gray scales, 60/second image shows, improves the restriction that display gray scale grade and scanning number of fields have been subjected to components and parts on this basis.Therefore, how to improve scanning number of fields and tonal gradation, reducing refreshing frequency fm as far as possible simultaneously is difficult problem of scanning means technical field, needs to be resolved hurrily.
Order of the present invention ground is that a kind of scanning device with Image storage and grey level decoding output will be provided, and 512 byte dual-port static memories is arranged, separate input, output control circuit, decoding correcting circuit and grey level decoding output matrix circuit in its inside.Use the LED display of this scanning device to improve and refresh number of fields each second, improve display gray scale, be connected with the computer media parts easily, thereby thoroughly solved the gray scale demonstration problem of LED display.
The object of the present invention is achieved like this:
1 scanning device is made up of six circuit units and external terminal.They are respectively: input control circuit unit U1, output control circuit unit U2, Image storage circuit unit U3, decoding correcting circuit unit U4, output matrix circuit unit U5U6; Input control pin WR, ADDR0, ADDR1, ID0, ID1, CS, HS, VS, output control pin ROW0～ROW4, ICLK, OPUL, OPULEN, data input pin D0～D7 proofreaies and correct base pin selection S0, S1, output pin DOUT0～DOUT15 and MOD, TSTEN.
The WR of U1, ADDR[0], ADDR[1], ID[0], ID[1], CS, HS, VS and the corresponding connection of input control pin, the SADDR[0 of U1]～SADDR[8] with the WA[0 of U3]～WA[8] corresponding connection, the WEN of U1 holds with the WEB of U3 and is connected.
ROW0～ROW4 of U2, ICLK, OPUL, OPULEN and the corresponding connection of output control pin, the DEB[0 of U2]～DEB[4] with the RA[4 of U3]～RA[8] corresponding connection, the CO[0 of U2]～CO[3] with the RA[0 of U3]～RA[3] corresponding connection, the CO[0 of U2]～CO[7] with the W[0 of U5U6]～W[7] corresponding connection, the OCLK of U2 is connected with the CLK of U5U6, the A of U2 is connected with the SEL of U5, and the B of U2 is connected with the SEL of U6.
The WA[0 of U3]～WA[8] with RA[0]～RA[8] with outside U1, U2 are connected, DI[0]～DI[7] corresponding connection with the data input pin, the DO[0 of U3]～D0[7] with the DIN[0 of U4]～DIN[7] corresponding connection, the OEB of U3, REB ground connection.
The DIN[0 of U4]～DIN[7] with outside U3 is connected, the corresponding connection of S0, S1, OUT[0 with the correction base pin selection]～OUT[7] with the AO[0 of U5U6]～AO[7] corresponding connection.
The AO[0 of U5]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U5]～DOUT[7] corresponding connection with output pin DOUT0～DOUT7.
The AO[0 of U6]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U6]～DOUT[7] corresponding connection with output pin DOUT8～DOUT15.
2 input control circuit unit U1 are by 5 parallel-by-bit counter U1-A, 6 parallel-by-bit counter U1-B, and 4 inputs or door U1-1,3 inputs or door U1-2,2 inputs or door U1-3,2 inputs and door U1-4,2 input XOR gate U1-5, U1-6 connect to form.
WR is connected with 1 end of U1-1, ADDR[1], ID[1] with U1-5 1,2 ends connect respectively, 3 ends of U1-5 are connected with 1 end of U1-2, ADDR[0], ID[0] with U1-6 1,2 ends connect respectively, 3 ends of U1-6 are connected with 2 ends of U1-2, CS is connected with 3 ends of U1-2,4 ends of U1-2 are connected with 2 ends of U1-1, HS is connected with 1 end of U1-3, the Q[5 of U1-B3] with 2 ends of U1-3,3 ends of U1-1 connect, 3 ends of U1-3 and 1 end of U1-4, the CLK of U1-B connects, 2 ends of VS and U1-4, the CDN of U1-B connects, and 3 ends of U1-4 are connected with the CDN of U1-A, the Q[4 of U1-A] be connected with 4 ends of U1-1,5 ends of U1-1 and the CLK of U1-A, WEN connects, the Q[0 of U1-A]～Q[3] with SADDR[0]～SADDR[3] corresponding connection, the Q[0 of U1-B]～Q[4] with SADDR[4]～SADDR[8] corresponding connection.
3 output control circuit unit U2 add a circuit U 2-B by delay control circuit U2-A, 8 parallel-by-bit counter U2-C, inverse gate U2-1, U2-2, U2-3,2 inputs or door U2-4, U2-5, U2-6, U2-7,2 inputs and door U2-8,4 input nand gate U2-9 connect to form.
C0～C4 of ROW0～ROW4 and U2-A, the DI[0 of U2-B]～DI[4] the corresponding connection, the CS of U2-A is connected with 1 end of U2-4, OPUL is connected with 1 end of U2-5,1 end of OPULEN and U2-3,2 ends of U2-5 connect, 2 ends of U2-3 are connected with 2 ends of U2-4,3 ends of U2-4 are connected with 1 end of U2-8,3 ends of U2-5 are connected with 2 ends of U2-8,3 ends of U2-8 are connected with the CDN of U2-C, the CLK of ICLK and U2-C, OCLK connects, the Q[3 of U2-C] with 1 end of U2-1,1 end of U2-7 connects, the Q[4 of U2-C] be connected with 1 end of U2-2,2 ends of U2-2 are connected the Q[5 of U2-C with 1 end of U2-9], Q[6], Q[7] with U2-9 2,3,4 ends connect respectively, 5 ends of U2-9 and 2 ends of U2-6,2 ends of U2-7 connect, the DO[0 of U2-B]～DO[4] with DEB[0]～DEB[4] corresponding connection, the Q[0 of U2-C]～Q[7] with C0[0]～C0[7] corresponding connection, 3 ends of U2-8 are connected with B, 3 ends of U2-7 are connected with A.
4 decode correcting circuit unit U4 by 4/8 decoder U4-A, 5/8 decoder U4-B, and 6/8 decoder U4-C, two 4 select a device U4-D, U4-E, U4-F, U4-G to connect to form.
DIN[0]～DIN[3] respectively with the IO[0 of U4-A]～IO[3] be connected, DIN[0]～DIN[4] respectively with the I1[0 of U4-B]～I1[4] be connected, DIN[0]～DIN[5] respectively with the I2[0 of U4-C]～I2[5] be connected, U4-D, U4-E, U4-F, the 1C0 of U4-G, the O0[7 of 2C0 and U4-A]～O0[0] corresponding connection, U4-D, U4-E, U4-F, the 1C1 of U4-G, the O1[7 of 2C1 and U4-B]～O1[0] corresponding connection, U4-D, U4-E, U4-F, the 1C2 of U4-G, the O2[7 of 2C2 and U4-C]～O2[0] corresponding connection, U4-D, U4-E, U4-F, the 1C3 of U4-G, 2C3 and DIN[7]～DIN[0] corresponding connection, S0, S1 respectively with U4-D, U4-E, U4-F, the A of U4-G, B connects, U4-D, U4-E, U4-F, the 1Y of U4-G, the corresponding respectively OUT[7 that connects of 2Y]～OUT[0], U4-D, U4-E, U4-F, the 1G of U4-G, 2G ground connection.
5 output matrix circuit unit U5U6 use pulse-width modulator U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, U5-H and 3/8 decoder U5-I to connect to form.
AO[0]～AO[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the A[0 of U5-H]～A[7] the corresponding connection, W[0]～W[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the B[0 of U5-H]～B[7] the corresponding connection, W[0]～W[2] with the A of U5-I, B, C is corresponding to be connected, SEL is connected with the G1 of U5-I, MOD, CLK, TSTEN and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the MOD of U5-H, CLK, TSTEN is corresponding to be connected, Y0～Y7 of U5-I respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the EN of U5-H connects, AO[0]～AO[7] respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the TSTIN of U5-H connects, U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the OP of U5-H connects DOUT[0 respectively]～DOUT[7].
6 delay control circuit U2-A are by 15ns delayer U2-D, U2-E, U2-F, U2-G, U2-H, and 2 import XOR gate U2-10, U2-11, U2-12, U2-13, U2-14,3 inputs or door U2-15, U2-16, and 2 input NOR gate U2-17 connect to form.
1 end of C0 and U2-D, 2 ends of U2-10 connect, 2 ends of U2-D are connected with 1 end of U2-10,3 ends of C1 and U2-E, 2 ends of U2-11 connect, 4 ends of U2-E are connected with 1 end of U2-11,5 ends of C2 and U2-F, 2 ends of U2-12 connect, 6 ends of U2-F are connected with 1 end of U2-12,7 ends of C3 and U2-G, 2 ends of U2-13 connect, 8 ends of U2-G are connected with 1 end of U2-13,9 ends of C4 and U2-H, 2 ends of U2-14 connect, 10 ends of U2-H are connected with 1 end of U2-14,3 ends of U2-10 are connected with 1 end of U2-15, and 3 ends of U2-11 are connected with 2 ends of U2-15, and 3 ends of U2-12 are connected with 3 ends of U2-15,3 ends of U2-13 are connected with 1 end of U2-16,3 ends of U2-14 are connected with 2 ends of U2-16, the 3 end ground connection of U2-16, and 4 ends of U2-15 are connected with 1 end of U2-17,4 ends of U2-16 are connected with 2 ends of U2-17, and 3 ends of U2-17 are connected with CS.
7 add a circuit U 2-B by inverter U2-18, U2-19, U2-20,2 input XOR gate U2-21,2 inputs with or door U2-22, U2-23, U2-24,2 input nand gate U2-25, U2-26, U2-27 connect to form.
DI[0] with 1 end of U2-18,2 ends of U2-21,2 ends of U2-25 connect, DI[1] with 1 end of U2-21,1 end of U2-25 connects, DI[2] with 1 end of U2-22,1 end of U2-26 connects, DI[3] with 1 end of U2-23,2 ends of U2-27 connect, DI[4] be connected with 1 end of U2-24,3 ends of U2-25 and 2 ends of U2-22,1 end of U2-19 connects, 2 ends of U2-19 are connected with 2 ends of U2-26,3 ends of U2-26 and 2 ends of U2-23,1 end of U2-20 connects, 2 ends of U2-20 are connected with 1 end of U2-20,3 ends of U2-27 are connected with 2 ends of U2-24,2 ends and the DO[0 of U2-18] be connected 3 ends and the DO[1 of U2-21] be connected 3 ends and the DO[2 of U2-22] be connected, 3 ends and the DO[3 of U2-23] be connected 3 ends and the DO[4 of U2-24] be connected.
The circuit diagram of Fig. 1 scanning device
The circuit diagram of Fig. 1-A input control circuit
The circuit diagram of Fig. 1-B output control circuit
The circuit diagram of Fig. 1-C decoding correcting circuit
The circuit diagram of Fig. 1-D output matrix circuit
The circuit diagram of Fig. 1-B-A delay control circuit
Fig. 1-B-B adds the circuit diagram of a circuit
Now in conjunction with the accompanying drawings the structure and the circuit diagram of the scanning device of band Image storage and grey level decoding output is described below.
By Fig. 1, the scanning device of band Image storage and grey level decoding output is made up of six circuit units and external terminal.They are respectively: input control circuit unit U1, output control circuit unit U2, Image storage circuit unit U3, decoding correcting circuit unit U4, output matrix circuit unit U5U6; Input control pin WR, ADDR0, ADDR1, ID0, IDI, CS, HS, VS, output control pin ROW0～ROW4, ICLK, OPUL, OPULEN, data input pin D0～D7 proofreaies and correct base pin selection S0, S1, output pin DOUT0～DOUT15 and MOD, TSTEN.
The WR of U1, ADDR[0], ADDR[1], ID[0], ID[1], CS, HS, VS and the corresponding connection of input control pin, the SADDR[0 of U1]～SADDR[8] with the WA[0 of U3]～WA[8] corresponding connection, the WEN of U1 holds with the WEB of U3 and is connected.
ROW0～ROW4 of U2, ICLK, OPUL, OPULEN and the corresponding connection of output control pin, the DEB[0 of U2]～DEB[4] with the RA[4 of U3]～RA[8] corresponding connection, the CO[0 of U2]～CO[3] with the RA[0 of U3]～RA[3] corresponding connection, the CO[0 of U2]～CO[7] with the W[0 of U5U6]～W[7] corresponding connection, the OCLK of U2 is connected with the CLK of U5U6, the A of U2 is connected with the SEL of U5, and the B of U2 is connected with the SEL of U6.
The WA[0 of U3]～WA[8] with RA[0]～RA[8] with outside U1, U2 are connected, DI[0]～DI[7] corresponding connection with the data input pin, the DO[0 of U3]～D0[7] with the DIN[0 of U4]～DIN[7] corresponding connection, the OEB of U3, REB ground connection.
The DIN[0 of U4]～DIN[7] with outside U3 is connected, the corresponding connection of S0, S1, OUT[0 with the correction base pin selection]～OUT[7] with the AO[0 of U5U6]～AO[7] corresponding connection.
The AO[0 of U5]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U5]～DOUT[7] corresponding connection with output pin DOUT0～DOUT7.
The AO[0 of U6]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U6]～DOUT[7] corresponding connection with output pin DOUT8～DOUT15.
The dual-port static memory U3 model that scanning device adopts is CC2P1T, writes the SADDR[0 of address by input control circuit U1]～SADDR[8] form.Data are delivered to the data input port DI[0 of memory U3 by pin D0～D7]～DI[7], read the CO[0 of address by output control circuit U2]～CO[3], DEB[0]～DEB[4] form, the data of U3 output DO[0]～D[7] meet the data input pin DIN[0 of decoding correcting circuit U4]～DIN[7], the data of U3 read control bit REB and output allows position OEB ground connection can make the data output of U3 keep continuous variation with reading address change.
By Fig. 1-A, input control circuit unit U1 is by 5 parallel-by-bit counter U1-A, 6 parallel-by-bit counter U1-B, and 4 inputs or door U1-1,3 inputs or door U1-2,2 inputs or door U1-3,2 inputs and door U1-4,2 input XOR gate U1-5, U1-6 connect to form.
WR is connected with 1 end of U1-1, ADDR[1], ID[1] with U1-5 1,2 ends connect respectively, 3 ends of U1-5 are connected with 1 end of U1-2, ADDR[0], ID[0] with U1-6 1,2 ends connect respectively, 3 ends of U1-6 are connected with 2 ends of U1-2, CS is connected with 3 ends of U1-2,4 ends of U1-2 are connected with 2 ends of U1-1, HS is connected with 1 end of U1-3, the Q[5 of U1-B] be connected with 3 ends of 2 ends-U1-1 of U1-3,3 ends of U1-3 and 1 end of U1-4, the CLK of U1-B connects, 2 ends of VS and U1-4, the CDN of U1-B connects, and 3 ends of U1-4 are connected with the CDN of U1-A, the Q[4 of U1-A] be connected with 4 ends of U1-1,5 ends of U1-1 and the CLK of U1-A, WEN connects, the Q[0 of U1-A]～Q[3] with SADDR[0]-SADDR[3] corresponding connection, the Q[0 of U1-B]～Q[4] with SADDR[4]～SADDR[8] corresponding connection.
U1-1 model: OR04, U1-2 model: OR03
U1-3 model: OR02, U1-4 model: AN02
U1-5 model: XO02, U1-6 model: XO02
U1-A model: COU5CDN
U1-B model: COU6CDN
Input control circuit U1, by using 2 input XOR gate U1-5, U1-6 and 3 inputs or a door U1-2 to form address comparison circuit, use low 4 Q[0 of 5 parallel-by-bit counter U1-A]～Q[3] and 6 parallel-by-bit counter U1-B hang down 5 Q[0]～Q[4] composition U3 write address SADDR[0]～SADDR[8].As ADDR[0] ADDR[1] with ID[0] ID[1] equate, clock CLK that CS allows during for low level the WEB of WR by the 5 ends control U3 of 4 inputs or door U1-1 to drive 5 parallel-by-bit counter U1-A simultaneously makes it add one.As the full 16 back Q[4 of U1-A meter] high level exported will be closed U1-1 makes the WR signal can not pass through U1-1.HS is by 2 inputs or door U1-3 and 2 inputs and the zero clearing position CDN of door U1-4 control U1-A and the clock CLK of U1-B.When VS was high level, the height high level of HS changed the U1-A zero clearing and recovers its count status, makes U1-B add one simultaneously.Behind U1-B meter full 32, the Q[5 of U1-B] high level of output will close U1-1 and U1-3 makes WR and HS all can not work.The height high level of VS changes U1-A and U1-B zero clearing, makes WR and HS enter enable state.The purpose of design address comparison circuit is to make the circuit structure of scanning device be convenient to expand to connect, and utilizes HS control to write the low 4 and to utilize VS to control high 5 purpose that writes the address be to be convenient to this structure be connected with the computer media vision signal of address.
By Fig. 1-B, output control circuit unit U2 adds a circuit U 2-B by delay control circuit U2-A, 8 parallel-by-bit counter U2-C, inverse gate U2-1, U2-2, U2-3,2 inputs or door U2-4, U2-5, U2-6, U2-7,2 inputs and door U2-8,4 input nand gate U2-9 connect to form.
C0～C4 of ROW0～ROW4 and U2-A, the DI[0 of U2-B]～DI[4] the corresponding connection, the CS of U2-A is connected with 1 end of U2-4, OPUL is connected with 1 end of U2-5,1 end of OPULEN and U2-3,2 ends of U2-5 connect, 2 ends of U2-3 are connected with 2 ends of U2-4,3 ends of U2-4 are connected with 1 end of U2-8,3 ends of U2-5 are connected with 2 ends of U2-8,3 ends of U2-8 are connected with the CDN of U2-C, the CLK of ICLK and U2-C, OCLK connects, the Q[3 of U2-C] with 1 end of U2-1,1 end of U2-7 connects, the Q[4 of U2-C] be connected with 1 end of U2-2,2 ends of U2-2 are connected the Q[5 of U2-C with 1 end of U2-9], Q[6], Q[7] with U2-9 2,3,4 ends connect respectively, 5 ends of U2-9 and 2 ends of U2-6,2 ends of U2-7 connect, the DO[0 of U2-B]～DO[4] with DEB[0]～DEB[4] corresponding connection, the Q[0 of U2-C]～Q[7] with CO[0]～CO[7] corresponding connection, 3 ends of U2-8 are connected with B, 3 ends of U2-7 are connected with A.
U2-1 model: IN01, U2-2 model: IN01, U2-3 model: IN01
U2-4 model: OR02, U2-5 model: OR02, U2-6 model: OR02
U2-7 model: OR02, U2-8 model: OR02, U2-9 model: NA04
U2-A is a delay circuit, and U2-B is for adding a circuit, U2-C model: COU8CDN
Output control circuit U2, the purpose of using delay circuit U2-A is that the output CS of U2-A when any one signal generation high-low level of ROW0～ROW4 changes can produce a high level of height and changes 8 parallel-by-bit counter U2-C zero clearings and restart a new decoding and export the cycle.(Fig. 1-B-A) utilizes former 1,2 ends of should C0～C4 receiving 2 input XOR gate U2-10～U2-14 respectively by delay cell U2-D～U2-H of XOR to delay circuit U2-A, when the level variation takes place in C0～C4, because the effect of delay cell, output in XOR gate will produce a low high-low level variation, by 3 inputs or door U2-15, U2-16 and 2 input NOR gate U2-17 outputs.In the U2 structure, the effect of OPUL is that the low level generation blanking effect of OPUL when utilizing any one signal generation high-low level of ROW0～ROW4 to change can be controlled LED display brightness.OPULEN selects signal control line, when OPULEN is low level, selects the OPUL function, closes the CS output of U2-A, and vice versa.Add a circuit U 2-B (function of Fig. 1-B-B) is output DEB[0 after ROW0～ROW4 carries out binary add one by this circuit]～DEB[4].The effect of gate circuit U2-1, U2-2, U2-7, U2-8 and U2-9 is as 8 parallel-by-bit counter U2-C output Q[7]～Q[4] Q[3 when being 1110] A output low level B output high level, Q[3 when being 0] A output high level B output low level when being 1, the another one effect of U2-C output is the grey level decoding comparator base value as output matrix U5U6.ICLK is the counting clock of U2-C.
By Fig. 1-C, correcting circuit unit U4 is by 4/8 decoder U4-A in decoding, 5/8 decoder U4-B, and 6/8 decoder U4-C, two 4 select a device U4-D, U4-E, U4-F, U4-G to connect to form.
DIN[0]～DIN[3] respectively with the I0[0 of U4-A]～I0[3] be connected, DIN[0]～DIN[4] respectively with the I1[0 of U4-B]～I1[4] be connected, DIN[0]～DIN[5] respectively with the I2[0 of U4-C]～I2[5] be connected, U4-D, U4-E, U4-F, the 1C0 of U4-G, the O0[7 of 2C0 and U4-A]～O0[0] corresponding connection, U4-D, U4-E, U4-F, the 1C1 of U4-G, the O1[7 of 2C1 and U4-B]～O1[0] corresponding connection, U4-D, U4-E, U4-F, the 1C2 of U4-G, the O2[7 of 2C2 and U4-C]～O2[0] corresponding connection, U4-D, U4-E, U4-F, the 1C3 of U4-G, 2C3 and DIN[7]～DIN[0] corresponding connection, S0, S1 respectively with U4-D, U4-E, U4-F, the A of U4-G, B connects, U4-D, U4-E, U4-F, the 1Y of U4-G, the corresponding respectively OUT[7 that connects of 2Y]～OUT[0], U4-D, U4-E, U4-F, the 1G of U4-G, 2G ground connection.
U4-A model: SB-16T256, U4-B model: SB-32T256
U4-C model: SB-64T256
U4-D model: LS153, U4-E model: LS153
U4-F model: LS153, U4-G model: LS153
Decoding correcting circuit U4, use 4/8 adjuster U4-A, 5/8 adjuster U4-B, 6/8 adjuster U4-C, purpose is it to be corrected to 256 grades of gray scales when pictorial data source during for 16 grades, 32 grades of gray scales or 64 grades, makes full use of 256 grades of grey level decoding abilities and improves image contrasts.1 device U4-D～U4-G is selected in S0, S1 control two 4, and the selection gray scale arrives OUT[0 for 16 grades, 32 grades, 64 grades or 256 grades]～OUT[7] output.
By Fig. 1-D, output matrix circuit U5U6 is to be connected to form by pulse-width modulator U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, U5-H and 3/8 decoder U5-I.
AO[0]～AO[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the A[0 of U5-H]～A[7] the corresponding connection, W[0]～W[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the B[0 of U5-H]～B[7] the corresponding connection, W[0]～W[2] with the A of U5-I, B, C is corresponding to be connected, SEL is connected with the G1 of U5-I, MOD, CLK, TSTEN and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the MOD of U5-H, CLK, TSTEN is corresponding to be connected, Y0～Y7 of U5-I respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the EN of U5-H connects, AO[0]～AO[7] respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the TSTIN of U5-H connects, U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the OP of U5-H connects DOUT[0 respectively]～DOUT[7].
U5-A model: SB-PWM256, U5-B model: SB-PWM256,
U5-C model: SB-PWM256, U5-D model: SB-PWM256,
U5-E model: SB-PWM256, U5-F model: SB-PWM256,
U5-G model: SB-PWM256, U5-H model: SB-PWM256,
U5-I model: LS138
Output matrix circuit U5U6 uses pulse-width modulator U5-A～U5-H as grey level decoding and driving output.Data wire AO[0]～AO[7] connect the A[0 of U5-A～U5-H]～A[7], comparator base value holding wire W[0]～W[7] connect the B[0 of U5-A～U5-H]～B[7].The effect of 3/8 decoder U5-I is low 3 W[0 that utilize the comparator base value]～W[2] and SEL holding wire, respectively with data AO[0]～AO[7] send into decoder U5-A～U5-H.The MOD holding wire is connected to the MOD position of decoder U5-A～U5-H, and the output of control decoder produces 180 degree phase change.The effect of TSTEN holding wire is the production test of being convenient to scanning device.
By Fig. 1-B-A, delay control circuit U2-A is by 15ns delayer U2-D, U2-E, U2-F, U2-G, U2-H, 2 input XOR gate U2-10, U2-11, U2-12, U2-13, U2-14,3 inputs or door U2-15, U2-16,2 input NOR gate U2-17 connect to form.
1 end of C0 and U2-D, 2 ends of U2-10 connect, 2 ends of U2-D are connected with 1 end of U2-10,3 ends of C1 and U2-E, 2 ends of U2-11 connect, 4 ends of U2-E are connected with 1 end of U2-11,5 ends of C2 and U2-F, 2 ends of U2-12 connect, 6 ends of U2-F are connected with 1 end of U2-12,7 ends of C3 and U2-G, 2 ends of U2-13 connect, 8 ends of U2-G are connected with 1 end of U2-13,9 ends of C4 and U2-H, 2 ends of U2-14 connect, 10 ends of U2-H are connected with 1 end of U2-14,3 ends of U2-10 are connected with 1 end of U2-15, and 3 ends of U2-11 are connected with 2 ends of U2-15, and 3 ends of U2-12 are connected with 3 ends of U2-15,3 ends of U2-13 are connected with 1 end of U2-16,3 ends of U2-14 are connected with 2 ends of U2-16, the 3 end ground connection of U2-16, and 4 ends of U2-15 are connected with 1 end of U2-17,4 ends of U2-16 are connected with 2 ends of U2-17, and 3 ends of U2-17 are connected with CS.
U2-D model: SB-D15N, U2-E model: SB-D15N, U2-F model: SB-D15N,
U2-G model: SB-D15N, U2-H model: SB-D15N,
U2-10 model: XO02, U2-11 model: XO02, U2-12 model: XO02,
U2-13 model: XO02, U2-14 model: XO02,
U2-15 model: OR03, U2-16 model: OR03,
U2-17 model: NR02
By Fig. 1-B-B, add a circuit U 2-B by inverter U2-18, U2-19, U2-20,2 input XOR gate U2-21,2 inputs with or door U2-22, U2-23, U2-24,2 input nand gate U2-25, U2-26, U2-27 connect to form.
DI[0] with 1 end of U2-18,2 ends of U2-21,2 ends of U2-25 connect, DI[1] with 1 end of U2-21,1 end of U2-25 connects, DI[2] with 1 end of U2-22,1 end of U2-26 connects, DI[3] with 1 end of U2-23,2 ends of U2-27 connect, DI[4] be connected with 1 end of U2-24,3 ends of U2-25 and 2 ends of U2-22,1 end of U2-19 connects, 2 ends of U2-19 are connected with 2 ends of U2-26,3 ends of U2-26 and 2 ends of U2-23,1 end of U2-20 connects, 2 ends of U2-20 are connected with 1 end of U2-20,3 ends of U2-27 are connected with 2 ends of U2-24,2 ends and the DO[0 of U2-18] be connected 3 ends and the DO[1 of U2-21] be connected 3 ends and the DO[2 of U2-22] be connected, 3 ends and the DO[3 of U2-23] be connected 3 ends and the DO[4 of U2-24] be connected.
U2-18 model: IN01, U2-19 model: IN01, U2-20 model: IN01,
U2-21 model: XO02,
U2-22 model: XN02, U2-23 model: XN02, U2-24 model: XN02,
U2-25 model: NA02, U2-26 model: NA02, U2-27 model: NA02,
Compared with prior art, the scanning device of the storage of band image and grey level decoding output has following advantages:
1. memory data output is larger.
2. image shows more stable.
3. visual level is abundanter.
4. the dynamic scan scope is flexible.
5. structural design is simpler.

Claims (7)

  1. A kind of scanning device with Image storage and grey level decoding is characterized in that:
    1 scanning device is made up of six circuit units and external terminal.They are respectively: input control circuit unit U1, output control circuit unit U2, Image storage circuit unit U3, decoding correcting circuit unit U4, output matrix circuit unit U5U6; Input control pin WR, ADDR0, ADDR1, ID0, ID1, CS, HS, VS, output control pin ROW0～ROW4, ICLK, OPUL, OPULEN, data input pin D0～D7 proofreaies and correct base pin selection S0, S1, output pin DOUT0～DOUT15 and MOD, TSTEN
    The WR of U1, ADDR[0], ADDR[1], ID[0], ID[1], CS, HS, VS and the corresponding connection of input control pin, the SADDR[0 of U1]～SADDR[8] with the WA[0 of U3]～WA[8] corresponding connection, the WEN of U1 holds with the WEB of U3 and is connected,
    ROW0～ROW4 of U2, ICLK, OPUL, OPULEN and the corresponding connection of output control pin, the DEB[0 of U2]～DEB[4] with the RA[4 of U3]～RA[8] corresponding connection, the CO[0 of U2]～CO[3] with the RA[0 of U3]～RA[3] corresponding connection, the CO[0 of U2]～CO[7] with the W[0 of U5U6]～W[7] corresponding connection, the OCLK of U2 is connected with the CLK of U5U6, the A of U2 is connected with the SEL of U5, and the B of U2 is connected with the SEL of U6
    The WA[0 of U3]～WA[8] with RA[0]～RA[8] with outside U1, U2 are connected, DI[0]～DI[7] corresponding connection with the data input pin, the DO[0 of U3]～D0[7] with the DIN[0 of U4]～DIN[7] corresponding connection, the OEB of U3, REB ground connection,
    The DIN[0 of U4]～DIN[7] with outside U3 is connected, the corresponding connection of S0, S1, OUT[0 with the correction base pin selection]～OUT[7] with the AO[0 of U5U6]～AO[7] corresponding connection,
    The AO[0 of U5]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U5]～DOUT[7] corresponding connection with output pin DOUT0～DOUT7,
    The AO[0 of U6]～AO[7], W[0]～W[7], SEL, CLK be with outside U2, U4 are connected, the corresponding connection with pin MOD, TSTEN of MOD, TSTEN, the DOUT[0 of U6]～DOUT[7] corresponding connection with output pin DOUT8～DOUT15.
  2. 2 devices according to claim 1, it is characterized in that input control circuit unit U1 is by 5 parallel-by-bit counter U1-A, 6 parallel-by-bit counter U1-B, 4 inputs or door U1-1,3 inputs or door U1-2,2 inputs or door U1-3,2 inputs and door U1-4,2 input XOR gate U1-5, U1-6 connect to form
    WR is connected with 1 end of U1-1, ADDR[1], ID[1] with U1-5 1,2 ends connect respectively, 3 ends of U1-5 are connected with 1 end of U1-2, ADDR[0], ID[0] with U1-6 1,2 ends connect respectively, 3 ends of U1-6 are connected with 2 ends of U1-2, CS is connected with 3 ends of U1-2,4 ends of U1-2 are connected with 2 ends of U1-1, HS is connected with 1 end of U1-3, the Q[5 of U1-B] with 2 ends of U1-3,3 ends of U1-1 connect, 3 ends of U1-3 and 1 end of U1-4, the CLK of U1-B connects, 2 ends of VS and U1-4, the CDN of U1-B connects, and 3 ends of U1-4 are connected with the CDN of U1-A, the Q[4 of U1-A] be connected with 4 ends of U1-1,5 ends of U1-1 and the CLK of U1-A, WEN connects, the Q[0 of U1-A]～Q[3] with SADDR[0]～SADDR[3] corresponding connection, the Q[0 of U1-B]～Q[4] with SADDR[4]～SADDR[8] corresponding connection.
  3. 3 devices according to claim 1, the output control circuit unit U2 that it is characterized in that it is by delay control circuit U2-A, add a circuit U 2-B, 8 parallel-by-bit counter U2-C, inverse gate U2-1, U2-2, U2-3,2 inputs or door U2-4, U2-5, U2-6, U2-7,2 inputs and door U2-8,4 input nand gate U2-9 connect to form
    C0～C4 of ROW0～ROW4 and U2-A, the DI[0 of U2-B]～DI[4] the corresponding connection, the CS of U2-A is connected with 1 end of U2-4, OPUL is connected with 1 end of U2-5,1 end of OPULEN and U2-3,2 ends of U2-5 connect, 2 ends of U2-3 are connected with 2 ends of U2-4,3 ends of U2-4 are connected with 1 end of U2-8,3 ends of U2-5 are connected with 2 ends of U2-8,3 ends of U2-8 are connected with the CDN of U2-C, the CLK of ICLK and U2-C, OCLK connects, the Q[3 of U2-C] with 1 end of U2-1,1 end of U2-7 connects, the Q[4 of U2-C] be connected with 1 end of U2-2,2 ends of U2-2 are connected the Q[5 of U2-C with 1 end of U2-9], Q[6], Q[7] with U2-9 2,3,4 ends connect respectively, 5 ends of U2-9 and 2 ends of U2-6,2 ends of U2-7 connect, the DO[0 of U2-B]～DO[4] with DEB[0]～DEB[4] corresponding connection, the Q[0 of U2-C]～Q[7] with CO[0]～CO[7] corresponding connection, 3 ends of U2-8 are connected with B, 3 ends of U2-7 are connected with A.
  4. 4 devices according to claim 1, the correcting circuit unit U4 that it is characterized in that decoding are by 4/8 decoder U4-A, 5/8 decoder U4-B, and 6/8 decoder U4-C, two 4 select a device U4-D, U4-E, U4-F, U4-G to connect to form,
    DIN[0]～DIN[3] respectively with the IO[0 of U4-A]～IO[3] be connected, DIN[0]～DIN[4] respectively with the I1[0 of U4-B]～I1[4] be connected, DIN[0]～DIN[5] respectively with the I2[0 of U4-C]～I2[5] be connected, U4-D, U4-E, U4-F, the 1C0 of U4-G, the O0[7 of 2C0 and U4-A]～O0[0] corresponding connection, U4-D, U4-E, U4-F, the 1C1 of U4-G, the O1[7 of 2C1 and U4-B]～O1[0] corresponding connection, U4-D, U4-E, U4-F, the 1C2 of U4-G, the O2[7 of 2C2 and U4-C]～O2[0] corresponding connection, U4-D, U4-E, U4-F, the 1C3 of U4-G, 2C3 and DIN[7]～DIN[0] corresponding connection, S0, S1 respectively with U4-D, U4-E, U4-F, the A of U4-G, B connects, U4-D, U4-E, U4-F, the 1Y of U4-G, the corresponding respectively OUT[7 that connects of 2Y]～OUT[0], U4-D, U4-E, U4-F, the 1G of U4-G, 2G ground connection.
  5. 5 devices according to claim 1 is characterized in that output matrix circuit unit U5U6 uses pulse-width modulator U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, U5-H and 3/8 decoder U5-I to connect to form,
    AO[0]～AO[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the A[0 of U5-H]～A[7] the corresponding connection, W[0]～W[7] and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the B[0 of U5-H]～B[7] the corresponding connection, W[0]～W[2] with the A of U5-I, B, C is corresponding to be connected, SEL is connected with the G1 of U5-I, MOD, CLK, TSTEN and U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the MOD of U5-H, CLK, TSTEN is corresponding to be connected, Y0～Y7 of U5-I respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the EN of U5-H connects, AO[0]～AO[7] respectively with U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the TSTIN of U5-H connects, U5-A, U5-B, U5-C, U5-D, U5-E, U5-F, U5-G, the OP of U5-H connects DOUT[0 respectively]～DOUT[7].
  6. 6 devices according to claim 1, it is characterized in that delay control circuit U2-A is by 15ns delayer U2-D, U2-E, U2-F, U2-G, U2-H, 2 input XOR gate U2-10, U2-11, U2-12, U2-13, U2-14,3 inputs or door U2-15, U2-16,2 input NOR gate U2-17 connect to form
    1 end of C0 and U2-D, 2 ends of U2-10 connect, 2 ends of U2-D are connected with 1 end of U2-10,3 ends of C1 and U2-E, 2 ends of U2-11 connect, 4 ends of U2-E are connected with 1 end of U2-11,5 ends of C2 and U2-F, 2 ends of U2-12 connect, 6 ends of U2-F are connected with 1 end of U2-12,7 ends of C3 and U2-G, 2 ends of U2-13 connect, 8 ends of U2-G are connected with 1 end of U2-13,9 ends of C4 and U2-H, 2 ends of U2-14 connect, 10 ends of U2-H are connected with 1 end of U2-14,3 ends of U2-10 are connected with 1 end of U2-15, and 3 ends of U2-11 are connected with 2 ends of U2-15, and 3 ends of U2-12 are connected with 3 ends of U2-15,3 ends of U2-13 are connected with 1 end of U2-16,3 ends of U2-14 are connected with 2 ends of U2-16, the 3 end ground connection of U2-16, and 4 ends of U2-15 are connected with 1 end of U2-17,4 ends of U2-16 are connected with 2 ends of U2-17, and 3 ends of U2-17 are connected with CS.
  7. 7 devices according to claim 1, it is characterized in that adding a circuit U 2-B by inverter U2-18, U2-19, U2-20,2 input XOR gate U2-21,2 inputs with or door U2-22, U2-23, U2-24,2 input nand gate U2-25, U2-26, U2-27 connect to form
    DI[0] with 1 end of U2-18,2 ends of U2-21,2 ends of U2-25 connect, DI[1] with 1 end of U2-21,1 end of U2-25 connects, DI[2] with 1 end of U2-22,1 end of U2-26 connects, DI[3] with 1 end of U2-23,2 ends of U2-27 connect, DI[4] be connected with 1 end of U2-24,3 ends of U2-25 and 2 ends of U2-22,1 end of U2-19 connects, 2 ends of U2-19 are connected with 2 ends of U2-26,3 ends of U2-26 and 2 ends of U2-23,1 end of U2-20 connects, 2 ends of U2-20 are connected with 1 end of U2-20,3 ends of U2-27 are connected with 2 ends of U2-24,2 ends and the DO[0 of U2-18] be connected 3 ends and the DO[1 of U2-21] be connected 3 ends and the DO[2 of U2-22] be connected, 3 ends and the DO[3 of U2-23] be connected 3 ends and the DO[4 of U2-24] be connected.
CN 97111960 1997-07-08 1997-07-08 Scanning device with image storage and grey level decoding output Pending CN1204919A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930349A (en) * 2010-08-16 2010-12-29 深圳市洲明科技股份有限公司 Led scanning control chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930349A (en) * 2010-08-16 2010-12-29 深圳市洲明科技股份有限公司 Led scanning control chip
CN101930349B (en) * 2010-08-16 2012-01-11 深圳市洲明科技股份有限公司 Led scanning control chip

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