CN1204606C - Etching method for forming channel having high depth-width ratio - Google Patents
Etching method for forming channel having high depth-width ratio Download PDFInfo
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- CN1204606C CN1204606C CN 01142993 CN01142993A CN1204606C CN 1204606 C CN1204606 C CN 1204606C CN 01142993 CN01142993 CN 01142993 CN 01142993 A CN01142993 A CN 01142993A CN 1204606 C CN1204606 C CN 1204606C
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Abstract
The present invention discloses a novel an etching method for a groove with a high rate of depth to width, which comprises the following steps: firstly, a semiconductor substrate provided with a dielectric layer is provided; then, a light blocking layer is formed and delimited on the dielectric layer; a groove is formed in the dielectric layer by executing an etching step, and the etchant used in the etching step at least comprises mixed gas containing C4F6 or CH2F2, such as C4F6/CH2F2/Ar/O2, C4F6/CH2F2/Ar/O2/CF4, C4F6/CH2F2/Ar/O2/C2F6, etc. so as to increase the etching selection ratio of the dielectric layer to the light blocking layer and strengthen the etching capability of the etchant; finally, the light blocking layer is removed so as to form a contact window or a dielectric hole with an accurate critical dimension.
Description
Technical field
The relevant a kind of engraving method that forms semi-conductive groove of the present invention particularly has the interlayer hole of different form ratios and the engraving method of contact hole about a kind of formation.
Background technology
Along with the density of integrated circuit constantly enlarges, for making wafer (chip) area keep the same, even dwindle, to continue to reduce the unit cost of circuit, only way is exactly constantly to dwindle circuit design specification (designrule), to meet the high-tech industry developing tendency in future.Along with development of semiconductor, the size of component of integrated circuit has tapered to the scope of deep-sub-micrometer.When semiconductor continuously tapers to the scope of deep-sub-micrometer, some problems on microtechnology have been produced.
Dynamic random access memory is widely used in the field of integrated circuit circuit element, and wherein the application in electronics industry is the most important, and these elements provide the device of temporary transient storage data, are used in digital system usually, as computer.Possessing more, the dynamic random access memory of high density and electric capacity is the target that integrated circuit industry is made great efforts to develop always.Because the strong competition in dynamic random access memory market makes manufacturer be necessary to reduce its product price of dynamic random access memory.For reducing price and meeting the client for shortening the access time and increasing the expectation of integrated circuit memory amount of capacity, manufacturer must be devoted to dwindle the circuitous pattern size on the integrated circuit, and these circuitous patterns dwindle the progress that brings semiconductor technology.Yet the geometrical construction of dwindling brings some problems in the manufacturing of dynamic RAM circuit.Therefore, quality how to keep element under the situation of dynamic random access memory dimension reduction simultaneously is the problem that integrated circuit industry must overcome.
Because the integrated level of the semiconductor element of integrated circuit increases day by day, when making the surface of wafer can't provide enough areas to make required intraconnections, for gold conjugate oxide-semiconductor (Metal Oxide Semiconductor; MOS) transistor dwindles the intraconnections demand that increased of back, the mode of the two-layer above essential employing of metal level design just becoming gradually many integrated circuits institute.In addition, in the processing procedure of deep-sub-micrometer, because the integrated level of integrated circuit constantly increases, therefore adopt the comprehensive architecture of multiple layer inner connection line (Multi-level interconnects) at present mostly, and often with inner metal dielectric layer (Inter-Metal Dielectric; IMD) as the dielectric material of isolating each metal interconnecting.Wherein be used for connecting the lead of two metal layers up and down, on semi-conductor industry, be called interlayer hole connector (Via Plug).Usually the opening that forms in dielectric layer if expose base members in the intraconnections, then is referred to as contact hole (Contact hole).Therefore, be that metal plug by contact hole or interlayer hole electrically connects between the two-layer intraconnections.
Generally speaking, in the stack framework of dynamic random access memory, several dielectric layers 110 that have different levels on the semiconductor substrate 100, and several grids 120 are that several dielectric layers 110, several contact holes 130 of being arranged in different levels are positioned on several grids 120 and are positioned on the semiconductor substrate 100, shown in Figure 1A with several interlayer holes 140.Because the level difference at several grid 120 places, the degree of depth of several contact holes 130 are also different, and the degree of depth of several interlayer holes 140 is darker.In manufacture of semiconductor, that the ratio of groove width and its degree of depth (H/W) can claim usually is depth-to-width ratio (Aspect Ratio; AR).When depth-to-width ratio increases, promptly represent the increase of gash depth or the minimizing of groove width, this causes the etched difficulty of groove.For the deep-sub-micrometer processing procedure, design specification is more and more littler, makes element have the contact hole or the interlayer hole of high-aspect-ratio.Especially in dynamic random access memory, more and more be difficult to contact hole or interlayer hole that etching has high-aspect-ratio.In addition, when the depth-to-width ratio of contact hole more and more hour, the etch capabilities of interlayer hole with high-aspect-ratio is just more important.
In traditional engraving method, the etchant that is used for high-aspect-ratio is C
4F
8/ O
2/ Ar/CO.Yet, because therefore the etch capabilities deficiency of this kind etchant when carrying out the ditch trench etch of high-aspect-ratio, is not etched to desired depth as yet the phenomenon that etching stops can to take place, shown in Figure 1B.Especially the depth-to-width ratio of groove is greater than 10, and the phenomenon that etching stops is even more serious.In addition, traditional etchant has higher etching selectivity between different dielectric layer 110, for example, oxide layer and nitration case, therefore must replacing work board with the different dielectric layer 110 of eating thrown, and then expend the operating time.On the other hand, because traditional etchant is better than not to the selection of photoresist layer 150, cause the problem of the residual deficiency of photoresist layer 150, also promptly when carrying out etching, photoresist layer 150 can be depleted so that can't reach predetermined live width, causes the critical dimension of groove uncontrollable, shown in Fig. 1 C.In addition, when photoresist layer 150 consumed, still residual fraction photoresist layer 150 was on dielectric layer 110, and this will cause forming the palisade thing near the dielectric layer 110 of groove, shown in Fig. 1 D.For the dynamic random access memory of grid, be difficult to once etch interlayer hole and contact hole by traditional etchant with different form ratios with different levels.Traditional engraving method makes that not only reproducibility, acceptance rate and the productivity ratio of element are relatively poor, and increases process time, causes the increase of processing cost.
Summary of the invention
The main purpose of the present invention is that a kind of groove engraving method with high-aspect-ratio is being provided, so that form contact hole and interlayer hole with different high-aspect-ratios, thus simplify procedure of processing to reduce process time; In addition, can avoid causing the phenomenon of etch-stop to form the less semiconductor element of a critical dimension; Therefore in the technology applicable to the deep-sub-micrometer of semiconductor element.
For achieving the above object, the engraving method of dielectric layer according to an aspect of the present invention is characterized in comprising at least:
One etchant is provided, and described etchant is one to have a C
4F
6With a CH
2F
2Mist; And carry out etching and the described dielectric layer of etching by described etchant.
The formation method of groove according to a further aspect of the invention is characterized in comprising the following steps: to provide one to have the semiconductor substrate of a dielectric layer at least; Form a photoresist layer on described dielectric layer; One etchant is provided, and described etchant is one to have a C
4F
6With a CH
2F
2Mist; Carry out etching by described etchant and described photoresist layer as an etch mask, the described dielectric layer of etching is to form a groove, to improve the etching selectivity of described photoresist layer and described dielectric layer; And remove described photoresist layer has vertically profiling with formation described groove.
Formation method according to several grooves with different form ratios of another aspect of the invention, be characterized in comprising the following steps: at least to provide the semiconductor ground, several dielectric layers that have the stack structure on the described semiconductor substrate thereon, and in each described dielectric layer embedding at least one multi-crystal silicon area in wherein; Form several photoresist layers on the surface of described several dielectric layers; One etchant is provided, and described etchant is one to have a C
4F
6/ CH
2F
2/ Ar/O
2Mist; By described etchant and the engraving method that described several photoresist layers are carried out as several etch masks, described several dielectric layers of etching are up to forming several first grooves till on the described semiconductor substrate, and form several second grooves on described several multi-crystal silicon areas, to improve the etching selectivity of described several photoresist layers and described several dielectric layers; And remove described several photoresist layers have vertically profiling with formation described several first grooves and described several second grooves.
One interlayer hole of dynamic random access memory according to a further aspect of the present invention and the formation method of several contact holes, be characterized in, at least comprise the following steps: to provide the semiconductor ground, has one first oxide layer on the described semiconductor substrate thereon, one nitration case on described first oxide layer with one second oxide layer on described nitration case, wherein, one first multi-crystal silicon area is embedded in described first oxide layer on the described semiconductor substrate, and one second multi-crystal silicon area is embedded in the described nitration case on described first oxide layer with one the 3rd multi-crystal silicon area and is embedded in described second oxide layer on the described nitration case; Form several photoresist layers on described second oxide layer; One etchant is provided, and described etchant is one to have C
4F
6/ CH
2F
2/ CF
4/ Ar/O
2Mist; By described several photoresist layers are carried out dry ecthing as several etch masks and described etchant, described second oxide layer of etching in regular turn, described nitride layer and described first oxide layer up to form on the described semiconductor substrate that is positioned at described first multi-crystal silicon area and described second multi-crystal silicon area one have first groove of one first depth-to-width ratio till, and form one and have second groove of one second depth-to-width ratio on described first multi-crystal silicon area, one has the 3rd groove of one the 3rd depth-to-width ratio in having the 4th groove of one the 4th depth-to-width ratio on described the 3rd multi-crystal silicon area with one on described second multi-crystal silicon area; And remove described several photoresist layers have a vertically profiling with formation a interlayer hole in described first groove, one first contact hole in described second groove, one second contact hole in described the 3rd groove with one the 3rd contact hole in described the 4th groove.
The present invention can (for example increase the etching selectivity of dielectric layer and photoresist layer and the etching selectivity between the reduction dielectric layer by new etchant, between oxide layer and the nitration case), with the loss of avoiding photoresist layer too much with can an eating thrown dielectric layer, the critical dimension of groove and more straight groove contour can be kept whereby, and the formation of the palisade thing of dielectric layer can be prevented.In addition, the present invention uses and has C
4F
6Or CH
2F
2Or CF
4Or C
2F
6Mist as etchant, the etching selectivity that can improve dielectric layer and photoresist layer is to being about 15, and between the reduction dielectric layer etching selectivity of (for example, between oxide layer and the nitration case) to being about 1.Therefore, the present invention can reduce cost of processing, and can increase reproducibility, processing acceptance rate and the productivity ratio of element.So, the present invention can meet economically benefit and the usability on the industry.
Be clearer understanding above-mentioned and other purpose, characteristics and advantage of the present invention, the present invention is described in detail below in conjunction with accompanying drawing.
Description of drawings
Figure 1A is the stack section of structure of dynamic random access memory;
Figure 1B causes the profile of etch-stop phenomenon for the conventional groove engraving method;
Fig. 1 C causes the profile of the influence of the residual deficiency of photoresist layer for the conventional groove engraving method;
Fig. 1 D causes the profile of palisade thing for the conventional groove engraving method;
Fig. 2 A and Fig. 2 B are according in first preferred embodiment of the present invention, are etched with the processing profile that forms groove by new etchant;
Fig. 3 A and Fig. 3 B are according in second preferred embodiment of the present invention, once are etched with the processing profile that forms several grooves with different high-aspect-ratios by new etchant; With
Fig. 4 A and Fig. 4 B are according in the 3rd preferred embodiment of the present invention, carry out engraving method has the dynamic random access memory of several interlayer holes of different high-aspect-ratios and contact hole with formation processing profile by new etchant.
Embodiment
The present invention is a kind of groove engraving method with high-aspect-ratio in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step or element will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that skill person had the knack of of semiconductor element.On the other hand, well-known procedure of processing or element are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also be implemented among other the embodiment widely, and scope of the present invention do not limit by it, but is as the criterion with the scope of claim.
Shown in figure 2A and Fig. 2 B, in the first embodiment of the present invention, at first provide semiconductor ground 200, semiconductor substrate 200 has a dielectric layer 210 thereon.Then, form and limit a photoresist layer 220 on dielectric layer 210.Then, by photoresist layer 220 is carried out etching step 230 as an etch mask, etching dielectric layer 210 is to form a groove 240 in dielectric layer 210.Wherein above-mentioned etching step 230 employed etchants comprise having C at least
4F
6Or CH
2F
2Mist, whereby, can improve the etching selectivity of photoresist layer 220 and dielectric layer 210 so that after etching step 230 is finished, still can keep the profile of photoresist layer 220, and can avoid dielectric layer 210 to produce the palisade things.At last, remove photoresist layer 220 has vertically profiling with formation groove 240.
Shown in figure 3A and Fig. 3 B, in the second embodiment of the present invention, semiconductor ground 300 at first is provided, several dielectric layers 310 that have the stack structure on the described semiconductor substrate 300 thereon, and embedding at least one multi-crystal silicon area 320 is in wherein in each dielectric layer 310, wherein, described several dielectric layers 310 comprise monoxide layer and/or mononitride layer at least.Then, form and limit several photoresist layers 330 on the surface of several dielectric layers 310, to limit the zone that forms interlayer hole and contact hole.Then, by described several photoresist layers 330 are carried out dry etching steps 340 as several etch masks, described several dielectric layers 310 of etching are up to forming several interlayer holes 350 till on the described semiconductor substrate 300, and form several lead contact holes 360 on described several multi-crystal silicon areas 320, wherein, dry etching steps 340 employed etchants comprise having C at least
4F
6/ CH
2F
2Or C
4F
6/ CH
2F
2/ CF
4Or C
4 F6/ CH
2F
2/ C
2F
6Mist, whereby, can improve the etching selectivity of several photoresist layers 330 and several dielectric layers 310 so that after dry etching steps 340 is finished, still can keep the profile of photoresist layer 330, and can avoid several dielectric layers 310 to produce the palisade things.In addition, above-mentioned etchant (for example also can reduce on the multi-crystal silicon area 320 between the different dielectric layer, between oxide layer and the nitration case) etching selectivity, avoiding dry etching steps 340 can't etching to penetrate the phenomenon of the etch-stop that different dielectric layer 310 caused, thereby make lead contact hole 360 interrupt.In addition, several interlayer holes 350 comprise one at least approximately greater than 10 high-aspect-ratio.At last, remove several photoresist layers 330 have vertically profiling with formation several interlayer holes 350 and several lead contact holes 360.
Shown in figure 4A and Fig. 4 B, in the third embodiment of the present invention, semiconductor ground 400 at first is provided, has one first oxide layer 410A on the semiconductor substrate 400 in regular turn thereon, mononitride layer 420 in the first oxide layer 410A go up with one second oxide layer 410B on nitride layer 420, wherein, one first multi-crystal silicon area 430A is embedded among the first oxide layer 410A on the semiconductor substrate 400, and one second multi-crystal silicon area 430B is embedded in the nitride layer 420 on the first oxide layer 410A with one the 3rd multi-crystal silicon area 430C and is embedded among the second oxide layer 410B on the nitride layer 420.Then, form and limit several photoresist layers 440 on the second oxide layer 410B, to limit the zone that forms interlayer hole and contact hole.Then, by described several photoresist layers 440 are carried out dry etching steps 450 as several etch masks, the eating thrown second oxide layer 410B in regular turn, the nitride layer 420 and the first oxide layer 410A are up to forming an interlayer hole 460 till on the semiconductor substrate 400 that is positioned at the first multi-crystal silicon area 430A and the second multi-crystal silicon area 430B, and form one first contact hole 470A on the first multi-crystal silicon area 430A, one second contact hole 470B in the second multi-crystal silicon area 430B go up with one the 3rd contact hole 470C on the 3rd multi-crystal silicon area 430C, wherein, dry etching steps 450 employed etchants comprise having C at least
4F
6/ CH
2F
2/ Ar/O
2Or C
4F
6/ CH
2F
2/ Ar/O
2/ CF
4Or C
4F
6/ CH
2F
2/ Ar/O
2/ C
2F
6Mist, whereby, can improve the etching selectivity of several photoresist layers 440 and the second oxide layer 410B extremely approximately greater than 15, so that after dry etching steps 450 is finished, still can keep the profile of several photoresist layers 440, and can avoid the second oxide layer 410B to produce the palisade thing.In addition, above-mentioned etchant also can reduce etching selectivity between the first oxide layer 410A, the second oxide layer 410B and the nitride layer 420 to being about about 1, to avoid dry-etching method 450 that the phenomenon of etch-stop takes place, therefore can form groove by a dry etching steps 450 with different form ratios.In addition, the depth-to-width ratio of interlayer hole 460 is approximately greater than 10.At last, remove several photoresist layers 440 have vertically profiling with formation interlayer hole 460, the first contact hole 470A, the second contact hole 470B and the 3rd contact hole 470C.
As mentioned above, in an embodiment of the present invention, the present invention can carry out engraving method one time by new etchant, has the contact hole and the interlayer hole of different high-aspect-ratios so that form, and can simplify procedure of processing to reduce process time.In addition, etchant of the present invention is very strong for the etch capabilities of different dielectric layer, and this can be avoided causing the phenomenon of etch-stop, can form the less semiconductor element of a critical dimension whereby.Therefore, this method can be applicable in the technology of deep-sub-micrometer of semiconductor element.The present invention can increase the etching selectivity of dielectric layer and photoresist layer by new etchant, and is too much with the loss of avoiding photoresist layer, can keep the critical dimension of groove and more straight groove contour whereby, and can prevent the formation of the palisade thing of dielectric layer.In addition, the present invention uses and has C
4F
6Or CH
2F
2Mist as etchant, the etching selectivity that can improve dielectric layer and photoresist layer is to being about 15.Therefore, the present invention can reduce traditional processing cost, and can increase reproducibility, processing acceptance rate and the productivity ratio of element.So, the present invention can meet economically benefit and the usability on the industry.
Certainly, the present invention is except on the ditch trench etch that can be used on dynamic random access memory, also may be used in the formation of groove of any semiconductor element.And the present invention, still is used in so far and utilizes engraving method to have groove processing side's method of high-aspect-ratio with formation to avoid the phenomenon of etch-stop by new etchant.
Above-mentioned is preferred embodiment of the present invention only, is not in order to limit scope of patent protection of the present invention; All other do not break away from that the equivalence finished under the disclosed spirit changes or equivalence is replaced, and all should be included in the scope of patent protection that claims ask.
Claims (7)
1. the formation method with several grooves of different form ratios is characterized in that comprising the following steps: at least
The semiconductor ground is provided, several dielectric layers that have the stack structure on the described semiconductor substrate thereon, and in each described dielectric layer embedding at least one multi-crystal silicon area in wherein;
Form several photoresist layers on the surface of described several dielectric layers;
One etchant is provided, and described etchant is one to have-C
4F
6/ CH
2F
2/ Ar/O
2Mist;
By described etchant and the engraving method that described several photoresist layers are carried out as several etch masks, described several dielectric layers of etching are up to forming several first grooves till on the described semiconductor substrate, and form several second grooves on described several multi-crystal silicon areas; And
Remove described several photoresist layers have vertically profiling with formation described several second grooves and described several second grooves.
2. the formation method of several grooves as claimed in claim 1 is characterized in that, described etchant comprises having C at least
4F
6/ CH
2F
2/ CF
4/ Ar/O
2Mist.
3. the formation method of several grooves as claimed in claim 1 is characterized in that, described etchant comprises having C at least
4F
6/ CH
2F
2/ C
2F
6/ Ar/O
2Mist.
4. the formation method of several grooves as claimed in claim 1 is characterized in that, the etching selectivity of described several photoresist layers and described several dielectric layers is greater than 15.
5. the formation method of an interlayer hole of a dynamic random access memory and several contact holes is characterized in that, comprises the following steps: at least
The semiconductor ground is provided, have on the described semiconductor substrate one first oxide layer thereon, a nitration case on described first oxide layer with one second oxide layer on described nitration case, wherein, one first multi-crystal silicon area is embedded in described first oxide layer on the described semiconductor substrate, and one second multi-crystal silicon area is embedded in the described nitration case on described first oxide layer with one the 3rd multi-crystal silicon area and is embedded in described second oxide layer on the described nitration case;
Form several photoresist layers on described second oxide layer;
One etchant is provided, and described etchant is one to have C
4F
6/ CH
2F
2/ CF
4/ Ar/O
2Mist;
By described several photoresist layers are carried out dry ecthing as several etch masks and described etchant, described second oxide layer of etching in regular turn, described nitride layer and described first oxide layer up to form on the described semiconductor substrate that is positioned at described first multi-crystal silicon area and described second multi-crystal silicon area one have first groove of one first depth-to-width ratio till, and form one and have second groove of one second depth-to-width ratio on described first multi-crystal silicon area, one has the 3rd groove of one the 3rd depth-to-width ratio in having the 4th groove of one the 4th depth-to-width ratio on described the 3rd multi-crystal silicon area with one on described second multi-crystal silicon area; And
Remove described several photoresist layers have a vertically profiling with formation a interlayer hole in described first groove, one first contact hole in described second groove, one second contact hole in described the 3rd groove with one the 3rd contact hole in described the 4th groove.
6. the formation method of an interlayer hole of dynamic random access memory as claimed in claim 5 and several contact holes is characterized in that, the etching selectivity of described several photoresist layers and described second oxide layer is greater than 15.
7. the formation method of an interlayer hole of dynamic random access memory as claimed in claim 5 and several contact holes is characterized in that, described first oxide layer, described nitration case and described second oxide layer etching selectivity each other are 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01142993 CN1204606C (en) | 2001-12-04 | 2001-12-04 | Etching method for forming channel having high depth-width ratio |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01142993 CN1204606C (en) | 2001-12-04 | 2001-12-04 | Etching method for forming channel having high depth-width ratio |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1423310A CN1423310A (en) | 2003-06-11 |
| CN1204606C true CN1204606C (en) | 2005-06-01 |
Family
ID=4677015
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01142993 Expired - Lifetime CN1204606C (en) | 2001-12-04 | 2001-12-04 | Etching method for forming channel having high depth-width ratio |
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| CN (1) | CN1204606C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| CN100452317C (en) * | 2005-09-09 | 2009-01-14 | 联华电子股份有限公司 | Method for reducing feature size and semi-conductor etching method |
| CN101211932B (en) * | 2006-12-27 | 2010-05-12 | 日月光半导体制造股份有限公司 | Method for manufacturing image sensing subassembly wafer-grade packaging structure |
| JP5719648B2 (en) * | 2011-03-14 | 2015-05-20 | 東京エレクトロン株式会社 | Etching method and etching apparatus |
-
2001
- 2001-12-04 CN CN 01142993 patent/CN1204606C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
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| Publication number | Publication date |
|---|---|
| CN1423310A (en) | 2003-06-11 |
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