CN1195884A - 利用平面化技术制造半导体器件的方法 - Google Patents

利用平面化技术制造半导体器件的方法 Download PDF

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CN1195884A
CN1195884A CN98101226A CN98101226A CN1195884A CN 1195884 A CN1195884 A CN 1195884A CN 98101226 A CN98101226 A CN 98101226A CN 98101226 A CN98101226 A CN 98101226A CN 1195884 A CN1195884 A CN 1195884A
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石川拓
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

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Abstract

一种制造半导体器件的方法,包括:在晶体管元件上形成氮化膜、BPSG膜和含硼或磷的SOG氧化硅膜;在加压蒸汽气氛中热处理所得晶片;并在惰性气体气氛中热处理该晶片。第一热处理引起SOG膜的水解作用,形成凝胶态SOG膜,而第二热处理通过去掉SOG膜中所含水分固化SOG膜。SOG膜中的磷或硼减弱了SOG膜中-Si-O-Si-链中的结合键,帮助-Si-O-Si-链的分离,及SOG膜的平面化。

Description

利用平面化技术制造半导体器件的方法
本发明涉及一种制造半导体器件的方法,特别涉及层间介质层的平面化技术。
随着半导体器件集成度和速度的提高,器件中的每个元件都要由更精细的图形构成。为获得更精细图形,目前的光刻技术要求晶体管元件和叠加的层间介质膜的平面度或平坦度更高。现有光刻技术的例子包括化学机械抛光(CMP),然而,该技术会导致半导体器件的制造成本增加,并且由于要抛光的层间介质膜的图形所限只能获得受限制的形貌。
日本特许公开JP-A-7-37879提出了一种半导体衬底上旋涂氧化硅形成的旋涂玻璃(SOG)膜的平面化技术,该技术利用低温回流技术,并在利用在蒸汽气氛中热氧化SOG膜提高了质量等效于BPSG(硼磷硅玻璃)的SOG氧化硅膜的质量后进行。
然而,该技术涉及SOG膜自身的固化,这会影响它的有效平面化。
W.Dauksher等人发表于1992年的《电化学学报》上的文章“Three“Low Dt”Option for Planarizing the Pre-metal Dielectric on anAdvanced Double Poly BiCMOS Process”描述了一种平面化技术,为了进行平面化,该技术在蒸汽气氛中热处理形成于晶体管元件上含有硼和磷的BPSG,以回流BPSG膜。
由于BPSG的熔点很高,所以,在蒸汽气氛中热处理BPSG膜的技术要求热处理的温度高达约800℃,以获得充分的平面化,但是这个温度会影响先前步骤中形成的扩散层的性质,进而造成晶体管特性的退化。
因此,本发明的目的是提供一种新颖且有效的半导体器件层间介质膜的平面化技术。
本发明提供一种制造半导体器件的方法,该方法包括以下步骤:在半导体衬底上依次形成半导体元件、第一绝缘膜、含磷和硼的第二绝缘膜、及至少含磷和硼之一的旋涂玻璃(SOG)第三绝缘膜,从而获得第一晶片;在加压蒸汽气氛中热处理该第一晶片;在惰性气体气氛中热处理该第一晶片;在第三绝缘膜上形成互连层。
根据本发明,第三绝缘膜中的磷或硼的作用是减弱第三绝缘膜中的结合键,以便在水解期间弱化的键由于加压蒸汽气氛中的热处理而分离,从而帮助第三绝缘膜的平面化。在惰性气体气氛中的热处理通过去掉第三绝缘膜中的水分使第三绝缘膜固化,这些水分是在先前的热氧化中引入的。
参考附图,通过以下的说明将更清楚本发明的上述和其它目的、特点及优点。
图1A-1E是根据本发明实施例的处于各顺序制造步骤的半导体器件的剖面图;
图2是展示SOG膜的平整度与包括热处理温度和气氛压力等的热处理条件的关系的曲线图;
图3A-3E是根据本发明第二实施例的处于各顺序制造步骤的半导体器件的剖面图。
下面参照附图详细说明本发明,其中类似的构件用相同或相关的参考数字表示。
图1A-1E展示了根据本发明第-实施例的处于各顺序制造步骤的半导体器件。参见图1A,在硅衬底11上形成MOSFET 17,该MOSFET具有栅绝缘膜12、与侧壁膜14相连的栅极13、及与轻掺杂漏(LDD)区15相连的源/漏区16。然后,在常压气氛中进行化学汽相淀积(CVD),在其上形成氧化硅膜18,随后于其上淀积氮化硅膜19,后者用作使晶体管17防水或水汽的保护层。氮化硅膜19的厚度为50-200埃便足够。
然后,在氮化硅膜19上形成合适厚度的由含硼和磷的氧化膜构成的BPSG膜20,如图1B所示,然后,在合适的温度下进行热处理,以使BPSG膜20稳定。BPSG膜20的厚度根据半导体器件的设计选择。随后,在BPSG膜20上旋涂形成SOG氧化硅膜21,如图1C所示。SOG膜21由至少含磷和硼中一种的氧化硅构成,磷和硼的作用是帮助平面化。然后,在如氮或氩气氛等惰性气体气氛中,在约200℃-约300℃的温度下,进行热处理,以去掉SOG膜21中的溶剂。
然后,在加压蒸汽气氛中对所得晶片进行另一热处理。加压蒸汽气氛中的热处理使得SOG膜21发生水解,其中,在蒸汽气氛中,SOG膜21中包括Si-O-Si-链的弱网状结构分子被H2O分子分离,与H2O分子发生反应,形成包括-Si-OH链的分子和包括HO-Si-链的分子。这样从弱结合结构上分离的SOG膜21改变为有塑性的凝胶态。SOG膜21中的磷或硼减弱了-Si-O-Si-链中的结合键。另外,加于凝胶SOG膜21上的高压平面化了SOG膜21,如图1D所示。
图2是展示SOG膜的平整度与包括热处理温度和气氛压力等的热处理条件的关系的曲线图。该图中,阴影区对应于所得器件中满足晶体管特性的极好SOG膜21平整度的情况。较高的压力可以提供实现极好平整度的合适低温条件,而在较低的压力下温度必须较高。此外,较高的温度提供较高压力下的更合适条件。
此后,用例如氮气等加压惰性气体作为进一步热处理的气氛,以固化平面化的SOG膜。热处理温度可以等于或高于加压蒸汽气气氛中热处理所用的温度,从而基本上完全去掉SOG膜21中的水分。在惰性气氛中的热处理之后,可以通过例如利用干法腐蚀技术的深腐蚀步骤调节SOG膜21(或SOG膜21/BPSG膜20)的厚度。SOG膜21的平面化表面能够在随后的制造金属塞22和金属互连13的光刻工艺步骤中进行精确构图,如图1E所示。
参见图3A-3E,这些图展示了根据本发明第二实施例的制造半导体器件的方法。图3A中,与第一实施例类似,形成MOSFET 17,然后,CVD形成氧化硅膜18。并在其上CVD淀积氮化硅膜19,然后CVD形成另一氧化硅膜20A,如图3B所示。氧化硅膜20A的厚度根据半导体器件的设计选择。
然后,在氧化硅膜20A上旋涂形成SOG膜21,并在例如氮或氩气体等惰性气体气氛中,在约200℃-约300℃的温度下对该膜进行热处理,从而去掉SOG膜21中的溶剂。然后对SOG膜21进行磷或硼离子注入,以提高SOG膜21的平面化性能。调节杂质离子的加速能量,以便SOG膜21中杂质的分布为在SOG膜21的表面区杂质浓度较高。
随后,与第一实施例类似,在加压蒸汽气氛中进行热处理,由此通过水解分离SOG膜21中弱结合的包括-Si-O-Si-链的网状结构的分子,以便与H2O反应,形成包括-Si-OH链的分子和包括HO-Si-链的分子。分离的SOG膜21改变为具有塑性的凝胶态。由于-Si-O-Si-链中弱结合键的缘故,SOG膜21中的磷或硼加速了SOG膜21向凝胶态的转变。另外,作用于SOG膜21自身的高压加速了凝胶SOG膜21的平面化。
然后,通过在如氮或氩气体气氛等惰性气体气氛中进一步热处理,固化这种平面化的凝胶SOG膜21。在惰性气氛中热处理过程的温度等于或高于先前在加压蒸汽气氛中的热处理温度,由此基本上完全去掉了SOG膜21中的水分。热处理后,通过利用干法腐蚀技术的深腐蚀工艺,调节SOG膜21的厚度。平面化的SOG膜21可以在随后的制造金属塞22和金属互连13的光刻步骤中精确地构图,如图3E所示。
本发明的实验表明,蒸汽气氛或惰性气体气氛的压力应在约5个大气压以上,热处理应在400℃和700℃之间的温度下进行约1-2小时,以实现合适的产量。惰性气体可以是氮、如氩等稀有气体中的一种或几种、或一种或几种稀有气体与氧的混合气。
尽管示例性地介绍了上述实施例,但本发明并不限于上述实施例,本领域的技术人员容易在本发明范围内进行各种改或替换。

Claims (5)

1.一种制造半导体器件的方法,包括以下步骤:在半导体衬底上依次形成半导体元件、第一绝缘膜、含磷和硼的第二绝缘膜、及至少含磷和硼之一的旋涂玻璃(SOG)第三绝缘膜,从而获得第一晶片;在加压的蒸汽气氛中热处理该第一晶片;在惰性气体气氛中热处理该第一晶片;在第三绝缘膜上形成互连层。
2.根据权利要求1的方法,其特征在于,第二绝缘膜由硼磷硅玻璃构成。
3.根据权利要求1的方法,其特征在于,第三绝缘膜由氧化硅构成。
4.根据权利要求1的方法,其特征在于,第一绝缘膜由氮化硅构成。
5.根据权利要求1的方法,其特征在于,在约5个大气压以上的压力和400℃-700℃的温度下进行加压蒸汽气氛中的热处理。
CN98101226A 1997-03-31 1998-03-30 利用平面化技术制造半导体器件的方法 Expired - Fee Related CN1122301C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100444331C (zh) * 2003-11-11 2008-12-17 三星电子株式会社 旋涂玻璃组合物和在半导体制造工序中使用该旋涂玻璃形成氧化硅层的方法

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3245136B2 (ja) * 1999-09-01 2002-01-07 キヤノン販売株式会社 絶縁膜の膜質改善方法
KR100611389B1 (ko) * 2000-06-29 2006-08-11 주식회사 하이닉스반도체 게이트산화막의 형성방법
KR100769206B1 (ko) * 2001-12-28 2007-10-23 매그나칩 반도체 유한회사 반도체 소자의 평탄화 방법
JP4582452B2 (ja) * 2004-03-16 2010-11-17 株式会社Ihi 半導体装置の製造方法
US7645677B2 (en) 2004-03-16 2010-01-12 Ishikawajima-Harima Heavy Industries Co., Ltd. Method for manufacturing semiconductor device
KR100593673B1 (ko) * 2004-10-27 2006-06-28 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 이용한 반도체 장치의 소자 분리막 제조 방법
CN100449888C (zh) * 2005-07-29 2009-01-07 日亚化学工业株式会社 半导体激光元件
KR100720509B1 (ko) * 2005-11-10 2007-05-22 동부일렉트로닉스 주식회사 이미지 센서 및 이의 제조 방법
WO2013066977A1 (en) * 2011-10-31 2013-05-10 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization
US9418963B2 (en) 2012-09-25 2016-08-16 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Methods for wafer bonding, and for nucleating bonding nanophases
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
JP6947914B2 (ja) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 高圧高温下のアニールチャンバ
KR102396319B1 (ko) 2017-11-11 2022-05-09 마이크로머티어리얼즈 엘엘씨 고압 프로세싱 챔버를 위한 가스 전달 시스템
KR20200075892A (ko) 2017-11-17 2020-06-26 어플라이드 머티어리얼스, 인코포레이티드 고압 처리 시스템을 위한 컨덴서 시스템
KR102539390B1 (ko) * 2018-02-22 2023-06-05 어플라이드 머티어리얼스, 인코포레이티드 더 양호한 막 품질을 가능하게 하기 위해 마스크 기판을 처리하기 위한 방법
US11114333B2 (en) 2018-02-22 2021-09-07 Micromaterials, LLC Method for depositing and reflow of a high quality etch resistant gapfill dielectric film
JP7239598B2 (ja) 2018-03-09 2023-03-14 アプライド マテリアルズ インコーポレイテッド 金属含有材料の高圧アニーリングプロセス
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455325A (en) * 1981-03-16 1984-06-19 Fairchild Camera And Instrument Corporation Method of inducing flow or densification of phosphosilicate glass for integrated circuits
US4420503A (en) * 1982-05-17 1983-12-13 Rca Corporation Low temperature elevated pressure glass flow/re-flow process
JPH0669039B2 (ja) * 1985-04-12 1994-08-31 株式会社リコー 半導体装置の製造方法
JPS63198359A (ja) * 1987-02-13 1988-08-17 Fujitsu Ltd 半導体装置の製造方法
JPH03288437A (ja) * 1990-04-04 1991-12-18 Seiko Instr Inc 半導体装置の製造方法
JPH0456221A (ja) 1990-06-25 1992-02-24 Matsushita Electron Corp 回転塗布方法および回転塗布装置
EP0540833B1 (de) * 1991-08-12 1997-04-23 KOENIG & BAUER-ALBERT AKTIENGESELLSCHAFT Qualitätskontrolle einer Bildvorlage z. B. eines gedruckten Musters
JP3064575B2 (ja) * 1991-09-27 2000-07-12 ヤマハ株式会社 多層配線形成法
JP2792335B2 (ja) 1992-05-27 1998-09-03 日本電気株式会社 半導体装置の製造方法
JPH0684901A (ja) * 1992-08-31 1994-03-25 Kawasaki Steel Corp 半導体装置の製造方法
JPH0737879A (ja) 1993-07-19 1995-02-07 Nippon Steel Corp 半導体装置の製造方法
US5409858A (en) * 1993-08-06 1995-04-25 Micron Semiconductor, Inc. Method for optimizing thermal budgets in fabricating semiconductors
JPH07183375A (ja) * 1993-12-22 1995-07-21 Kawasaki Steel Corp 層間絶縁膜の形成方法
US5679610A (en) * 1994-12-15 1997-10-21 Kabushiki Kaisha Toshiba Method of planarizing a semiconductor workpiece surface
US5801076A (en) * 1995-02-21 1998-09-01 Advanced Micro Devices, Inc. Method of making non-volatile memory device having a floating gate with enhanced charge retention
JPH08321609A (ja) * 1995-05-26 1996-12-03 Sanyo Electric Co Ltd 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100444331C (zh) * 2003-11-11 2008-12-17 三星电子株式会社 旋涂玻璃组合物和在半导体制造工序中使用该旋涂玻璃形成氧化硅层的方法

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