CN118316458A - High speed 10:1 parallel-serial conversion circuit - Google Patents

Abstract

The invention discloses a high-speed 10: the parallel-serial conversion circuit 1 belongs to the field of parallel-serial conversion and comprises a clock frequency division module, a low-speed parallel-serial conversion module and a 4:1 parallel-serial conversion module; the clock frequency dividing module is connected with an initial four-phase clock, and divides the frequency of the initial clock for multiple times through frequency dividers with different frequency dividing ratios to obtain clocks with different frequencies and 20bit multiphase clocks needed by the low-speed parallel-serial conversion module circuit; the low-speed parallel-serial conversion module is connected with 10-bit parallel 0.1N Gbps data, a 0.5N GHz four-phase single-ended clock and a 0.05NGHz 20bit single-ended multiphase clock, and realizes parallel-serial conversion of the 10-bit parallel data under the control of the clock to obtain 4-bit parallel differential CMOS data; the data bit of the 4:1 parallel-serial conversion module is connected with 4-bit parallel differential data output by the first-level low-speed parallel-serial conversion module, and the sampling clock is a four-phase clock of 0.25N GHz and a differential clock of 0.5N GHz; and the 4:1 parallel-serial conversion module converts the 4-bit parallel differential data into 1-bit parallel differential signals under the control of the clocks with different frequencies.

Description

High speed 10:1 parallel-serial conversion circuit

Technical Field

The invention relates to the technical field of parallel-serial conversion, in particular to a high-speed 10: and 1a parallel-serial conversion circuit.

Background

Parallel-serial conversion technology is widely applied to the field of high-speed data transmission. The transmission mode is to serialize multiple parallel low-speed data, convert the data into a high-speed signal and transmit the signal in a channel. Compared with parallel transmission, the number of transmission IO can be greatly reduced, and the data transmission efficiency is effectively improved.

The conventional parallel-to-serial conversion circuit is mainly divided into serial, parallel and tree structures. The serial architecture usually consists of a set of D flip-flops that are combined in and out into a shift register, and all devices of this architecture need to operate at full speed, so the circuit power consumption is high.

The parallel structure adopts a multiphase clock to sample a plurality of parallel data simultaneously, for example, parallel-serial conversion is performed to N paths of parallel data and 1 path of serial data, and N duty ratios are required to be 1: the phase clock of (N-1) selectively turns on each path of data. This structure, although consuming less power, requires strict phase accuracy for clock and data and is not suitable for high-speed systems.

The tree structure refers to that each level adopts 2 paths of 2:1MUX, stepwise implementing 2 ^N: 1. The tree structure has lower requirement on the high-frequency clock than other two structures, has moderate design difficulty and power consumption, but the structural layout occupies larger area, is only suitable for processing 2 ^N paths of parallel input data, and can be used only by converting 10 bits of parallel data into 2 ^N parallel data for a 10-path parallel-serial conversion circuit.

Disclosure of Invention

The invention aims to provide a high-speed 10:1 parallel-serial conversion circuit to solve the problems in the background art.

In order to solve the technical problems, the invention provides a high-speed 10: a parallel-to-serial conversion circuit comprising:

The clock frequency division module is connected with the initial four-phase clock, and divides the frequency of the initial clock for multiple times through frequency dividers with different frequency division ratios to obtain clocks with different frequencies and 20-bit multiphase clocks needed by the low-speed parallel-serial conversion module circuit;

The low-speed parallel-serial conversion module is connected with 10-bit parallel 0.1N Gbps data, a 0.5N GHz four-phase single-ended clock and a 0.05N GHz 20-bit single-ended multiphase clock, and realizes parallel-serial conversion of the 10-bit parallel data under the control of the clock to obtain 4-bit parallel differential CMOS data;

The 4:1 parallel-serial conversion module is used for receiving the 4-bit parallel differential data output by the first-level low-speed parallel-serial conversion module, and the sampling clock is a four-phase clock of 0.25N GHz and a differential clock of 0.5N GHz; and the 4:1 parallel-serial conversion module converts the 4-bit parallel differential data into 1-bit parallel differential signals under the control of the clocks with different frequencies.

In one embodiment, the clock frequency division module comprises a latch array, a multi-stage frequency division circuit, a multi-phase frequency division circuit and a delay array unit, and generates clocks with different frequencies and different phases, wherein the frequency of the 20bit multi-phase clock is 0.05 times of the highest serial data, and the duty ratio of the low level in the multi-phase clock is 1:20; the clock signal generating circuit with the 1:20 duty ratio mainly comprises a NAND gate and a clock selection inverter logic, the transistor size of the D flip-flops is adjusted, so that the device fixed delay of each D flip-flop is 1/20 of the multiphase clock, and the 20-bit multiphase clock is finally generated through resampling and delay of a primary stage.

In one embodiment, the 20bit multiphase clock is divided into 4 groups for sampling by a low-speed parallel-serial circuit, each parallel-serial conversion is to obtain 10-bit data with a data rate of 0.1N Gbps, namely 20-bit 0.05N Gbps data, and each bit of data is selectively conducted by a clock selection inverter after being sampled by 2 or more D flip-flops; the type of the D trigger is the same, only the sampling clocks are different, the sampling clocks are alternately 0.05N GHz differential clocks, the differential data with the 4bit data rate of 0.25N Gbps is output, and the conversion from non-2 ^N data to 2 ^N data is realized.

In one embodiment, the output of the low-speed parallel-to-serial conversion module is connected to the output of the 4: the 1 parallel-serial conversion module realizes the conversion from data to 2 ^N bits;

The 4: the 1 parallel-serial conversion module mainly comprises 3 MUX2:1 circuits and 2D triggers, wherein data bits in the two MUX2:1 circuits of the first stage are respectively connected with the 0 th bit, the 2 nd bit, the 1 st bit and the 3 rd bit of the low-speed parallel-serial conversion module of the previous stage; and then the input end of the second stage MUX2:1 is connected with the output ends of the 2D triggers through the sampling unified time sequence of the D triggers, and finally, the high-speed serialization of signals is realized.

In one embodiment, the 4:1 parallel to serial conversion module is connected with an external interface circuit through an additional output driving module after high-speed serialization is realized.

In one embodiment, the 4:1 parallel to serial conversion module is typically in a tree structure.

The invention provides a high-speed 10: and the parallel-serial conversion circuit converts multiple paths of low-speed parallel data into one path of high-speed serial data by adopting a mode of combining a parallel structure and a tree structure. Compared with the traditional parallel and tree-shaped structures, the novel architecture provided by the invention not only reduces the highest frequency clock required by the parallel-serial conversion circuit to 1/2 of the original clock, but also achieves the effect of reducing the circuit power consumption by adopting the mode of processing high-speed data by adopting the low frequency clock, thereby greatly improving the processing capacity of parallel data, simultaneously reducing the design difficulty on the whole and saving the whole layout area. In addition, the final stage 2:1 tree type MUX circuit can be designed by adopting an analog circuit structure according to specific requirements, and various bandwidth expansion technologies can be flexibly adopted to meet the requirements of an integral parallel-serial conversion system.

Drawings

Fig. 1 shows a high speed 10 according to the present invention: 1 parallel-serial conversion circuit structure block diagram.

FIG. 2 is a simplified block diagram of a 20bit multi-phase clock generation circuit in a clock divider module according to the present invention.

Fig. 3 is a simplified block diagram of a low-speed parallel-serial conversion circuit according to the present invention.

Fig. 4 is a simplified timing diagram of a low-speed parallel-serial conversion circuit according to the present invention.

Fig. 5 shows a diagram of the present invention 4:1 parallel-serial conversion circuit structure block diagram.

Fig. 6 shows a diagram of the present invention 4: 1a simplified timing diagram of a parallel to serial conversion circuit.

Detailed Description

The following presents a high speed 10 in connection with the drawings and the specific embodiments: the 1 parallel to serial conversion circuit is described in further detail. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention proposes a high speed 10: the 1 parallel-serial conversion circuit has a structure shown in fig. 1 and comprises a clock frequency division module, a low-speed parallel-serial conversion module, a 4:1 parallel-serial conversion module and an output driving module. The serial high-speed signal rate of the output is set to N Gbp/s in this example, and thus the data rate corresponding to the input 10-bit parallel data is 0.1N Gbp/s. The input clock of the clock frequency division module is a four-phase clock of 0.5N GHz, which is CLK0, CLK0N, CLK1 and CLK1N respectively. The clock frequency division module provides clocks with different frequencies and phases for the whole parallel-serial conversion circuit. The clocks required by the low-speed parallel-serial conversion module comprise 0.05N GHz multiphase clocks CLKS <19:0>, and 0.05N GHz clocks CLKM and 0.25N GHz CLKQ<3:0> with a duty cycle of 50%. The clock dividing module is thus composed of a plurality of frequency dividers of different dividing ratios. For a low-speed parallel-serial conversion circuit, a first stage of 10-bit 0.1N Gbps data is sampled by a 0.05N GHz multiphase clock, and two columns of 10-bit input data are extracted when sampling is actually performed, namely, the extracted 20-bit 0.1N Gbps input data are subjected to parallel-serial conversion processing. The 20-bit multiphase clock is divided into 4 groups, 20-bit data are sampled in sequence, each group contains 5-bit data, and the 5:1 data conversion of each group is realized by sequentially gating at different moments, namely, the 4 groups of data integrally realize 10:4 parallel-serial conversion.

The 4:1 parallel-serial conversion circuit adopts a tree structure, and comprises 3 2:1 is formed by MUX circuits. And the clock signals of the 4:1 parallel-serial conversion circuit are 0.25N GHz CLKQ<3:0> and a differential clock CLKP/CLKN of 0.5 GHz. After the 4:1 parallel-serial conversion circuit, the method is actually completed by 10:1, and most of the output signals are CMOS signals. Considering that high speed serial typically uses a standard interface to communicate externally, the final stage of the transmitter circuit that is typically completed is an analog high speed drive circuit. On one hand, the driving circuit needs to carry out port matching according to an interface protocol standard to determine an output amplitude range; on the other hand, considering the attenuation and other reasons such as channel bandwidth, the drive circuit often adopts a configurable bandwidth expansion or equalization structure, so that the high-speed signal still has high bandwidth after passing through the channel, and the error rate of the whole data transmission is ensured. The implementation manner of the high-speed driving circuit is various, and the specific explanation is omitted in the example, and only the 10:1 parallel-serial conversion logic is analyzed in detail.

In the clock frequency division module shown in fig. 1, the multiphase clock generation circuit is mainly generated by a five-frequency division circuit, a2 nd frequency division circuit and a delay unit. Fig. 2 is a simplified block diagram of a 20bit multiphase clock generation circuit in a clock divider module. Wherein CLKQ <3:0> in FIG. 2 is the 0.25N GHz clock signal generated by the clock divider module in FIG. 1, which are 90 ° out of phase with each other. I9-I12 are 4 identical buffers, so XX 0-XX 3 is also a 0.25N GHz clock signal with a phase difference of 90 degrees. CLKIN1 is a 50% 0.05N GHz clock signal divided multiple times, and CLKIN2 is a 0.1N GHz clock signal having a duty cycle of 40%. The clock signal after the two signals pass through the first NAND gate I0 is a 0.05N GHz clock with a duty cycle of 20%. I2 is a clocked inverter, which is turned on only at the low level of the XX0 clock, and the high level is turned off to keep the signal at the same low level. In this module, the reset signal RST is reset at a low level at the time of start-up, and the RST signal is set to "1" at the time of normal operation. In effect, through I1 and I2, the net01 node signal is still a 0.05N GHz clock with a 20% duty cycle. Similarly, under the gating of clock signals XX1, XX2, XX3, net01, net02, net03 and net04 signals are still 0.05N GHz clocks with a duty cycle of 20% and are N GHz clock cycles out of phase with each other. To align the timing strictly, net01, net02, net03 and net04 are sampled a second time to get S <3:0>, with a phase difference of N GHz clock cycles from each other. The D flip-flop is properly sized so that the fixed delay of the device is also N GHz clock cycles, thereby realizing a 20bit multi-phase clock.

As can be seen from fig. 1, the multiphase clocks are divided into 4 groups in total, and are grouped in the following order according to the delay of the clocks: the first group contains clocks CLKS <0>, CLKS <4>, CLKS <8>, CLKS <12>, CLKS <16>, respectively; the second set of clocks are CLKS <1>, CLKS <5>, CLKS <9>, CLKS <13>, CLKS <17>, respectively; the third set of clocks are CLKS <2>, CLKS <6>, CLKS <10>, CLKS <14>, CLKS <18>, respectively; the fourth set of clocks are CLKS <3>, CLKS <7>, CLKS <11>, CLKS <15>, CLKS <19>, respectively. Fig. 3 is a simplified block diagram of a low-speed parallel-to-serial conversion circuit according to the present invention, using a first set of clocks as an example. CLKM is a 0.02N GHz clock with an input duty cycle of 50%, and CLK1P and CLK1N clocks are sequentially generated through two-stage inverters. And SNX0 is also the inverse clock of CLKS <0 >. After the input 0.1N Gbps data is sampled by the D trigger with different sampling clocks, the corresponding clock gating is carried out at different moments, so that 5: 1. The data actually converted from these four sets of data are listed below in the form of a table. For convenience of explanation, 2 columns of 20bit data of 0.1N Gbps data are designated herein as D90 to D00 and D91 to D11, respectively. The data sampled first time by CLK1P is designated as D90-D00 and the data sampled first time by CLK1N is designated as D91-D01. Table 1 is a table of data bits, sampling multiphase clocks, and serial codewords for each group of parallel data samples in the low speed parallel to serial conversion circuit. Fig. 4 is a simplified timing diagram of a low-speed parallel-serial conversion circuit according to the present invention.

TABLE 1 Low speed parallel to serial conversion circuit codeword table

Fig. 5 shows a simplified block diagram of a 4:1 parallel to serial conversion circuit configuration in accordance with the present invention. The 4:1 circuit is mainly composed of 3 2:1 is formed by MUX circuits. The clock signals in each MUX circuit are different, e.g., CLKQ <3:0> in I0 and I1 is a 0.25N GHz clock signal with a 90 DEG phase difference, and CLKP and CLKN signals in I2-I4 are 0.5N GHz differential clock signals. Here Q <3: the 0> signal is 4bit data output from the previous stage. After I0, the Q20 node signal output codeword should be D80D60D40D20D00D81D61D41D21D01, and the data rate is 0.5N GHz. The Q31 node outputs code word as D90D70D50D30D10D91D71D51D31D11, and the data rate is also 0.5N GHz. To align the data timing exactly, the Q20 and Q31 signals are resampled by a D flip-flop with sampling clocks CLK and CLKN, respectively. The two-stage MUX circuit finally carries out 2:1 gating on the sampled data, and finally realizes complete serialization, and the high-order data is first-out, namely the output code word is

D90D80D70D60D50D40D30D20D10D00D 81D71D61D51D4DD31D21D11D01, and the data rate is N Gbps.

The time sequence diagram of the core 4:1 parallel-serial conversion circuit in the parallel-serial conversion circuit provided by the invention is shown in fig. 6, and the conversion from 10bit data to 4bit data is realized by means of a low-frequency multiphase clock generated by a clock frequency division system. The structure not only reduces the highest working frequency of the clock on the parallel-serial conversion circuit and reduces the overall power consumption and the design difficulty, but also provides a new design thought for data bits from non-2 ^N to 2 ^N.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (6)

1. High speed 10:1 parallel-serial conversion circuit, characterized by comprising:

The clock frequency division module is connected with the initial four-phase clock, and divides the frequency of the initial clock for multiple times through frequency dividers with different frequency division ratios to obtain clocks with different frequencies and 20bit multiphase clocks needed by the low-speed parallel-serial conversion module circuit;

The low-speed parallel-serial conversion module is connected with 10-bit parallel 0.1N Gbps data, a 0.5N GHz four-phase single-ended clock and a 0.05N GHz 20-bit single-ended multiphase clock, and realizes parallel-serial conversion of the 10-bit parallel data under the control of the clock to obtain 4-bit parallel differential CMOS data;

The 4:1 parallel-serial conversion module is used for receiving the 4-bit parallel differential data output by the first-level low-speed parallel-serial conversion module, and the sampling clock is a four-phase clock of 0.25N GHz and a differential clock of 0.5N GHz; and the 4:1 parallel-serial conversion module converts the 4-bit parallel differential data into 1-bit parallel differential signals under the control of the clocks with different frequencies.

2. The high speed 10 of claim 1: the parallel-serial conversion circuit is characterized in that the clock frequency division module comprises a latch array, a multi-stage frequency division circuit, a multi-phase frequency division circuit and a delay array unit, and different frequencies and different phase clocks are generated, wherein the frequency of the 20bit multi-phase clock is 0.05 times of the highest serial data, and the duty ratio of the low level in the multi-phase clock is 1:20; the clock signal generating circuit with the 1:20 duty ratio mainly comprises a NAND gate and a clock selection inverter logic, the transistor size of the D flip-flops is adjusted, so that the device fixed delay of each D flip-flop is 1/20 of the multiphase clock, and the 20-bit multiphase clock is finally generated through resampling and delay of a primary stage.

3. The high speed 10 of claim 2: the parallel-serial conversion circuit 1 is characterized in that the 20-bit multiphase clock is divided into 4 groups for sampling by the low-speed parallel-serial circuit, each parallel-serial conversion is used for obtaining 10-bit data with the data rate of 0.1N Gbps, namely 20-bit 0.05N Gbps data, and each bit of data is selected to be conducted by a clock selection inverter after being sampled by 2 or more D triggers; the type of the D trigger is the same, only the sampling clocks are different, the sampling clocks are alternately 0.05N GHz differential clocks, the differential data with the 4bit data rate of 0.25N Gbps is output, and the conversion from non-2 ^N data to 2 ^N data is realized.

4. A high speed 10 as claimed in claim 3: 1 parallel-serial conversion circuit, characterized in that, the output end of the low-speed parallel-serial conversion module is connected to the 4: the 1 parallel-serial conversion module realizes the conversion from data to 2 ^N bits;

The 4: the 1 parallel-serial conversion module mainly comprises 3 MUX2:1 circuits and 2D triggers, wherein data bits in the two MUX2:1 circuits of the first stage are respectively connected with the 0 th bit, the 2 nd bit, the 1 st bit and the 3 rd bit of the low-speed parallel-serial conversion module of the previous stage; and then the input end of the second stage MUX2:1 is connected with the output ends of the 2D triggers through the sampling unified time sequence of the D triggers, and finally, the high-speed serialization of signals is realized.

5. The high speed 10 of claim 4: the parallel-serial conversion circuit is characterized in that the 4:1 parallel-serial conversion module is connected with an external interface circuit through an additional output driving module after realizing high-speed serialization.

6. The high speed 10 of claim 1: the parallel-serial conversion circuit is characterized in that the 4:1 parallel-serial conversion module is of a typical tree structure.