CN118280838A

CN118280838A - Semiconductor manufacturing process

Info

Publication number: CN118280838A
Application number: CN202211722751.5A
Authority: CN
Inventors: 陈朝刚; 谈文毅; 苏世芳
Original assignee: United Semi Integrated Circuit Manufacture Xiamen Co ltd
Current assignee: United Semi Integrated Circuit Manufacture Xiamen Co ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2024-07-02

Abstract

The invention discloses a semiconductor manufacturing process method, which comprises the steps of forming a substrate, forming at least one first grid on the substrate in a first area, forming a second grid on the substrate in a second area, forming an oxide layer on the substrate in the second area, covering the first grid and the second grid, forming a nitride layer, covering the oxide layer, performing a rapid annealing step, and sequentially removing part of the nitride layer and the oxide layer in the first area.

Description

Semiconductor manufacturing process

Technical Field

The invention relates to the field of semiconductors, in particular to a method for saving a manufacturing process when a stress memory technology manufacturing process and a metal silicide manufacturing process are sequentially carried out.

Background

In the conventional semiconductor manufacturing process, it is desired to increase the performance of the semiconductor device, and a common method is to change the stress of the gate channel, which may be also referred to as a stress memorization technique (stress memorization technique, SMT). However, when using the above method, it is necessary to additionally form a stress layer and heat it to provide transistor stress. And the stress layer is removed in a subsequent step, thereby adding additional processing steps.

Therefore, a semiconductor manufacturing process is needed that can effectively utilize the stress layer formed in the stress memorization technique to achieve the purpose of saving steps.

Disclosure of Invention

The invention provides a semiconductor manufacturing process method, which comprises the steps of forming a substrate, forming at least one first grid on the substrate in a first area, forming a second grid on the substrate in a second area, forming an oxide layer on the substrate in the second area, covering the first grid and the second grid, forming a nitride layer, covering the oxide layer, performing a rapid annealing step, and sequentially removing part of the nitride layer and the oxide layer in the first area.

In the prior art, if a Stress Memory Technology (SMT) process is performed sequentially with a metal silicide process, a stress layer formed in the SMT process is removed first, and then a new material layer is formed again to start the metal silicide process. But this adds additional processing steps. The invention is characterized in that the stress layer formed in the SMT manufacturing process is directly used for the mask of the subsequent metal silicide manufacturing process, so that the mask layer is not required to be repeatedly formed, and the effect of saving steps is achieved.

Drawings

Fig. 1 to 9 are schematic views of a semiconductor manufacturing process according to a first preferred embodiment of the present invention;

fig. 10 to 13 are schematic views illustrating a semiconductor manufacturing process according to a second preferred embodiment of the present invention.

Description of the main reference signs

10 Substrate

11 Shallow trench isolation

12 Gate conductive layer

14 Spacer wall

14A spacer

14B spacer

20 Oxide layer

22 Nitrided layer

24 Photoresist layer

25 Natural oxide layer

30 Oxide layer

32 Nitride layer

34 Photoresist layer

40 Metal silicide layer

P1 rapid annealing step

P2 etching step

P3 etching step

R1 first region

R2-second region

Detailed Description

The following description sets forth the preferred embodiments of the present invention and, together with the accompanying drawings, provides a further understanding of the invention, and further details of the construction and the advantages to be achieved by those skilled in the art to which the invention pertains.

For convenience of description, the drawings of the present invention are merely schematic to facilitate understanding of the present invention, and a detailed ratio thereof may be adjusted according to design requirements. The relative positioning of the elements in the figures is understood by those skilled in the art, and thus the elements can be reversed to present the same elements, which are encompassed by the present disclosure.

Referring to fig. 1 to 9, a semiconductor manufacturing process according to a first preferred embodiment of the invention is shown. As shown in fig. 1, a substrate 10, such as a silicon substrate, is provided, and the substrate 10 includes a first region R1 and a second region R2, wherein in the following steps, different devices, such as different types of transistors (P-type or N-type), or other devices, may be formed in the first region R1 and the second region R2 according to different requirements. In this embodiment, for example, a P-type transistor may be formed in the first region R1, an N-type transistor may be formed in the second region R2, and a metal silicide may be formed in the first region R1 (but not in the second region R2) in a subsequent manufacturing process. It should be noted that the above examples are only one possibility of the present invention, and the present invention is not limited thereto. The substrate 10 between the first region R1 and the second region R2 includes a shallow trench isolation 11, and the shallow trench isolation 11 is made of an insulating material such as silicon oxide, but is not limited thereto.

As shown in fig. 1, a gate G1 and a gate G2 are formed on the substrate 10 in the first region R1 and the second region R2, and the gate G1 and the gate G2 may include a gate conductive layer 12 and a spacer 14 respectively located at two sides of the gate conductive layer 12. The gate conductive layer 12 is made of metal, polysilicon, or the like, and the spacer 14 is made of an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, but the present invention is not limited thereto. In some embodiments, the spacer 14 may be a multi-layer structure, for example, the spacer 14 is a dual-layer structure including the spacers 14A and 14B, but the invention is not limited thereto. Next, an oxide layer 20 and a nitride layer 22 are sequentially formed in the first region R1 and the second region R2, wherein the oxide layer 20 comprises silicon oxide and the nitride layer comprises silicon nitride.

Referring to fig. 2, 3 and 4, as shown in fig. 2, a photoresist layer 24 is formed to cover the nitride layer 22 in the second region R2, and as shown in fig. 3, an etching step is performed to remove the nitride layer 22 in the first region R1 and expose the oxide layer 20 in the first region R1. Since the second region R2 is covered with the photoresist layer 24, the nitride layer 22 and the oxide layer 20 in the second region R2 still exist.

Next, as shown in fig. 4, the photoresist layer 24 in the second region R2 is removed, and the nitride layer 22 in the second region R2 is exposed, and then a rapid annealing (RTP) step P1 is performed, which can provide different effects for different regions. For example, for an N-type transistor, the device may generate a tensile force due to thermal expansion when performing the rapid annealing step P1, which may improve the quality of the device, such as the speed of the transistor. The above steps are known as Stress Memorization Technique (SMT), and other related knowledge about SMT belongs to the prior art in the field, and are not repeated herein. The purpose of removing the nitride layer 22 in the first region R1 and only leaving the nitride layer 22 in the second region R2 is to improve the performance of the N-type transistor in the SMT step P1.

It is further noted that after the rapid annealing (RTP) step P1, since the surface of the nitride layer 22 is exposed to oxygen in the air and is at a high temperature, a native oxide layer 25 may be formed on the surface of the nitride layer 22, wherein the native oxide layer 25 is not a material layer desired to be formed by the manufacturing process, but is a concomitant product during the manufacturing process.

Next, as shown in fig. 5 to 6, the remaining nitride layer 22 (located in the second region R2) and the oxide layer 20 (located in the first region R1 and the second region R2) are sequentially removed. It should be noted that, in fig. 5, before removing the nitride layer 22, the natural oxide layer 25 needs to be removed first because the surface of the nitride layer 22 is formed with the natural oxide layer 25. The method for removing the native oxide layer 25 is, for example, soaking with hydrofluoric acid (DHF) solution (etching step P2 in fig. 5), removing the native oxide layer 25, and then continuing to remove the nitride layer 22, wherein the nitride layer 22 is removed, for example, soaking with phosphoric acid solution (etching step P3 in fig. 5).

Subsequently, as shown in fig. 7 and 8, another oxide layer 30 and another nitride layer 32 are formed again to cover the first region R1 and the second region R2, and then another photoresist layer 34 is formed to cover the second region R2. As shown in fig. 8, an etching step is performed to remove the nitride layer 32 and the oxide layer 30 in the first region R1, and then remove the photoresist layer 34.

Referring to fig. 9, when the substrate 10 in the first region R1 is exposed, a metal silicide process may be performed on the first region R1, for example, a metal layer (not shown) is formed in the first region R1 to cover the substrate 10, and a heating step is performed to react the metal layer with the substrate 10 and form a metal silicide layer 40 to cover the substrate 10 at both sides of the gate electrode G1. In the present embodiment, the metal layer is, for example, a nickel layer, and the metal silicide layer is, for example, a nickel silicide (NiSi) layer, but the present invention is not limited thereto. Other related art related to metal silicide fabrication processes are known in the art and are not repeated here.

The applicant has found that the first embodiment described above still has some problems. First, in fig. 5, when the native oxide layer 25 is removed, since the oxide layer 20 in the first region R1 is also exposed, the oxide layer 20 in the first region R1 may be removed together when the first region R1 is immersed in a hydrofluoric acid (DHF) solution, and even if the spacer 14 is made of silicon oxide in some embodiments, the spacer 14 is etched together and lowered.

If the manufacturing process is adjusted without immersing hydrofluoric acid to remove the native oxide layer 25, that is, directly immersing phosphoric acid solution to remove the nitride layer 22, the silicon nitride layer 22 may not be etched cleanly due to the low etching speed of phosphoric acid to silicon oxide, which may affect the formation quality of subsequent devices.

Therefore, both of the above cases may affect the quality of the semiconductor structure fabricated by the present invention.

In addition, in the first embodiment of the present invention, the transistor (e.g., P-type transistor) located in the first region R1 or the transistor (e.g., N-type transistor) located in the second region R2 is subjected to the SMT process, and then the metal silicide process is performed, so that the oxide layer and the nitride layer need to be regrown (fig. 7), which also makes the manufacturing process more complicated.

In order to simplify the manufacturing process, a second embodiment of the present invention is presented, referring to fig. 10 to 13, which illustrate a semiconductor manufacturing process method according to a second preferred embodiment of the present invention. In order to clearly describe the differences between the different embodiments, the same points of this embodiment as the first embodiment described above are denoted by the same reference numerals.

As shown in fig. 10, similar to fig. 1 of the first embodiment, a substrate 10 is provided, the substrate 10 includes a first region R1 and a second region R2, the substrate 10 between the first region R1 and the second region R2 includes shallow trench isolation 11, the substrate 10 is formed with a gate G1 and a gate G2, and the gate G1 and the gate G2 may include a gate conductive layer 12 and a spacer 14 located at two sides of the gate conductive layer 12. The spacer 14 in this embodiment has a double-layer structure, including the spacer 14A and the spacer 14B, but the invention is not limited thereto. Next, an oxide layer 20 and a nitride layer 22 are sequentially formed in the first region R1 and the second region R2, wherein the oxide layer 20 comprises silicon oxide and the nitride layer comprises silicon nitride. The material characteristics of each element mentioned in this embodiment are substantially the same as those of the first embodiment, and thus a detailed description thereof will not be repeated.

It should be noted that the first region R1 and the second region R2 may include transistors of the same type, for example, N-type transistors. In the present embodiment, the difference between the first region R1 and the second region R2 is that the metal silicide layer is formed in the first region R1 in the subsequent step, but the metal silicide layer is not formed in the second region R2.

Next, as shown in fig. 11, unlike the first embodiment, the rapid annealing (RTP) step P1 is directly performed without removing the nitride layer 22 of the first region R1, that is, the transistors in the first region R1 and the second region R2 are simultaneously subjected to rapid annealing. If the transistors in the first region R1 and the second region R2 are both N-type transistors, the performance of the transistors in the two regions can be improved at the same time, and besides, the nitride layer 22 remains in the first region R1 and the second region R2, so that the lower gate G1 and the lower gate G2 can be better protected.

As shown in fig. 12 to 13, in the case of retaining the oxide layer 20 and the nitride layer 22, the photoresist layer 34 is directly formed in the second region R2, and the subsequent steps are similar to those of fig. 8 to 9 of the first embodiment described above, the nitride layer 22 and the oxide layer 20 in the first region R1 are removed, and the metal silicide layer 40 is formed in the first region R1. Since these steps are similar to those described in the first embodiment, the description thereof will not be repeated here.

Unlike the first embodiment, the nitride layer in the first region R1 is not removed in the SMT step (fig. 10 to 11), so that the nitride layer 22 can protect the underlying gate electrode G1 and the underlying gate electrode G2. In addition, the step of removing the nitride layer 22 and the oxide layer 20 (i.e., the steps of fig. 5 and 6 in the first embodiment) is omitted after the SMT step is completed, so that the problem of incomplete etching caused by overetching with DHF or without DHF in the first embodiment is avoided. The nitride layer 22 and the oxide layer 20 in the SMT step are retained in the metal silicide process (fig. 12 to 13), that is, the nitride layer and the oxide layer in the SMT process are directly used as the nitride layer and the oxide layer which should be regenerated in the metal silicide process. Therefore, the nitride layer and the oxide layer do not need to be removed and then reformed, and compared with the first preferred embodiment, the method omits a plurality of steps and can save manufacturing process steps.

In addition, in the second embodiment, if the first region R1 and the second region R2 include different types of transistors, for example, the transistors in the first region R1 are P-type transistors and the transistors in the second region R2 are N-type transistors, also applicable. In the SMT step, even if the heating step results in a slight decrease in the performance of the P-type transistor (and an increase in the performance of the N-type transistor), the second embodiment of the present invention achieves the advantage of saving multiple steps as a whole.

In view of the above description and the accompanying drawings, the present invention provides a semiconductor manufacturing process, which includes forming a substrate 10, forming at least a first gate G1 on the substrate 10 in the first region R1 and forming a second gate G2 on the substrate 10 in the second region R2, forming an oxide layer 20, covering the first gate G1 and the second gate G2, forming a nitride layer 22, covering the oxide layer 20, performing a rapid annealing step P1, and sequentially removing part of the nitride layer 22 and the oxide layer 20 of the first region R1.

In some embodiments of the present invention, the rapid annealing step P1 is performed, and the nitride layer 22 and the oxide layer 20 still cover the first region R1 and the second region R2.

In some embodiments of the present invention, after the rapid annealing step P1 is completed, a photoresist layer 34 is formed in the second region R2 to cover the nitride layer 22.

In some embodiments of the present invention, the oxide layer 20 and the nitride layer 22 in the first region and the second region are not removed after the rapid annealing step P1 is performed until the photoresist layer 34 is formed (refer to fig. 11 to 12 of the second embodiment of the present invention).

In some embodiments of the present invention, the rapid annealing step P1 is performed before the formation of the photoresist layer 34, and no other material layer is included in the first region R1 and the second region R2.

In some embodiments of the present invention, after the nitride layer 22 is formed, a native oxide layer 25 is further included on the surface of the nitride layer 22.

In some embodiments of the present invention, the method for removing the nitride layer 22 of the first region R1 further comprises removing the native oxide layer 25 on the surface of the nitride layer with a hydrofluoric acid (DHF) solution.

In some embodiments of the present invention, the method for removing the nitride layer 22 of the first region R1 includes removing the nitride layer 22 with a phosphoric acid solution after the native oxide layer 25 is removed.

In some embodiments of the present invention, a plurality of spacers 14 are disposed on both sides of the first gate G1 and the second gate G2, respectively.

In some embodiments, the spacers 14 comprise a multi-layer structure (14A, 14B), wherein at least one of the spacers comprises silicon oxide.

In some embodiments of the present invention, after the nitride layer 22 and the oxide layer 20 in the first region R1 are removed, a portion of the substrate 10 in the first region R1 is exposed.

In some embodiments of the present invention, a metal silicide layer 40 is formed on the exposed substrate 10 in the first region R1.

In some embodiments of the present invention, the metal silicide layer comprises nickel silicide (NiSi).

In some embodiments of the present invention, the first gate and the second gate comprise polysilicon.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A semiconductor fabrication process comprising:

forming a substrate, wherein the substrate comprises a first area and a second area;

Forming at least one first grid electrode on the substrate in the first area, and forming a second grid electrode on the substrate in the second area;

Forming an oxide layer to cover the first grid electrode and the second grid electrode;

forming a nitride layer to cover the oxide layer;

performing a rapid annealing step; and

And sequentially removing part of the nitride layer and the oxide layer in the first region.

2. The method of claim 1, wherein the rapid annealing step is performed while the nitride layer and the oxide layer remain covered in the first region and the second region.

3. The method of claim 1, wherein after the rapid annealing step is completed, further comprising forming a photoresist layer in the second region to cover the nitride layer.

4. The method of claim 1, wherein the oxide layer and the nitride layer in the first region and the second region are not removed after the rapid annealing step is performed until the photoresist layer is formed.

5. The method of claim 1, wherein the rapid annealing step is performed before the formation of the photoresist layer, and no additional material layer is included in the first region and the second region.

6. The method of claim 1, wherein after the nitride layer is formed, a native oxide layer is further included on the surface of the nitride layer.

7. The method of claim 6, wherein removing the nitride layer of the first region further comprises removing the native oxide layer on the surface of the nitride layer with a hydrofluoric acid (DHF) solution.

8. The method of claim 7, wherein removing the nitride layer of the first region comprises removing the nitride layer with a phosphoric acid solution after the native oxide layer is removed.

9. The method of claim 1, further comprising a plurality of spacers disposed on both sides of the first gate and the second gate, respectively.

10. The method of claim 9, wherein the spacers comprise a multi-layer structure, wherein the material of at least one layer of spacers comprises silicon oxide.

11. The method of claim 1, wherein the nitride layer and the oxide layer in the first region are removed and a portion of the substrate in the first region is exposed.

12. The method of claim 10, further comprising forming a metal silicide layer on the exposed substrate in the first region.

13. The method of claim 12, wherein the metal silicide layer comprises nickel silicide (NiSi).

14. The method of claim 1, wherein the first gate and the second gate comprise polysilicon.