CN118280722A

CN118280722A - Multilayer electronic component and method for manufacturing the same

Info

Publication number: CN118280722A
Application number: CN202311182279.5A
Authority: CN
Inventors: 罗元竣; 康崙盛; 郑会烲; 金善花; 朴柄圭
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2022-12-29
Filing date: 2023-09-13
Publication date: 2024-07-02

Abstract

The present disclosure provides a multilayer electronic component and a method of manufacturing the same. The multilayer electronic component includes: a body including a plurality of dielectric layers and a plurality of internal electrodes; and an external electrode disposed on the body, wherein at least one of the plurality of internal electrodes includes Ni, sr, and Ru, and an average content of (Sr+Ru)/(Ni+Sr+Ru) is greater than 0wt% and less than 8.40wt%, wherein the average content of (Sr+Ru)/(Ni+Sr+Ru) refers to a sum of mass percentages of Sr and Ru when the sum of mass percentages of Ni, sr, and Ru is converted to 100 wt%.

Description

Multilayer electronic component and method for manufacturing the same

The present application claims the benefit of priority from korean patent application No. 10-2022-0189617 filed on the date of 2022, 12 months, 29 and korean patent application No. 10-2023-0031805 filed on the date of 2023, 3 months, 10, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to a multilayer electronic component and a method of manufacturing the same.

Background

A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, may be a chip capacitor mounted on a printed circuit board of various electronic products such as image display devices including Liquid Crystal Displays (LCDs) and Plasma Display Panels (PDPs), computers, smart phones, and mobile phones and used for charging or discharging.

Since the multilayer ceramic capacitor may have a small size and high capacitance and may be easily mounted, such a multilayer ceramic capacitor may be used as a component of various electronic devices. As various electronic devices such as computers and mobile devices have been miniaturized and implemented as high output, demands for miniaturized and high-capacitance multilayer ceramic capacitors have increased.

As a method for achieving miniaturization and high capacitance of the multilayer ceramic capacitor, a method of reducing the thickness of the internal electrode can be used. However, when the internal electrode is formed by printing or coating a conductive paste, it may be difficult to ensure uniformity of thickness of the internal electrode, the thickness may be different at different positions, and there may be a limit in reducing the thickness.

In order to greatly reduce the thickness of the inner electrode, it may be necessary to develop atomization techniques for the inner electrode material first. As the material is atomized and nanosized, the onset temperature or melting point of necking between the metal powder particles may decrease, which may result in a decrease in the onset temperature of thermal shrinkage. In the case of a metal material, the decrease in the heat shrinkage initiation temperature due to the size reduction may be higher than the decrease in the heat shrinkage initiation temperature of the ceramic material, so that there may be a difference in the heat shrinkage initiation temperature between the dielectric layer and the internal electrode. As the difference in the thermal shrinkage initiation temperature between the dielectric layer and the internal electrode increases, connectivity between the internal electrodes may deteriorate during the sintering process (i.e., the disconnection area of the internal electrode may increase), a decrease in capacitance and a decrease in reliability may occur, and as the number of stacked internal electrodes increases, a step difference may occur.

Currently, a method of adding fine-sized barium titanate (BaTiO ₃) to the internal electrode may be used to reduce the difference in the heat shrinkage initiation temperature between the dielectric layer and the internal electrode. However, when a large amount of barium titanate is added to reduce the thickness of the internal electrode, the film density of the internal electrode may decrease, and the barium titanate may be absorbed into the dielectric layer, so that the thickness of the dielectric layer may increase, and the capacitance may decrease. Therefore, an attempt is made to add a material having higher thermal stability than barium titanate, and an optimum addition amount may need to be designed in consideration of various variables.

Disclosure of Invention

Example embodiments of the present disclosure are directed to achieving miniaturization and high capacitance of multilayer electronic components.

Example embodiments of the present disclosure are directed to reducing the thickness of an inner electrode.

Example embodiments of the present disclosure are directed to improving connectivity of an internal electrode.

Example embodiments of the present disclosure are directed to improving thickness uniformity of an internal electrode.

Example embodiments of the present disclosure are directed to controlling the size of dielectric grains

According to an example embodiment of the present disclosure, a multilayer electronic assembly includes: a body including a plurality of dielectric layers and a plurality of internal electrodes; and an external electrode disposed on the body, wherein at least one of the plurality of internal electrodes includes Ni, sr, and Ru, and an average content of (Sr+Ru)/(Ni+Sr+Ru) is greater than 0wt% and less than 8.40wt%, wherein the average content of (Sr+Ru)/(Ni+Sr+Ru) refers to a sum of mass percentages of Sr and Ru when the sum of mass percentages of Ni, sr, and Ru is converted to 100 wt%.

According to another example embodiment of the present disclosure, a method of manufacturing a multilayer electronic assembly includes: forming a laminate by laminating a plurality of ceramic green sheets on which a plurality of internal electrode patterns are formed and cutting the plurality of ceramic green sheets; sintering the laminate; and forming an external electrode on the sintered laminate, wherein at least one of the plurality of internal electrode patterns is formed by depositing Ni and SrRuO ₃ by using a sputtering method, wherein the content of SrRuO ₃ is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of Ni.

According to another example embodiment of the present disclosure, a method of manufacturing a multilayer electronic component includes laminating a plurality of ceramic green sheets, wherein an internal electrode pattern is disposed on at least one ceramic green sheet of the plurality of ceramic green sheets, the internal electrode pattern includes Ni and SrRuO ₃, and a content of SrRuO ₃ is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of Ni.

According to an example embodiment of the present disclosure, a multilayer electronic assembly includes: a body including a plurality of dielectric layers and a plurality of internal electrodes; and an external electrode disposed on the body, wherein at least one of the plurality of internal electrodes includes Ni, sr, and Ru, and an average content of (sr+ru)/(ni+sr+ru) is greater than 0wt% and equal to or less than 3.61wt%, wherein the average content of (sr+ru)/(ni+sr+ru) refers to a sum of mass percentages of Ni, sr, and Ru when the sum of mass percentages of Ru is converted to 100wt%, wherein the at least one of the plurality of internal electrodes includes an electrode region including a conductive material and a disconnection region not containing the conductive material, and wherein the at least one of the plurality of internal electrodes satisfies 90% +.c, wherein C is a connectivity of the at least one of the plurality of internal electrodes, and is defined as a ratio of a sum of lengths of the electrode regions to a total length of the at least one of the plurality of internal electrodes.

Drawings

The above and other aspects, features and advantages of the present disclosure will be more clearly understood from a consideration of the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a perspective view illustrating a multilayer electronic assembly according to an example embodiment of the present disclosure;

Fig. 2 is an exploded perspective view illustrating a laminated structure of an internal electrode according to an example embodiment of the present disclosure;

FIG. 3 is a cross-sectional view taken along line I-I' in FIG. 1;

FIG. 4 is a cross-sectional view taken along line II-II' in FIG. 1;

fig. 5 is an enlarged view showing a region P in fig. 3;

Fig. 6 is an enlarged view showing a part of a capacitance forming portion according to an example embodiment of the present disclosure;

fig. 7A to 7D are images of capacitance forming portions obtained by SEM according to an exemplary embodiment and a comparative example;

Fig. 8A is an image of a capacitance forming portion obtained by SEM according to an example embodiment of the present disclosure, and fig. 8B to 8D are images of mapping specific elements using SEM-EDS according to an example embodiment of the present disclosure; and

Fig. 9A is an image of a capacitance forming portion obtained by SEM according to an example embodiment of the present disclosure, and fig. 9B to 9D are images of specific elements mapped using SEM-EDS according to an example embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, apparatus, and/or systems described herein. However, various modifications, variations, and equivalents of the methods, devices, and/or systems described herein will be readily appreciated after an understanding of the present disclosure.

In the drawings, like elements will be denoted by like reference numerals. Furthermore, redundant descriptions and detailed descriptions of known functions and known elements that may unnecessarily obscure the gist of the present disclosure will not be provided. In the drawings, some elements may be exaggerated, omitted, or briefly shown, and the sizes of the elements do not necessarily reflect the actual sizes of the elements. The terms "comprises," "comprising," "including," "includes," "including," "having" and the like in the specification are intended to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, and does not preclude the possibility of one or more features, numbers, steps, operations, elements, portions or groups thereof being present or added.

In the drawings, a first direction may be defined as a lamination direction or a thickness direction, a second direction may be defined as a length direction, and a third direction may be defined as a width direction.

Multilayer electronic component

Fig. 1 is a perspective view illustrating a multilayer electronic assembly according to an example embodiment.

Fig. 2 is an exploded perspective view showing a laminated structure of an internal electrode according to an example embodiment.

Fig. 3 is a sectional view taken along line I-I' in fig. 1.

Fig. 4 is a sectional view taken along line II-II' in fig. 1.

Fig. 5 is an enlarged view showing a region P in fig. 3.

Fig. 6 is an enlarged view showing a part of the capacitance forming portion according to the example embodiment.

Hereinafter, a multi-layered electronic component according to an example embodiment will be described in more detail with reference to fig. 1 to 6. A multilayer ceramic capacitor will be described as an example of a multilayer electronic component, but various electronic components using a dielectric composition (such as an inductor, a piezoelectric element, a varistor, or a thermistor) may also be described as an example of a multilayer electronic component.

The multilayer electronic assembly 100 may include: a body 110 including a plurality of dielectric layers 111 and a plurality of internal electrodes 121 and 122; and external electrodes 131 and 132 disposed on the body 110, wherein the internal electrodes 121 and 122 may include Ni, sr, and Ru, and an average content of (sr+ru)/(ni+sr+ru) may be greater than 0wt% and less than 8.40wt%.

In the body 110, the dielectric layers 111 and the internal electrodes 121 and 122 may be alternately stacked.

More specifically, the body 110 may include a capacitance forming portion Ac disposed in the body 110 and forming a capacitance, the capacitance forming portion Ac including first and second internal electrodes 121 and 122 alternately disposed to face each other with the dielectric layer 111 interposed between the first and second internal electrodes 121 and 122.

The shape of the body 110 may not be limited to any particular shape, but as shown in fig. 1, the body 110 may have a hexahedral shape or a shape similar to a hexahedral shape. Since the ceramic powder included in the body 110 is contracted during the sintering process, the body 110 may not have an exact hexahedral shape formed of a straight line, but may have a substantially hexahedral shape.

The body 110 may have first and second surfaces 1 and 2 opposite to each other in a first direction, third and fourth surfaces 3 and 4 connected to the first and second surfaces 1 and 2 and opposite in a second direction, and fifth and sixth surfaces 5 and 6 connected to the first and second surfaces 1 and 2 and the third and fourth surfaces 3 and 4 and opposite to each other in the third direction.

The plurality of dielectric layers 111 forming the body 110 may be in a sintered state, and boundaries between adjacent dielectric layers 111 may be integrated with each other such that the boundaries therebetween may not be apparent without using a Scanning Electron Microscope (SEM).

The raw material for forming the dielectric layer 111 is not limited to any particular example as long as a sufficient capacitance can be obtained therewith. For example, barium titanate-based materials, lead composite perovskite-based materials, or strontium titanate-based materials may be used. The barium titanate-based material may include BaTiO ₃ ceramic powder, and examples of BaTiO ₃ ceramic powder may include (Ba_1-xCa_x)TiO₃(0<x<1)、Ba(Ti_1-yCa_y)O₃(0<y<1)、(Ba_1-xCa_x)(Ti_1-yZr_y)O₃(0<x<1,0<y<1) or Ba (Ti _1-yZr_y)O₃ (0 < y < 1) in which calcium (Ca) and/or zirconium (Zr) are partially solid-solved in BaTiO ₃.

In addition, various ceramic additives, organic solvents, binders, dispersants, and the like may be added to the raw materials such as barium titanate (BaTiO ₃) used to form the dielectric layer 111 in the example embodiment.

The thickness td of the dielectric layer 111 may not be limited to any particular example.

However, in order to easily achieve miniaturization and high capacitance of the multilayer electronic component 100, the thickness td of the dielectric layer 111 may be 0.6 μm or less, and more preferably may be 0.4 μm or less.

Here, the thickness td of the dielectric layer 111 may refer to an average thickness of the dielectric layer 111 disposed between the first and second internal electrodes 121 and 122.

The thickness td of the dielectric layer 111 may refer to a dimension of the dielectric layer 111 in the first direction. Further, the thickness td of the dielectric layer 111 may refer to an average thickness td of the dielectric layer 111 and may refer to an average size of the dielectric layer 111 in the first direction.

The average thickness of the dielectric layer 111 may be measured by scanning a cross section of the body 110 in the first direction and the second direction using a Scanning Electron Microscope (SEM) with a magnification of 10000. More specifically, the average value can be obtained by: in the scanned image, the thickness of the dielectric layer 111 at 5 points equidistantly spaced in the second direction is averaged. The 5 points equidistantly spaced apart may be specified in the capacitance forming portion Ac. Further, when the average value is measured by extending the measurement of the average value to ten dielectric layers 111, the average thickness of the dielectric layers 111 in the first direction can be more generalized. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used to obtain an average thickness of the dielectric layer 111, even if not described in this disclosure.

Hereinafter, an example of a method of measuring an average thickness of a dielectric layer and a standard deviation of the thickness of the dielectric layer in an example embodiment will be described in more detail with reference to fig. 5.

Fig. 5 is an enlarged view showing a part of the capacitance forming portion in the cross section of the main body 110 in the first direction and the second direction (more specifically, a part including any of the internal electrodes 121 and 122 and the dielectric layer 111 provided in the central region, which is obtained by dividing the capacitance forming portion Ac into five equal parts in the first direction, in the cross section taken along the first direction and the second direction at the central portion of the main body 110 in the third direction).

The average thickness td of the dielectric layer 111 may be an average of dimensions (td 1, td2, td3, td4, td5, etc.) in the first direction measured at five or more points (line a) of the dielectric layer 111 equidistantly spaced in the second direction in the region shown in fig. 5.

In an example embodiment, the dielectric layer 111 may include a plurality of dielectric grains, and strontium (Sr) may be disposed at a dielectric grain boundary, which is a boundary between grains adjacent to each other. Further, triple points may be provided in areas where three or more dielectric grain boundaries are in contact with each other, and strontium (Sr) may be provided at the triple points of the dielectric grains. The dielectric grain boundaries and the metal grain boundaries (described further below) may be observed by scanning a cross section of the body 110 in the first direction and the second direction using a Scanning Electron Microscope (SEM). Other methods and/or tools as understood by those of ordinary skill in the art may be used to observe dielectric and metal grain boundaries, even if not described in the present disclosure.

Further, the average size (GD) of the dielectric grains may be 50nm or more and 300nm or less.

When the average size (GD) of the dielectric grains is 50nm or more and 300nm or less, the target insulation resistance characteristics and dielectric characteristics can be obtained.

When the average size (GD) of the dielectric grains is less than 50nm, dielectric properties may be deteriorated, and when the average size (GD) of the dielectric grains exceeds 300nm, insulation resistance properties may be deteriorated.

Hereinafter, an example of a method of measuring an average size (GD) of dielectric grains will be described, but example embodiments thereof are not limited thereto.

The average size of the dielectric grains can be obtained by: the average size of dielectric grains included in the central region of the capacitance forming portion Ac is measured with respect to a cross section taken in the first direction and the second direction at the central portion of the body 110 in the third direction. For example, the dielectric crystal grains may be extracted from an image of a 5 μm×5 μm region (including the internal electrode and the dielectric layer) included in the central region of the capacitance forming portion Ac obtained by SEM by an image program. In the extracted dielectric grains, the size (distance) of the longest straight line passing through the center of the dielectric grains may be defined as the size of the dielectric grains, and the average value of the measured sizes of the dielectric grains may be defined as the average size of the dielectric grains. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used to obtain the average size of the dielectric grains, even if not described in the present disclosure.

For example, the sizes (GD 1, GD2, GD3, GD4, GD5, etc.) of five or more dielectric grains included in a specific region may be measured, and the measured values may be averaged to calculate an average size (GD) of the dielectric grains.

In an example embodiment, the percentage of the dimensional variation coefficient (CV%) of the dielectric grains may be greater than 0% and equal to or less than 38%, and preferably may be equal to or less than 22%, the dimensional variation coefficient of the dielectric grains being a ratio of the standard deviation of the dimensions of the dielectric grains (σgd) to the average size of the plurality of dielectric Grains (GD).

The standard deviation of the dielectric grain size (σgd) can be obtained by: the dimensions of five or more dielectric grains (GD 1, GD2, GD3, GD4, GD5,) measured in the random area are summed with values obtained by squaring differences (GD-GD 1, GD-GD2, GD-GD3, GD-GD4, GD-GD5,) of the average dimensions of the dielectric grains measured by the above method, and the values are divided by the measured number of dielectric grains and square root.

In this case, the ratio of the standard deviation (σgd) of the size of the dielectric grain to the average size (GD) of the plurality of dielectric grains (σgd/GD) may be referred to as the size variation Coefficient (CV) of the dielectric grain.

When the percentage of the dimensional variation coefficient (CV%) of the dielectric crystal grains exceeds 38%, it may be difficult to achieve a dielectric crystal grain of uniform size, so that it may be difficult to control the size distribution of the dielectric crystal grain, and the insulation resistance characteristics and the withstand voltage characteristics may deteriorate.

The internal electrodes 121 and 122 may be alternately laminated with the dielectric layer 111.

The internal electrodes 121 and 122 may include first and second internal electrodes 121 and 122, the first and second internal electrodes 121 and 122 may be alternately disposed to face each other with the dielectric layer 111 included in the body 110 interposed between the first and second internal electrodes 121 and 122, and the first and second internal electrodes 121 and 122 may be exposed to the third and fourth surfaces 3 and 4 of the body 110, respectively.

More specifically, the first internal electrode 121 may be spaced apart from the fourth surface 4 and may be exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and may be exposed through the fourth surface 4. The first external electrode 131 may be disposed on the third surface 3 of the body 110 and may be connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body 110 and may be connected to the second internal electrode 122.

That is, the first inner electrode 121 may be connected to the first outer electrode 131 without being connected to the second outer electrode 132, and the second inner electrode 122 may be connected to the second outer electrode 132 without being connected to the first outer electrode 131. In this case, the first and second internal electrodes 121 and 122 may be electrically separated from each other by the dielectric layer 111 disposed therebetween.

The body 110 may be formed by alternately stacking ceramic green sheets on which the conductive paste for the first internal electrode 121 is printed and ceramic green sheets on which the conductive paste for the second internal electrode 122 is printed and sintering the green sheets.

The material for forming the internal electrodes 121 and 122 is not limited to any particular example, and a material having excellent conductivity may be used. For example, the internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

Further, the internal electrodes 121 and 122 may be formed by printing a conductive paste for the internal electrodes, including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, on the ceramic green sheet. A screen printing method or a gravure printing method may be used as a method of printing the conductive paste for the internal electrode, but example embodiments thereof are not limited thereto.

However, when the internal electrode is formed by printing or coating a conductive paste, there may be a limitation in reducing the thickness of the internal electrode, for example, it may be difficult to form the internal electrode having a thickness of 0.3 μm or less. In other words, it may be difficult to realize an internal electrode that is ultra-thin in thickness and has excellent connectivity and uniformity.

Currently, a method of adding fine-sized barium titanate (BaTiO ₃) to the internal electrode may be used to reduce the difference in the heat shrinkage initiation temperature between the dielectric layer and the internal electrode. However, when a large amount of barium titanate is added to reduce the thickness of the internal electrode, the film density of the internal electrode may decrease, and the barium titanate may be absorbed into the dielectric layer, so that the thickness of the dielectric layer may increase, and the capacitance may decrease.

Accordingly, in example embodiments, the inner electrodes 121 and 122 may have an ultra-thin thickness (e.g., a thickness of greater than 0 μm and less than or equal to 0.3 μm (preferably a thickness of less than or equal to 0.25 μm and more preferably a thickness of less than or equal to 0.22 μm) by using a thin film deposition method such as sputtering or vacuum deposition, physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), and may improve connectivity and uniformity of the inner electrodes.

In example embodiments, strontium ruthenium oxide (SrRuO ₃) may reduce a difference in thermal shrinkage initiation temperature between the dielectric layer and the inner electrode. That is, strontium ruthenium oxide (SrRuO ₃) can be used as a conventional common material. However, the addition of other common materials including ceramic particles, such as barium titanate (BaTiO ₃), may not be precluded.

Accordingly, the internal electrodes 121 and 122 may include nickel (Ni), strontium (Sr), and ruthenium (Ru). In this case, the average value of (sr+ru)/(ni+sr+ru) included in the inner electrodes 121 and 122 may be more than 0wt% and less than 8.40wt%.

Here, the ratio of the contents of each element (sr+ru)/(ni+sr+ru) may refer to a ratio of the sum of the mass percentages (wt%) of the strontium (Sr) and ruthenium (Ru) elements detected in the inner electrodes 121 and 122 by EDS analysis to the sum of the mass percentages (wt%) of the nickel (Ni), strontium (Sr) and Ru elements. In this case, elements other than the mass percent (wt%) values of the nickel (Ni), strontium (Sr) and ruthenium (Ru) may be excluded and the sum of the mass percent (wt%) of the nickel (Ni), strontium (Sr) and ruthenium (Ru) may be converted to 100wt%.

For example, when the element is detected by point EDS analysis in the inner electrode, the total mass percent (wt%) of the nickel (Ni), strontium (Sr) and ruthenium (Ru) elements may be converted to 100wt%, and when the conversion result is 98.45wt% nickel (Ni), 0.40wt% strontium (Sr) and 1.15wt% ruthenium (Ru), the value of (sr+ru) may be 1.55wt%, the value of (ni+sr+ru) may be 100wt%, and thus the value of (sr+ru)/(ni+sr+ru) may be 1.55wt%.

For example, a scanning electron microscope-energy dispersive X-ray spectrometer (SEM-EDS), a transmission electron microscope-energy dispersive X-ray spectrometer (TEM-EDS), or a scanning transmission electron microscope-energy dispersive X-ray spectrometer (STEM-EDS) analysis device may be used as the EDS analysis device, but example embodiments thereof are not limited thereto. The method of measuring the type and content of the element included in the dielectric layer 111 or the internal electrodes 121 and 122 is not limited to any particular example. By way of example, the type and content of elements may be calculated from images observed using SEM-EDS, TEM-EDS, or STEM-EDS. More specifically, the cross sections in the first and second directions may be exposed by polishing the body 110 along the third direction until the central portion, and the type and content (wt%, at%, and mol%) of each element included in the dielectric layer 111 and the internal electrodes 121 and 122 disposed in the central region of the capacitance forming portion Ac may be measured using EDS.

The method of measuring the average content (wt%, at%, mol%) of the element by EDS analysis may be as follows, but example embodiments thereof are not limited thereto.

First, using the above-described method, any of the inner electrodes disposed in the central region may be selected among the sections of the body 110 taken in the first and second directions at the central portion thereof in the third direction. Thereafter, a dot EDS analysis may be performed on the central region of each selected inner electrode, and the average content (wt%, at%, mol%) of each detection element may be the average content (wt%, at%, mol%) of the element.

When the average content of (sr+ru)/(ni+sr+ru) included in the inner electrodes 121 and 122 is more than 0wt% and less than 8.40wt%, connectivity of the inner electrodes 121 and 122 may be improved, and a uniform thickness may be obtained.

The average content of (sr+ru)/(ni+sr+ru) included in the inner electrodes 121 and 122 may be more than 0wt% and less than 8.40wt%.

Here, the average content of (sr+ru)/(ni+sr+ru) included in the inner electrodes 121 and 122 may be 7.0wt% or less, 5.0wt% or less, or 3.61wt% or less, and may be 0.1wt% or more, 0.5wt% or more, 1.0wt% or more, or 1.55wt% or more.

When the average content of (sr+ru)/(ni+sr+ru) included in the inner electrodes 121 and 122 is 8.40wt% or more, sintering may not be completed or dielectric characteristics may be deteriorated.

In addition, the average content of Sr/(ni+sr+ru) included in the inner electrodes 121 and 122 may be more than 0wt% and less than 1.18wt%.

The strontium (Sr) element included in the inner electrodes 121 and 122 may be diffused into the dielectric layer 111 during the sintering process. When an excessive amount of strontium (Sr) is added to the internal electrodes 121 and 122, the amount of strontium (Sr) diffused into the dielectric layer 111 may increase, strontium (Sr) may be adsorbed to the surface of the dielectric crystal grains, sintering may be delayed, and completion of sintering may be suppressed, so that the dielectric characteristics may be deteriorated or may not be achieved.

A small amount of strontium (Sr) may promote grain growth of the dielectric grains, but an excessive amount of strontium (Sr) may inhibit grain growth of the dielectric grains. Thus, the grain growth of the dielectric grains can be controlled by adding an appropriate amount of strontium (Sr).

Further, the average content of Ru/(Ni+Sr+Ru) included in the inner electrodes 121 and 122 may be more than 0wt% and less than 2.43wt%.

The melting point of ruthenium (Ru) may be about 2334℃, which may be about 879℃ higher than the melting point of nickel (Ni) (about 1455℃). Since the melting point of ruthenium (Ru) is high, ruthenium (Ru) hardly reacts with nickel (Ni) in the sintering process, and necking between nickel (Ni) metal particles can be suppressed, so that the heat shrinkage initiation temperature can be increased.

Ruthenium (Ru) diffusion into the dielectric layer 111 may be prevented during sintering. In other words, the average content of ruthenium (Ru) included in the inner electrodes 121 and 122 may be higher than the average content of ruthenium (Ru) included in the dielectric layer 111.

In addition, ruthenium (Ru) may be disposed at grain boundaries or triple points of nickel (Ni) metal, and grain growth of nickel (Ni) may be prevented.

More specifically, the internal electrodes 121 and 122 may include a plurality of metal grains, and ruthenium (Ru) may be disposed at metal grain boundaries, which are boundaries between metal grains adjacent to each other. Further, a triple point may be disposed in a region where three or more metal grain boundaries are in contact with each other, and ruthenium (Ru) may be disposed at the triple point of the metal grain boundaries.

The internal electrodes 121 and 122 may include an oxide having at least one of strontium (Sr) and ruthenium (Ru).

For example, the inner electrodes 121 and 122 may include at least one of strontium oxide (SrO ₂), ruthenium oxide (RuO ₂), and strontium ruthenium oxide (SrRuO ₃), but example embodiments thereof are not limited thereto. This is probably because a part of the strontium ruthenium oxide (SrRuO ₃) added at the time of forming the internal electrodes 121 and 122 is decomposed into strontium oxide (SrO ₂) and ruthenium oxide (RuO ₂) during sintering, probably because of the remaining non-decomposed strontium ruthenium oxide (SrRuO ₃), and probably because of their secondary phase precipitation.

In addition, the internal electrodes 121 and 122 may include at least one of a nickel (Ni) -strontium (Sr) alloy and a nickel (Ni) -ruthenium (Ru) alloy.

This is because a part of strontium ruthenium oxide (SrRuO ₃) reacts with nickel (Ni) in the sintering process so that a nickel (Ni) -strontium (Sr) alloy or a nickel (Ni) -ruthenium (Ru) alloy can be formed.

The thickness te of the inner electrodes 121 and 122 may not need to be limited to any particular example.

However, in order to easily achieve miniaturization and high capacitance of the multilayer electronic assembly 100, the thickness te of the internal electrodes 121 and 122 may be 0.4 μm or less, preferably 0.3 μm or less, and more preferably 0.22 μm or less.

Here, the thickness of 0.3 μm or less can be preferably formed using the sputtering method or the deposition method described above. In the case of forming the internal electrode by sputtering or the like, the internal electrode can be formed to have a uniform thickness.

In the case of depositing the inner electrode using the sputtering method, a material that can increase the heat shrinkage initiation temperature, for example, strontium ruthenium oxide (SrRuO ₃), may be deposited together, thereby increasing the sintering initiation temperature between metal particles of the inner electrode and improving the connectivity of the inner electrode. In this case, when metal particles of the inner electrode and a material that increases the heat shrinkage initiation temperature are simultaneously deposited using a sputtering method, connectivity of the inner electrode can be improved.

Here, the thickness te of the inner electrodes 121 and 122 may refer to the dimension of the inner electrodes 121 and 122 in the first direction. Further, the thickness te of the inner electrodes 121 and 122 may refer to an average thickness te of the inner electrodes 121 and 122, and may refer to an average size of the inner electrodes 121 and 122 in the first direction.

The average thickness of the internal electrodes 121 and 122 may be measured by scanning a cross section of the body 110 in the first direction and the second direction using a Scanning Electron Microscope (SEM) having a magnification of 10000. More specifically, the average value can be obtained by: in the scanned image, the thicknesses of the internal electrodes 121 and 122 at 30 points equidistantly spaced in the second direction are averaged. The 30 points equidistantly spaced apart may be specified in the capacitance forming portion Ac. Further, when the average value is measured by extending the measurement of the average value to ten internal electrodes 121 and 122, the average thickness of the internal electrodes 121 and 122 can be more generalized. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used to obtain the average thickness of the inner electrodes 121 and 122, even if not described in the present disclosure.

In an example embodiment, the average thickness te of at least one of the plurality of internal electrodes 121 and 122 may be smaller than the average thickness td of at least one of the plurality of dielectric layers 111, and preferably, the average thickness te of the internal electrodes may be smaller than the average thickness td of the dielectric layers.

Accordingly, miniaturization and high capacitance of the multilayer electronic assembly 100 can be obtained by reducing the average thickness te of the internal electrodes, and insulation resistance characteristics and withstand voltage characteristics can be improved by forming the dielectric layer 111 with a sufficiently thick thickness. In particular, in the example embodiment, since the internal electrodes 121 and 122 include nickel (Ni), strontium (Sr), and ruthenium (Ru), the internal electrodes 121 and 122 may be further thinned, so that the effect of improving the insulation resistance characteristic and the withstand voltage characteristic may be remarkable.

Hereinafter, an example of the meaning of the average thickness of the inner electrode and the standard deviation of the thickness of the inner electrode and a method of measuring the average thickness of the inner electrode and the standard deviation of the thickness of the inner electrode in the example embodiment will be described in more detail with reference to fig. 5.

For example, the average thickness te of the first inner electrode 121 may be an average of dimensions (te 1, te2, te3, te4, te5, etc.) in the first direction measured at five or more points (line a) of the first inner electrode 121 equidistantly spaced in the second direction in the region shown in fig. 5. When the average measurement is extended to 10 or more internal electrodes 121 and 122, the average size of the internal electrodes 121 and 122 in the first direction may be more generalized.

The standard deviation of thickness (σte) of the first internal electrode can be obtained by: the dimensions (te 1, te2, te3, te4, te5,) in the first direction measured at five or more points (line a) of the first inner electrode 121 equidistantly spaced in the second direction are summed with values obtained by squaring differences (te-te 1, te-te2, te-te3, te-te4, te-te5,) of the average thickness te of the first inner electrode 121 measured by the above method, and dividing the values by the number of measurement positions and then square root.

In this case, the ratio of the standard deviation (σte) of the thickness of the inner electrode to the average thickness te of the inner electrode (σte/te) may be referred to as a thickness variation Coefficient (CV) of the inner electrode.

In an example embodiment, the percentage of the thickness variation coefficient (CV%) of the inner electrode may be greater than 0% and equal to or less than 43% (preferably, equal to or less than 30%), the thickness variation coefficient of the inner electrode being a ratio (σte/te) of a standard deviation (σte) of the thickness of the inner electrode to an average thickness te of at least one of the plurality of inner electrodes.

When the percentage of the thickness variation coefficient of the inner electrode is 43% or less, uniformity of the thickness of the inner electrode can be improved.

When the percentage of the thickness variation coefficient of the internal electrode exceeds 43%, the uniformity of the thickness of the internal electrode may be deteriorated and the interface bonding characteristics with the adjacent dielectric layer 111 may be deteriorated, so that delamination between the internal electrode and the dielectric layer may occur and a step difference may occur due to an increase in the number of layers stacked.

Fig. 6 shows an enlarged view of a portion of the capacitance forming portion Ac in a cross section in the first direction and the second direction of the multilayer electronic component according to the example embodiment.

In an example embodiment, the internal electrodes 121 and 122 may include electrode regions 121a and 122a (including conductive material) and break regions 121b and 122b (excluding (not including) conductive material), and when a ratio of a sum of lengths of the electrode regions (l1+l2+l3+l4+), to a total length L of the internal electrodes is defined as connectivity (C) of the internal electrodes, at least one of the plurality of internal electrodes may satisfy 90% +.c, more preferably 95% +.c.

Here, the total length L of the inner electrode may refer to the size of the region including the electrode regions 121a and 122a and the break regions 121b and 122b in the second direction in the layers of the inner electrodes 121 and 122, and the electrode region length (L1, L2, L3, L4,) may refer to the size of the region including the electrode regions 121a and 122a and not including the break regions 121b and 122b in the second direction in the layers of the inner electrodes 121 and 122. The connectivity (C) of the inner electrodes may be more generalized by extending the measurement to more than 10 inner electrodes 121 and 122. The length may be measured by scanning a section of the body 110 in the first direction and the second direction using a Scanning Electron Microscope (SEM). Even if not described in the present disclosure, other methods and/or tools as understood by those of ordinary skill in the art may be used to obtain connectivity C of the inner electrode.

The electrode regions 121a and 122a and the disconnection regions 121b and 122b can be distinguished by contrast differences in images observed with a scanning electron microscope at a magnification of 10000 times or more, and contrast differences can be distinguished more easily by an image program.

When the connectivity (C) of the internal electrode is 90% or more, the capacitance improvement effect can be more excellent, and the step difference due to the increase in the number of stacks can be suppressed.

When the average thickness te of the internal electrode is 0.3 μm or less, the effect of improving the connectivity (C) of the internal electrode may be more excellent.

The body 110 may include cover portions 112 and 113 provided on both end surfaces of the capacitance forming portion Ac in the first direction.

More specifically, the body 110 may include an upper cover 112 disposed above the capacitance forming portion Ac in the first direction and a lower cover 113 disposed below the capacitance forming portion Ac in the first direction.

The upper and lower cover parts 112 and 113 may be formed by stacking a single dielectric layer 111 or two or more dielectric layers 111 on the upper and lower surfaces of the capacitance forming part Ac, respectively, in the first direction, and may prevent the internal electrodes 121 and 122 from being damaged due to physical stress or chemical stress.

The upper and lower cover parts 112 and 113 do not include the inner electrodes 121 and 122, and may include the same material as that of the dielectric layer 111. That is, the upper and lower cover parts 112 and 113 may include a ceramic material, for example, barium titanate (BaTiO ₃) ceramic material.

The thickness tc of the cover portions 112 and 113 may not need to be limited to any particular example.

However, in order to easily obtain miniaturization and high capacitance of the multilayer electronic component, the thickness tc of the covering portions 112 and 113 may be 100 μm or less, preferably 30 μm or less. More preferably, the thickness may be 20 μm or less.

Here, the thickness tc of the cover portions 112 and 113 may refer to the dimension of the cover portions 112 and 113 in the first direction. Further, the thickness tc of the covering portions 112 and 113 may refer to an average thickness tc of the covering portions 112 and 113, and may refer to an average size of the covering portions 112 and 113 in the first direction.

The average thickness of the cover parts 112 and 113 may be measured by scanning a cross section of the body 110 in the first direction and the second direction at a magnification of 10000 using a Scanning Electron Microscope (SEM). More specifically, the average value can be obtained by: in the scanned image, the thickness of the covering portion at 30 points equidistantly spaced in the second direction was averaged. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used to obtain the average thickness of the covers 112 and 113, even if not described in this disclosure.

Further, the average size of the cover parts in the first direction measured by the above-described method may be substantially the same as the average size of the cover parts in the first direction in the cross section of the main body 110 in the first direction and the third direction.

The side edge portions 114 and 115 may be provided on both end surfaces of the capacitance forming portion Ac in the third direction.

More specifically, the side edge portions 114 and 115 may include a first side edge portion 114 and a second side edge portion 115 provided on both end surfaces of the capacitance forming portion Ac in the third direction, respectively. That is, the side edge portions 114 and 115 may be provided on both end surfaces of the capacitance forming portion Ac in the third direction.

As shown in fig. 4, the side edge portions 114 and 115 may refer to: with respect to the cross section of the body 110 in the first direction and the third direction, the regions between the two end surfaces of the first and second internal electrodes 121 and 122 in the third direction and the boundary surface of the body 110 are located.

The side edge portions 114 and 115 may be mainly used to prevent the internal electrodes 121 and 122 from being damaged due to physical stress or chemical stress.

The side edge portions 114 and 115 may be formed by forming the inner electrodes 121 and 122 by coating a conductive paste on the ceramic green sheet on the areas other than the areas where the side edge portions 114 and 115 are formed. In order to suppress the step difference caused by the inner electrodes 121 and 122, the side edge portions 114 and 115 may be formed by: the internal electrodes 121 and 122 are laminated on each other, the laminated internal electrodes 121 and 122 are cut so as to be exposed to both end surfaces of the capacitance forming portion Ac in the third direction, and a single dielectric layer 111 or two or more dielectric layers 111 are laminated on both end surfaces of the capacitance forming portion Ac in the third direction.

The first and second side edge portions 114 and 115 do not include the inner electrodes 121 and 122, and may include the same material as that of the dielectric layer 111. That is, the first and second side edge portions 114 and 115 may include a ceramic material, such as barium titanate (BaTiO ₃) ceramic material.

Further, the width wm of the first side edge portion 114 and the second side edge portion 115 may not need to be limited to any particular example.

However, in order to easily obtain miniaturization and high capacitance of the multilayer electronic component 100, the width wm of the side edge portions 114 and 115 may be 100 μm or less, preferably 30 μm or less, and more preferably 20 μm or less in an ultra-small product.

Here, the width wm of the side edge portions 114 and 115 may refer to the dimension of the side edge portions 114 and 115 in the third direction. Further, the width wm of the side edge portions 114 and 115 may refer to the average width wm of the side edge portions 114 and 115 and the average size of the side edge portions 114 and 115 in the third direction.

The average size of the side edge portions 114 and 115 in the third direction can be measured by scanning a cross section of the main body 110 in the first direction and the third direction using a Scanning Electron Microscope (SEM) at a magnification of 10000. More specifically, the average size may be an average value obtained by: in the scanned image, the dimensions in the third direction at 10 points equidistantly spaced in the first direction of one of the opposite side edge portions are averaged. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used to obtain the average dimension of the side edge portions 114 and 115 in the third direction, even if not described in this disclosure.

In an example embodiment, the multi-layered electronic assembly 100 may have two external electrodes 131 and 132, but the number or shape of the external electrodes 131 and 132 may vary according to the form of the internal electrodes 121 and 122 or other purposes.

The external electrodes 131 and 132 may be disposed on the body 110, and may be connected to the internal electrodes 121 and 122.

More specifically, the external electrodes 131 and 132 may be disposed on the third surface 3 and the fourth surface 4 of the body 110, respectively, and may include first and second external electrodes 131 and 132 connected to the first and second internal electrodes 121 and 122, respectively. That is, the first external electrode 131 may be disposed on the third surface 3 of the body and may be connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body and may be connected to the second internal electrode 122.

The external electrodes 131 and 132 may be formed using any material having conductivity, such as metal, and a specific material may be determined in consideration of electrical characteristics and structural stability, and the external electrodes 131 and 132 may have a multi-layered structure.

For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a disposed on the body 110, and plating layers 131b and 132b disposed on the electrode layers 131a and 132 a.

As more specific examples of the electrode layers 131a and 132a, the electrode layers 131a and 132a may be sintered electrodes including a first conductive metal and glass or resin-based electrodes including a second conductive metal and resin.

Further, the electrode layers 131a and 132a may have a form of a sintered electrode and a resin-based electrode sequentially formed on the body.

Further, the electrode layers 131a and 132a may be formed by transferring a sheet including a conductive metal onto the body or by transferring a sheet including a conductive metal onto the sintered electrode.

The conductive metal for the electrode layers 131a and 132a is not limited to any particular example as long as the material can be electrically connected with the internal electrodes 121 and 122 to form a capacitance. For example, the conductive metal may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, but example embodiments thereof are not limited thereto. The electrode layers 131a and 132a may be formed as follows: a conductive paste prepared by applying a frit to a conductive metal powder is coated and sintered.

The plating layers 131b and 132b may improve the mounting characteristics.

The types of the plating layers 131b and 132b are not limited to any particular example, and may be single-layer plating layers 131b and 132b including at least one of nickel (Ni), tin (Sn), palladium (Pd), and alloys thereof, or may include at least two layers.

As more specific examples of the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers formed on the electrode layers 131a and 132a, ni plating layers and Sn plating layers sequentially formed on the electrode layers 131a and 132a, or Sn plating layers, ni plating layers and Sn plating layers sequentially formed on the electrode layers 131a and 132 a. In addition, the plating layers 131b and 132b may include a plurality of Ni plating layers and/or a plurality of Sn plating layers.

The dimensions of the multilayer electronic assembly 100 may not need to be limited to any particular example.

However, in order to obtain both miniaturization and high capacitance, it may be necessary to reduce the thickness of the dielectric layer and the internal electrode to increase the number of stacks, so that the effect in the example embodiment may be excellent in the multilayer electronic component 100 having a size of 1005 (length×width, 1.0mm×0.5 mm) or 0603 (length×width, 0.6mm×0.3 mm) or smaller.

Method for manufacturing multilayer electronic component

In the following description, example embodiments will be described in more detail.

A method of manufacturing a multilayer electronic component according to an example embodiment may include: forming a laminate by laminating a plurality of ceramic green sheets on which internal electrode patterns are formed and cutting the plurality of ceramic green sheets; sintering the laminate; and forming an external electrode on the sintered laminate, wherein an internal electrode pattern is formed by depositing Ni and SrRuO ₃ using a sputtering method, and wherein the content of SrRuO ₃ is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of Ni.

First, a laminate may be formed by laminating a plurality of ceramic green sheets on which internal electrode patterns are formed and cutting the plurality of ceramic green sheets.

More specifically, a plurality of first stripe-shaped internal electrode patterns may be formed on the ceramic green sheet with a predetermined distance therebetween. The plurality of first stripe-shaped internal electrode patterns may be formed in parallel with each other, and the ceramic green sheet on which the first internal electrode patterns are formed may be defined as a first ceramic green sheet. Further, a plurality of second stripe-shaped internal electrode patterns may be formed on another ceramic green sheet at a predetermined distance, and the ceramic green sheet formed with the second internal electrode patterns may be defined as a second ceramic green sheet.

The ceramic green sheet may include a ceramic slurry including a ceramic material, an organic solvent, and an organic binder. The ceramic material may be a material having a high dielectric constant, and the type of material is not limited to any particular example, but a perovskite (ABO ₃) -based material may be used, for example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material may be used. The barium titanate-based material may include BaTiO ₃ -based ceramic powder, and examples of the ceramic powder may include BaTiO ₃ and (Ba_1-xCa_x)TiO₃(0<x<1)、Ba(Ti_1-yCa_y)O₃(0<y<1)、(Ba_1-xCa_x)(Ti_1-yZr_y)O₃(0<x<1,0<y<1) or Ba (Ti _1-yZr_y)O₃ (0 < y < 1) in which calcium (Ca) and/or zirconium (Zr) are partially solid-dissolved in BaTiO ₃.

The internal electrode pattern may be formed by coating a paste for the internal electrode on the ceramic green sheet using a screen printing method or a gravure printing method, but example embodiments thereof are not limited thereto.

When an ultra-thin internal electrode pattern (e.g., thickness of 0.3 μm or less) is formed, the screen printing method may have a limitation in obtaining target connectivity and uniformity of the internal electrode. In this case, when the above sputtering method and deposition method are used, there are effects of obtaining an inner electrode of an ultra-thin thickness and improving connectivity and uniformity.

In an example embodiment, the internal electrode pattern may be formed by depositing nickel (Ni) and strontium ruthenium oxide (SrRuO ₃) using a sputtering method.

Here, strontium ruthenium oxide (SrRuO ₃) may be added only to the inner electrode pattern to serve as a material added for improving connectivity of the inner electrode, and may not be included in the ceramic green sheets (for example, at least one ceramic green sheet of the plurality of ceramic green sheets does not contain SrRuO ₃), but example embodiments thereof are not limited thereto.

In the example embodiment, nickel (Ni) may be used as an example of the conductive metal for forming the internal electrode pattern, but example embodiments thereof are not limited thereto, and any material having excellent conductivity may be used.

In the sputtering method, nickel (Ni) may be deposited using a first sputter gun, and strontium ruthenium oxide (SrRuO ₃) may be deposited using a second sputter gun.

When nickel (Ni) and strontium ruthenium oxide (SrRuO ₃) are deposited using different sputter guns, the strontium ruthenium oxide (SrRuO ₃) can be uniformly distributed between nickel (Ni) metal particles so that necking between nickel (Ni) metal particles or aggregation of internal electrodes can be prevented, which can effectively improve connectivity of the internal electrodes.

In this case, when nickel (Ni) and strontium ruthenium oxide (SrRuO ₃) are simultaneously deposited using the first and second sputter guns, necking between nickel (Ni) metal particles or aggregation of the inner electrodes can be effectively prevented, and the heat shrinkage initiation temperature can be improved, so that connectivity of the inner electrodes can be improved.

The sputtering method may be used under the following conditions or methods, but example embodiments thereof are not limited thereto, and any one of various conditions to which the sputtering method may be applied may be used.

First, an internal electrode pattern may be deposited on a ceramic green sheet using a sputtering apparatus mounted with two or more target guns. In this case, a stainless steel (SUS) mask may be provided on the ceramic green sheet to form the internal electrode pattern, and the internal electrode pattern to be formed may be deposited using a sputtering apparatus. In this case, nickel (Ni) and strontium ruthenium oxide (SrRuO ₃) can be simultaneously deposited while maintaining a vacuum of 10 ^-5 torr or more as a pressure condition.

The thickness of the internal electrode patterns may be proportional to the deposition time. That is, the thickness of the internal electrode pattern may be adjusted by adjusting the deposition time. The thickness of the inner electrode controlled by deposition time may refer to: for example, the thickness of the inner electrode pattern may increase as the deposition time increases, and the thickness of the inner electrode pattern may decrease as the deposition time decreases. However, proportionality may not necessarily mean proportionality.

After checking the deposition rate for each output of each material, the deposition rates of nickel (Ni) and strontium ruthenium oxide (SrRuO ₃) can be controlled by the output values.

In this case, the content of strontium ruthenium oxide (SrRuO ₃) may be more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of nickel (Ni).

Here, the content of strontium ruthenium oxide (SrRuO ₃) may be 8.5 parts by weight or less, 7.0 parts by weight or less, or 5.0 parts by weight or less, and may be 0.1 parts by weight or more, 0.5 parts by weight or more, 1.5 parts by weight or more, or 2.5 parts by weight or more, based on 100 parts by weight of nickel (Ni).

"Parts by weight" may refer to relative amounts based on the standard amounts of the substance. For example, 5.0 parts by weight of strontium ruthenium oxide (SrRuO ₃) based on 100 parts by weight of nickel (Ni) may refer to 5.0g of strontium ruthenium oxide (SrRuO ₃) per 100g of nickel (Ni).

When the content of strontium ruthenium oxide (SrRuO ₃) is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of nickel (Ni), connectivity of the internal electrodes 121 and 122 may be improved and a uniform thickness may be formed.

When the content of strontium ruthenium oxide (SrRuO ₃) is more than 10.0 parts by weight based on 100 parts by weight of nickel (Ni), sintering may not be completed or dielectric characteristics may be deteriorated. Therefore, the content of strontium ruthenium oxide (SrRuO ₃) may be preferably less than 10.0 parts by weight, and more preferably may be less than 5.0 parts by weight, based on 100 parts by weight of nickel (Ni).

The first ceramic green sheet and the second ceramic green sheet may be alternately laminated such that the first stripe-shaped internal electrode patterns and the second stripe-shaped internal electrode patterns may be alternately laminated.

In this case, a portion where a capacitor is formed by stacking ceramic green sheets on which an internal electrode pattern is printed in the first direction may be defined as a green sheet capacitor forming portion, and cover portion green sheets may be provided on both end surfaces of the green sheet capacitor forming portion in the first direction. More specifically, the cover green sheet may include a first cover green sheet disposed above the green sheet capacitance forming portion in the first direction and a second cover green sheet disposed below the green sheet capacitance forming portion in the first direction.

Thereafter, while undergoing the sintering process, the first bar-shaped internal electrode pattern may become the first internal electrode 121, and the second bar-shaped internal electrode pattern may become the second internal electrode 122. Further, the first cover green sheet may become the upper cover 112, and the second cover green sheet may become the lower cover 113.

The thickness of the first ceramic green sheet and the second ceramic green sheet may not be limited to any particular example.

However, in order to easily obtain miniaturization and high capacitance of the multilayer electronic component, the thickness of the first ceramic green sheet and the second ceramic green sheet may be 0.6 μm or less, more preferably 0.4 μm or less.

Here, the thickness of the first ceramic green sheet and the second ceramic green sheet may refer to the dimensions of the first ceramic green sheet and the second ceramic green sheet in the first direction.

The thicknesses of the first and second internal electrode patterns may not be limited to any particular example.

However, in order to easily obtain miniaturization and high capacitance of the multilayer electronic component, the thicknesses of the first and second internal electrode patterns may be greater than 0 μm and equal to or less than 0.4 μm, preferably may be equal to or less than 0.3 μm, and more preferably may be equal to or less than 0.15 μm.

The first ceramic green sheet on which the plurality of first stripe-shaped internal electrode patterns parallel to each other are printed and the second ceramic green sheet on which the plurality of second stripe-shaped internal electrode patterns parallel to each other are printed may be alternately laminated, thereby forming a laminate of ceramic green sheets.

More specifically, lamination may be performed such that the central portions of the plurality of first stripe-shaped internal electrode patterns printed on the first ceramic green sheet and the intervals between the plurality of second stripe-shaped internal electrode patterns printed on the second ceramic green sheet overlap each other. Here, the region where the first internal electrode pattern and the second internal electrode pattern overlap each other may be a green sheet capacitance forming portion.

The ceramic green sheet laminate may be cut through the plurality of first stripe-shaped internal electrode patterns and the plurality of second stripe-shaped internal electrode patterns. That is, the ceramic green sheet laminate may be cut along cutting lines orthogonal to each other.

In example embodiments, the cut ceramic green sheet laminate may be referred to as a laminate, and one skilled in the art will be able to understand the description without difficulty.

More specifically, the first and second bar-shaped internal electrode patterns may be cut in the second direction, and the first and second bar-shaped internal electrode patterns may be divided into a plurality of internal electrodes having a constant size in the third direction. In this case, the laminated ceramic green sheet may also be cut into a plurality of parts together with the internal electrode patterns, thereby preparing a plurality of laminated bodies. The dimensions of the cut ceramic green sheet and the cut internal electrode pattern in the third direction may be the same.

In addition, cutting may be performed along individual cut lines to accommodate individual body sizes. That is, a plurality of laminates may be formed by cutting a bar-shaped ceramic green sheet laminate along a cutting line into individual ceramic body sizes before attaching an edge portion green sheet (described later).

That is, the bar-shaped ceramic green sheet laminate may be cut along a cutting line passing through the interval between the central portion of the first bar-shaped internal electrode pattern and the second bar-shaped internal electrode pattern. Thus, the end portions of the first and second internal electrodes may be alternately exposed to the cut-out surface.

Thereafter, a side edge portion green sheet may be formed on the side surface of the laminate in the third direction.

More specifically, the first side edge portion green sheet may be formed on one surface of the laminate in the third direction, and the second side edge portion green sheet may be formed on the other surface of the laminate in the third direction.

Thereafter, the method of manufacturing the multilayer electronic assembly may include sintering the laminate.

When sintering the laminate, sintering may be performed in a reducing atmosphere having a hydrogen concentration of 0.1vol% or more and 0.5vol% or less, preferably in an atmosphere having a hydrogen concentration of 0.11 vol%.

The sintering temperature may be, for example, 1150 ℃ or more and 1300 ℃ or less, and preferably may be 1200 ℃ or more and 1250 ℃ or less.

Thereafter, the method of manufacturing the multilayer electronic component may include forming external electrodes on the sintered laminate.

More specifically, a first external electrode paste may be coated on one surface (e.g., the third surface 3) of the laminate in the second direction, and a second external electrode paste may be coated on the other surface (e.g., the fourth surface 4) of the laminate in the second direction, and the electrode layers 131a and 132a may be formed by sintering the first external electrode paste and the second external electrode paste.

In addition, a plating process may be further performed such that the external electrodes 131 and 132 may include plating layers 131b and 132b.

The descriptions of the external electrodes 131 and 132 may be the same as those in the foregoing example embodiments, and thus will not be provided.

Although the exemplary embodiments have been described in detail above, the exemplary embodiments are not limited to the above-described embodiments and the accompanying drawings, but are intended to be defined by the appended claims. Accordingly, those skilled in the art will make various alternatives and modifications within the technical spirit of the present disclosure described in the claims, which also fall within the scope of the present disclosure.

Hereinafter, example embodiments will be described in more detail, which is helpful in understanding the present disclosure in detail, and the scope of the present invention is not limited thereto.

Example (example)

The following table 1 lists connectivity (C), average thickness te, standard deviation of thickness (σte) and average size (GD) and standard deviation of size (σgd) of dielectric grains included in the dielectric layer of the nickel (Ni) inner electrode according to the deposition content of strontium ruthenium oxide (SrRuO ₃).

More specifically, test example 1 was prepared by coating nickel (Ni) internal electrode paste, which is a general internal electrode forming method, instead of by applying a sputtering method, and strontium ruthenium oxide (SrRuO ₃) was not added. Fig. 7A is an image obtained by capturing a capacitance forming portion of the sample of test example 1.

In test example 2, an internal electrode was formed by applying a sputtering method, and 2.5 parts by weight of strontium ruthenium oxide (SrRuO ₃) based on 100 parts by weight of nickel (Ni) was simultaneously deposited with nickel (Ni), thereby forming a nickel (Ni) internal electrode. Fig. 7B is an image of the capacitance forming portion of the sample of test example 2.

In test example 3, an internal electrode was formed by applying a sputtering method, and 5.0 parts by weight of strontium ruthenium oxide (SrRuO ₃) based on 100 parts by weight of nickel (Ni) was simultaneously deposited with nickel (Ni), thereby forming a nickel (Ni) internal electrode. Fig. 7C is an image obtained by capturing the capacitance forming portion of the sample of test example 3.

In test example 4, an internal electrode was formed by applying a sputtering method, and 10.0 parts by weight of strontium ruthenium oxide (SrRuO ₃) with respect to 100 parts by weight of nickel (Ni) was simultaneously deposited with nickel (Ni), thereby forming a nickel (Ni) internal electrode. Fig. 7D is an image obtained by capturing the capacitance forming portion of the sample of test example 4.

The addition amount of strontium ruthenium oxide (SrRuO ₃) for each test example was the content before sintering, and corresponds to the deposition content using the sputtering method (except for test example 1).

The mass percentages (wt%) of nickel (Ni), strontium (Sr) and ruthenium (Ru) are contents of elements measured by SEM-EDS elemental analysis of the internal electrode in the capacitance forming portion of the sample after sintering, and the sum of the contents of nickel (Ni), strontium (Sr) and ruthenium (Ru) is converted to 100wt% and listed in table 1.

TABLE 1

In test example 1, the connectivity (C) of the internal electrode was 62%, and was poor compared with test examples 2 to 4 to which SrRuO ₃ was added. This is because a method of coating the internal electrode paste is applied and SrRuO ₃ is not added. Further, the average thickness te of the internal electrode was 446nm, so that an internal electrode having an ultra-thin thickness (300 nm or less) was not obtained.

In test example 2 to which 2.5 parts by weight of SrRuO ₃ was added, 98.45wt% Ni, 0.40wt% Sr and 1.15wt% Ru were detected at the inner electrode, indicating that the (sr+ru)/(ni+sr+ru) value was 1.55 (wt%). The average thickness te of the inner electrode was 217nm, the standard deviation of thickness (σte) was 65nm, and the connectivity (C) was 96%, so that the inner electrode had an ultra-thin thickness and a uniform thickness was obtained as compared with test example 1. The average size (GD) of the dielectric grains included in the dielectric layer was observed to be 250nm and the standard deviation of size (σgd) was 54.1nm, probably because grain growth of the dielectric grains was promoted due to Sr diffusion of SrRuO ₃ into the dielectric layer during the sintering process.

Fig. 8A to 8D are images of the capacitance forming portion of test example 2 captured by SEM and images obtained by EDS elemental analysis of a part of the region. More specifically, fig. 8A is an SEM image of the internal electrode and the dielectric layer, and fig. 8B to 8D are images of oxygen (O) element, strontium (Sr) element, and ruthenium (Ru) element included in the rectangular region of fig. 8A analyzed by EDS. The region with a large content of oxygen (O) element detected in fig. 8B corresponds to the dielectric layer, and the region with a small content of oxygen (O) element corresponds to the internal electrode. Referring to fig. 8C, it can be confirmed that strontium (Sr) element is concentrated in a part of the region of the inner electrode, and the strontium (Sr) element is uniformly detected even in the dielectric layer, which can indicate that grain growth of the dielectric grains is affected. Referring to fig. 8D, it can be confirmed that ruthenium (Ru) element is detected from the inner electrode and the dielectric layer, but more ruthenium (Ru) is detected from the inner electrode than from the dielectric layer, which may indicate that less diffusion of ruthenium (Ru) into the dielectric layer occurs during the sintering process.

In test example 3 to which 5.0 parts by weight of SrRuO ₃ was added, 96.39wt% of Ni, 1.18wt% of Sr, and 2.43wt% of Ru were detected in the inner electrode, which may indicate that the (sr+ru)/(ni+sr+ru) value was 3.61wt%. The average thickness te of the inner electrode was 208nm, the standard deviation of thickness (σte) was 88nm, and the connectivity (C) was 97%, so that the inner electrode having an ultra-thin thickness was formed and a uniform thickness was obtained as compared with test example 1. The average size (GD) of the dielectric grains included in the dielectric layer was 90nm, and a standard deviation of size (σgd) of 33.6nm was observed, which may indicate that the uniform grain growth of the dielectric grains was affected due to Sr of SrRuO ₃ diffusing into the dielectric layer during the sintering process, but the grain growth was prevented due to the addition of a relatively small amount of Sr instead of an appropriate content.

Fig. 9A to 9D are images of the capacitance forming portion of test example 3 captured by SEM and images obtained by EDS elemental analysis of a partial region. More specifically, fig. 9A is an SEM image of the internal electrode and the dielectric layer, and fig. 9B to 9D are images of oxygen (O) element, strontium (Sr) element, and ruthenium (Ru) element included in the rectangular region of fig. 9A analyzed by EDS. The region with a large content of oxygen (O) element detected in fig. 9B corresponds to the dielectric layer, and the region with a small content of oxygen (O) element corresponds to the internal electrode. Referring to fig. 9C, it can be confirmed that strontium (Sr) element is concentrated in a part of the region of the inner electrode, and the strontium (Sr) element is uniformly detected in the dielectric layer, which can indicate that grain growth of the dielectric grains is affected. Referring to fig. 9D, it can be confirmed that ruthenium (Ru) element is detected from the inner electrode and the dielectric layer, but more ruthenium (Ru) is detected from the inner electrode than from the dielectric layer, which may indicate that less diffusion of ruthenium (Ru) into the dielectric layer occurs during the sintering process.

Although not listed in the table, in test example 4 to which 10.0 parts by weight of SrRuO ₃ was added, the connectivity (C) of the internal electrode was 99% (this is excellent), the thickness te of the internal electrode was 201nm, and the standard deviation (σte) of the thickness was 46nm, thereby forming an internal electrode having an ultra-thin thickness and obtaining a uniform thickness. However, the standard deviation of the size (σgd) of the dielectric grains included in the dielectric layer has a uniform size of 27.8nm, but the average size (GD) of the dielectric grains is 66nm (this is relatively small), and sintering cannot be performed completely, so that dielectric characteristics cannot be measured. This is because: due to the Sr excess, grain growth of the dielectric grains is excessively suppressed by Sr diffusing into the dielectric layer region.

According to the above-described exemplary embodiments, miniaturization and high capacitance of the multilayer electronic component can be achieved.

In addition, the thickness of the inner electrode can be reduced.

In addition, connectivity of the internal electrode can be improved.

In addition, the thickness uniformity of the internal electrode can be improved.

In addition, the uniformity of the dielectric die can be improved.

Although example embodiments have been shown and described above, it will be readily appreciated by those skilled in the art that modifications and variations may be made without departing from the scope of the disclosure as defined by the appended claims.

Claims

1. A multilayer electronic assembly comprising:

A body including a plurality of dielectric layers and a plurality of internal electrodes; and

An external electrode disposed on the main body,

Wherein at least one of the plurality of internal electrodes includes Ni, sr, and Ru, and an average content of (sr+ru)/(ni+sr+ru) is more than 0wt% and less than 8.40wt%, wherein the average content of (sr+ru)/(ni+sr+ru) refers to a sum of mass percentages of Sr and Ru when the sum of mass percentages of Ni, sr, and Ru is converted to 100 wt%.

2. The multilayer electronic component of claim 1, wherein the average content of (sr+ru)/(ni+sr+ru) is greater than 0wt% and less than or equal to 3.61wt%.

3. The multilayer electronic component according to claim 2, wherein the average content of (sr+ru)/(ni+sr+ru) is 1.55wt% or more and 3.61wt% or less.

4. The multilayer electronic component of claim 1, wherein an average content of Sr/(ni+sr+ru) of at least one of the plurality of internal electrodes is greater than 0wt% and less than 1.18wt%, wherein the average content of Sr/(ni+sr+ru) refers to a mass percentage of Sr when a sum of mass percentages of Ni, sr, and Ru is converted to 100 wt%.

5. The multilayer electronic component of claim 1, wherein an average content of Ru/(ni+sr+ru) of at least one of the plurality of internal electrodes is greater than 0wt% and less than 2.43wt%, wherein an average content of Ru/(ni+sr+ru) refers to a mass percentage of Ru when a sum of mass percentages of Ni, sr, and Ru is converted to 100 wt%.

6. The multilayer electronic component of claim 1, wherein an average thickness of at least one of the plurality of internal electrodes is 0.3 μιη or less.

7. The multilayer electronic assembly of claim 6, wherein an average thickness of at least one of the plurality of internal electrodes is 0.22 μm or less.

8. The multilayer electronic component of claim 1, wherein a percentage of a thickness variation coefficient of an internal electrode is 43% or less, the thickness variation coefficient of the internal electrode being a ratio of a standard deviation of a thickness of the at least one of the plurality of internal electrodes to an average thickness of the at least one of the plurality of internal electrodes.

9. The multilayer electronic component of claim 8, wherein the percentage of the thickness variation coefficient of the internal electrode is 30% or less.

10. The multilayer electronic component of claim 1,

Wherein the at least one of the plurality of internal electrodes comprises an electrode region comprising a conductive material and a break-away region free of the conductive material, and

Wherein the at least one of the plurality of internal electrodes satisfies 90% C, wherein C is connectivity of the at least one of the plurality of internal electrodes, and is defined as a ratio of a sum of lengths of the electrode regions to a total length of the at least one of the plurality of internal electrodes.

11. The multilayer electronic component of claim 1, wherein an average content of Ru included in the at least one of the plurality of internal electrodes is higher than an average content of Ru included in at least one of the plurality of dielectric layers.

12. The multilayer electronic assembly of claim 1, wherein the at least one of the plurality of internal electrodes comprises a plurality of metal grains, a metal grain boundary is disposed between metal grains adjacent to each other, and Ru is disposed on the metal grain boundary.

13. The multilayer electronic assembly of claim 1, wherein the at least one of the plurality of internal electrodes comprises an oxide comprising at least one element of Sr and Ru.

14. The multilayer electronic assembly of claim 1, wherein the at least one of the plurality of internal electrodes comprises at least one of a Ni-Sr alloy and a Ni-Ru alloy.

15. The multilayer electronic component of claim 1,

Wherein at least one dielectric layer of the plurality of dielectric layers comprises a plurality of dielectric grains, and

Wherein the average size of the dielectric grains is greater than or equal to 50nm and less than or equal to 300nm.

16. The multilayer electronic component of claim 1,

The percentage of the size variation coefficient of the dielectric crystal grains is less than or equal to 38%, and the size variation coefficient of the dielectric crystal grains is the ratio of the standard deviation of the sizes of the dielectric crystal grains to the average size of the dielectric crystal grains.

17. The multilayer electronic component of claim 16, wherein the dielectric grains have a coefficient of dimensional variation of 22% or less.

18. The multilayer electronic assembly of claim 1, wherein at least one dielectric layer of the plurality of dielectric layers comprises Sr.

19. The multilayer electronic assembly of claim 18, wherein the at least one of the plurality of dielectric layers comprises a plurality of dielectric grains, dielectric grain boundaries are disposed between dielectric grains adjacent to each other, and Sr is disposed on the dielectric grain boundaries.

20. The multilayer electronic assembly of claim 1, wherein an average thickness of at least one of the plurality of dielectric layers is 1.0 μιη or less.

21. The multilayer electronic assembly of claim 1, wherein an average thickness of the at least one of the plurality of internal electrodes is less than an average thickness of at least one of the plurality of dielectric layers.

22. A method of manufacturing a multilayer electronic assembly, the method comprising:

Forming a laminate by laminating a plurality of ceramic green sheets on which a plurality of internal electrode patterns are formed and cutting the plurality of ceramic green sheets;

Sintering the laminate; and

Forming an external electrode on the sintered laminate,

Wherein at least one of the plurality of internal electrode patterns is formed by depositing Ni and SrRuO ₃ using a sputtering method,

Wherein the content of SrRuO ₃ is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of Ni.

23. The method according to claim 22, wherein the content of SrRuO ₃ is more than 0 parts by weight and less than 5.0 parts by weight based on 100 parts by weight of Ni.

24. The method according to claim 23, wherein the content of SrRuO ₃ is 2.5 parts by weight or more and 5.0 parts by weight or less based on 100 parts by weight of Ni.

25. The method of claim 22, wherein the sputtering method comprises depositing Ni using a first sputter gun and depositing SrRuO ₃ using a second sputter gun.

26. The method of claim 25, wherein the sputtering method comprises depositing Ni and SrRuO ₃ simultaneously.

27. The method of claim 22, wherein at least one ceramic green sheet of the plurality of ceramic green sheets is free of SrRuO ₃.

28. The method of claim 22, wherein an average thickness of at least one of the plurality of internal electrode patterns is 0.3 μιη or less.

29. The method of claim 22, wherein the sputtering method further comprises forming the plurality of internal electrode patterns using a mask.

30. The method according to claim 22, wherein sintering of the laminate is performed in a reducing atmosphere having a hydrogen concentration of 0.1vol% or more.

31. The method according to claim 22, wherein sintering of the laminate is performed at a temperature of 1150 ℃ or more and 1300 ℃ or less.

32. The method of claim 22, wherein the sputtering is performed at a pressure of 10 ^-5 torr or greater.

33. The method of claim 22, wherein a thickness of the at least one of the plurality of internal electrode patterns is proportional to a sputter deposition time.

34. The method of claim 22, wherein at least one ceramic green sheet of the plurality of ceramic green sheets has an average thickness of 1.0 μm or less.

35. A method of manufacturing a multilayer electronic assembly, the method comprising:

A plurality of ceramic green sheets are laminated, wherein an internal electrode pattern is provided on at least one ceramic green sheet of the plurality of ceramic green sheets, the internal electrode pattern includes Ni and SrRuO ₃, and a content of SrRuO ₃ is more than 0 parts by weight and less than 10.0 parts by weight based on 100 parts by weight of Ni.

36. The method according to claim 35, wherein the content of SrRuO ₃ is more than 0 parts by weight and less than 5.0 parts by weight based on 100 parts by weight of Ni.

37. The method according to claim 35, wherein the content of SrRuO ₃ is 2.5 parts by weight or more and 5.0 parts by weight or less based on 100 parts by weight of Ni.

38. The method of claim 35, wherein at least one ceramic green sheet of the plurality of ceramic green sheets is free of SrRuO ₃.

39. The method of claim 35, further comprising depositing Ni and SrRuO ₃ on the at least one of the plurality of ceramic green sheets using a sputtering process.

40. The method of claim 39, wherein the sputtering comprises depositing Ni using a first sputter gun and depositing SrRuO ₃ using a second sputter gun.

41. The method of claim 39, wherein the sputtering comprises depositing Ni and SrRuO ₃ simultaneously.

42. A multilayer electronic assembly comprising:

An external electrode disposed on the main body,

Wherein at least one of the plurality of internal electrodes includes Ni, sr and Ru, and an average content of (Sr+Ru)/(Ni+Sr+Ru) is more than 0wt% and 3.61wt% or less, wherein the average content of (Sr+Ru)/(Ni+Sr+Ru) means a sum of mass percentages of Sr and Ru when the sum of mass percentages of Ni, sr and Ru is converted to 100wt%,

43. The multilayer electronic assembly of claim 42, wherein the at least one of the plurality of internal electrodes comprises an oxide comprising at least one element of Sr and Ru.

44. The multilayer electronic assembly of claim 42, wherein the at least one of the plurality of internal electrodes comprises at least one of a Ni-Sr alloy and a Ni-Ru alloy.

45. The multilayer electronic assembly of claim 42, wherein an average thickness of at least one of the plurality of internal electrodes is 0.3 μm or less.

46. The multilayer electronic assembly of claim 42, wherein at least one dielectric layer of the plurality of dielectric layers comprises Sr.

47. The multilayer electronic assembly of claim 46, wherein at least one of the plurality of dielectric layers comprises a plurality of dielectric grains, a dielectric grain boundary is disposed between dielectric grains adjacent to each other, and Sr is disposed on the dielectric grain boundary.