CN118231222A - Semiconductor structure, forming method thereof and forming method of chip - Google Patents
Semiconductor structure, forming method thereof and forming method of chip Download PDFInfo
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- CN118231222A CN118231222A CN202211646006.7A CN202211646006A CN118231222A CN 118231222 A CN118231222 A CN 118231222A CN 202211646006 A CN202211646006 A CN 202211646006A CN 118231222 A CN118231222 A CN 118231222A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 43
- 238000005520 cutting process Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 3
- 230000000903 blocking effect Effects 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 11
- 239000004593 Epoxy Substances 0.000 claims description 7
- 238000001746 injection moulding Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims 2
- 230000003139 buffering effect Effects 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 54
- 239000002184 metal Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 6
- 230000005856 abnormality Effects 0.000 description 5
- 238000003698 laser cutting Methods 0.000 description 5
- 238000012858 packaging process Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000011863 silicon-based powder Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
A semiconductor structure, a forming method thereof and a forming method of a chip, wherein the method comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between adjacent chip areas, and a first surface on which the device layer is positioned and a second surface opposite to the first surface; etching the wafer from the second surface to form a groove in the scribing channel region; and forming a buffer layer in the groove, wherein the toughness of the buffer layer material is greater than that of the wafer material, and the buffer layer can play a role in buffering in the cutting process of cutting the scribing channel regions from the first surface to separate the chip regions from each other and reduce the influence on the adjacent chip regions of the scribing channel regions, so that the quality of chips obtained by cutting is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure, a method for forming the same, and a method for forming a chip.
Background
The cutting is used as an inexhaustible or ring-lacking joint in the chip manufacturing process, the chips on the wafer are cut one by one, and the quality of the cutting process directly determines the yield of the chips.
The existing wafer cutting method mainly comprises mechanical cutting and laser cutting, but both technologies have certain limitations, and certain influences are generated on the performance or yield of the product. For example, mechanical dicing inevitably causes damage to the wafer structure, wasting wafer area, and if the damaged area is too large, the chip function may be disabled. Although the damage of laser cutting is small, the heat generated by the laser may cause the performance of the chip to change or even fail.
Therefore, the existing wafer dicing method needs to be further improved.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure, a forming method thereof and a forming method of a chip so as to improve the performance of the chip obtained by cutting.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a wafer, wherein the wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between adjacent chip areas, and a first surface where the device layer is positioned and a second surface opposite to the first surface; etching the wafer from the second face to form a groove in the scribe line region; and forming a buffer layer in the groove, wherein the toughness of the buffer layer material is greater than that of the wafer material.
Optionally, the forming method of the buffer layer includes: forming a buffer material layer on the surfaces of the grooves and the second surface; the buffer material layer is planarized until the second surface is exposed, forming a buffer layer.
Optionally, the method of forming the cushioning material layer includes an injection molding process.
Optionally, the recess forming process includes a plasma etching process.
Optionally, the material of the buffer layer comprises epoxy.
Optionally, the scribe line region includes an auxiliary region, and the device layer within the auxiliary region includes one or both of a test structure and an alignment mark; the groove is positioned in the substrate of the auxiliary area.
Optionally, the scribe line region further includes a protection region, and the protection region is located between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
Optionally, the scribe line region further includes a blocking region, the blocking region being located between the auxiliary region and the protection region; the device layer within the barrier region includes a barrier wall structure.
Alternatively, the width of the grooves ranges from 50 μm to 70 μm; the depth of the grooves ranges from 600 μm to 730 μm.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises the following steps: the wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between the adjacent chip areas, and a first surface on which the device layer is positioned and a second surface opposite to the first surface; a groove in the scribe line region, the groove extending from the second face to the first face; and the material toughness of the buffer layer is greater than that of the wafer.
Optionally, the material of the buffer layer comprises epoxy.
Optionally, the scribe line region includes an auxiliary region, and the device layer within the auxiliary region includes one or both of a test structure and an alignment mark; the groove is positioned in the substrate of the auxiliary area.
Optionally, the scribe line region further includes a protection region, and the protection region is located between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
Optionally, the scribe line region further includes a blocking region, the blocking region being located between the auxiliary region and the protection region; the device layer within the barrier region includes a barrier wall structure.
Alternatively, the width of the grooves ranges from 50 μm to 70 μm; the depth of the grooves ranges from 600 μm to 730 μm.
Correspondingly, the technical scheme of the invention also provides a chip forming method, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a wafer, the wafer comprises a substrate and a device layer positioned on the substrate, the wafer further comprises a plurality of chip areas and scribing channel areas between adjacent chip areas, and the wafer is provided with a first surface on which the device layer is positioned and a second surface opposite to the first surface; a groove in the scribe line region, the groove extending from the second face to the first face; the material toughness of the buffer layer is greater than that of the wafer; dicing the scribe line regions from the first side to separate the chip regions from each other to form a plurality of chips.
Optionally, the scribe line region includes an auxiliary region, and the device layer within the auxiliary region includes one or both of a test structure and an alignment mark; the groove is positioned in the substrate of the auxiliary area.
Optionally, the scribe line region further includes a protection region, and the protection region is located between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
Optionally, the scribe line region further includes a blocking region, the blocking region being located between the auxiliary region and the protection region; the device layer within the barrier region includes a barrier wall structure.
Alternatively, the width of the grooves ranges from 50 μm to 70 μm; the depth of the grooves ranges from 600 μm to 730 μm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the method for forming the semiconductor structure provided by the technical scheme of the invention, the wafer is etched from the second surface, the groove is formed in the scribing channel region, and the buffer layer is formed in the groove, so that the scribing channel region can be cut from the first surface in the subsequent packaging process of the formed semiconductor structure, the chip regions are mutually separated, the buffer layer can play a role in buffering in the cutting process, in addition, the buffer layer is easier to cut relative to the original wafer material, the influence on the adjacent chip regions of the scribing channel region (such as edge breakage abnormality of the chip region edge caused by cutting stress) can be reduced, and the quality of the chip obtained by cutting is improved.
In the semiconductor structure provided by the technical scheme of the invention, the grooves are positioned in the scribing channel region, the grooves extend from the second surface to the first surface, the buffer layer is arranged in the grooves, and the material toughness of the buffer layer is larger than that of the wafer, so that the scribing channel region can be cut from the first surface in the subsequent packaging process of the semiconductor structure, the chip regions are mutually separated, and in the cutting process, the buffer layer can play a role in buffering, in addition, compared with the original wafer material, the buffer layer is easier to cut, the influence on the adjacent chip regions of the scribing channel region (such as edge breakage abnormality of the chip region edge caused by cutting stress) can be reduced, and therefore, the quality of chips obtained by cutting is improved.
In the method for forming the chip provided by the technical scheme of the invention, the semiconductor structure is provided, the groove is positioned in the scribing channel region, the groove extends from the second surface to the first surface, the buffer layer is arranged in the groove, and the scribing channel region is cut from the first surface because the toughness of the material of the buffer layer is larger than that of the wafer, so that the buffer layer can play a role in buffering in the cutting process in the process of mutually separating the chip regions.
Drawings
FIGS. 1 and 2 are schematic views of a wafer dicing method;
Fig. 3 to 6 are schematic structural views of steps of a semiconductor structure forming method according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a chip forming method according to an embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background, the performance of chips obtained by the conventional wafer dicing method is in need of improvement. The analysis will now be described in connection with a wafer dicing method.
Fig. 1 and 2 are schematic structural views of a wafer dicing method.
Referring to fig. 1 and 2, fig. 1 is a schematic top view, and fig. 2 is a schematic cross-sectional view along the direction DD1 in fig. 1, including: providing a wafer, wherein the wafer comprises a plurality of chip areas 101, scribe lanes 102 are arranged between adjacent chip areas 101, and packaging strips 103 are arranged between the chip areas 101 and the scribe lanes 102; the wafer is diced along scribe lanes 102 using blade 104.
In the above method, the scribe line 102 is used for dicing the wafer into a plurality of chips, and the package strip 103 is used for protecting the performance of the chips from being damaged. Typically, a layer of material other than silicon, such as a metal interconnect layer, will be present within scribe line 102 due to the presence of test features (test keys), alignment marks (ALIGN MARK), and the like. During dicing, problems may occur that affect the reliability of the chip, or even lead to failure of the chip, such as: 1) Cutting the thicker metal layer 105 of the metal interconnect layer may cause the metal layer 105 to roll up and squeeze the dielectric layer 106 around the metal layer 105 to form a spall a, which may contact the package strip 103, causing the package strip 103 to be damaged, thereby allowing moisture to enter the chip; 2) With longer metal strips in the metal interconnect layer, longer wires B may peel off, which may cause the chip to fail in electrical performance if the wires B contact solder balls (bumps) or leads (bonding wires) during subsequent packaging, and may damage the package strips 103, resulting in moisture entering the chip. In summary, the existing way of mechanically dicing wafers needs to be further improved.
In order to solve the above problem, in another embodiment, a laser cutting method is adopted, however, the laser cutting may introduce high heat, and the high heat may cause damage to silicon, so that the sidewall of the cutting groove is uneven, and micro defects are easily generated, and the micro defects may be further deepened in subsequent packaging or reliability tests, and damage the adjacent packaging strip 103 structure, thereby affecting the chip performance, and even causing the chip electrical performance failure.
In order to solve the above problems, in the semiconductor structure, the method for forming the same and the method for forming the chip provided by the invention, the wafer is etched from the second surface, the groove is formed in the scribe line region, and the buffer layer is formed in the groove, so that the scribe line region can be cut from the first surface in the subsequent packaging process of the formed semiconductor structure, the buffer layer can play a role in buffering in the cutting process, in addition, the buffer layer is easier to cut compared with the original wafer material, the influence on the adjacent chip regions of the scribe line region (such as edge breakage abnormality of the edge of the chip region caused by cutting stress) can be reduced, and the quality of the chip obtained by cutting can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 6 are schematic structural views of steps of a semiconductor structure forming method according to an embodiment of the present invention.
Referring to fig. 3 and 4, fig. 3 is a schematic top view of a first surface of a wafer, fig. 4 is a schematic cross-sectional view along the direction EE1 in fig. 3, and a wafer is provided, the wafer includes a substrate 200 and a device layer 201 disposed on the substrate 200, the wafer further includes a plurality of chip regions 202 and scribe line regions 203 between adjacent chip regions 202, the wafer has a first surface 200a on which the device layer 201 is disposed, and a second surface 200b opposite to the first surface 200 a.
The scribe street region 203 includes an auxiliary region I, and the device layer within the auxiliary region I includes one or both of a test structure 204 and an alignment mark. In this embodiment, scribe line region 203 includes an auxiliary region I, and device layer 201 within auxiliary region I includes test structure 204.
In this embodiment, the scribe line region 203 further includes a protection region II, and the protection region II is located between the auxiliary region I and the chip region 202.
In this embodiment, the device layer 201 in the protection region II includes a guard ring structure 205.
In this embodiment, the scribe line region 203 further includes a blocking region III, and the blocking region III is located between the auxiliary region I and the protection region II.
In this embodiment, the device layer 201 within the blocking region III includes a blocking wall structure 206.
Referring to fig. 5, in the same view as fig. 4, the wafer is etched from the second surface 200b to form a recess 207 in the scribe line region 203.
In this embodiment, before forming the groove 207, further comprising: the first surface 200a of the wafer is directed to the surface of the stage 300, and the wafer is fixed to the surface of the stage 300.
In this embodiment, the recess 207 is located in the substrate 200 of the auxiliary area I. Since the grooves 207 are in the substrate 200, the substrate 200 is mostly of silicon material, and thus the grooves 207 are relatively easy to etch.
In this embodiment, the recess 207 forming process includes a plasma etching process.
In this embodiment, the width d of the groove 207 ranges from 50 μm to 70 μm. The width range is selected so that the width of the groove 207 is greater than the width of the saw at the time of cutting, and less than the width of the scribe lane region 203.
In this embodiment, the depth h of the groove 207 ranges from 600 μm to 730 μm. The depth range is selected so that the recess 207 does not expose the metal layer within the device layer 201 and maintains a certain safe thickness with the metal layer.
Referring to fig. 6, in the same view as fig. 4, a buffer layer 208 is formed in the recess 207, and the toughness of the buffer layer 208 is greater than that of the wafer material.
Because the toughness of the material of the buffer layer 208 is greater than that of the wafer material, in the subsequent packaging process of the formed semiconductor structure, the scribe line regions 203 can be cut from the first face 200a, so that the chip regions 202 are separated from each other, and in the cutting process, the buffer layer 208 can play a role in buffering.
In this embodiment, the method for forming the buffer layer 208 includes: forming a buffer material layer (not shown) on the surfaces of the groove 207 and the second face 200 b; the buffer material layer is planarized until the surface of the second surface 200b is exposed, forming a buffer layer 208.
In this embodiment, the method for forming the buffer material layer includes an injection molding process.
In this embodiment, the material of the buffer layer 208 includes epoxy. In other embodiments, the material of buffer layer 208 includes silicon powder.
In this embodiment, the process of planarizing the buffer material layer includes a mechanochemical polishing process.
In this embodiment, after forming the buffer layer 208, further includes: the wafer is removed from the carrier 300.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with continued reference to fig. 3 and 6, the semiconductor structure includes: the wafer comprises a substrate 200 and a device layer 201 positioned on the substrate 200, the wafer further comprises a plurality of chip areas 202 and scribe line areas 203 between the adjacent chip areas 202, and the wafer is provided with a first surface 200a on which the device layer 201 is positioned and a second surface 200b opposite to the first surface 200 a; a groove 207 (shown in fig. 5) located within the scribe line region 203, the groove 207 extending from the second face 200b toward the first face 200 a; and a buffer layer 208 positioned in the groove 207, wherein the material toughness of the buffer layer 208 is greater than that of the wafer.
Because the toughness of the material of the buffer layer 208 is greater than that of the wafer material, in the subsequent packaging process of the formed semiconductor structure, the scribe line regions 203 can be cut from the first face 200a, so that the chip regions 202 are separated from each other, and in the cutting process, the buffer layer can play a role in buffering, in addition, the buffer layer 208 is easier to cut compared with the original wafer material, and the influence on the adjacent chip regions 202 of the scribe line regions 203 (such as edge breakage abnormality of the chip region edge caused by cutting stress) can be reduced, thereby improving the quality of chips obtained by cutting.
In this embodiment, the material of the buffer layer 208 includes epoxy.
In this embodiment, scribe line region 203 includes an auxiliary region I, and device layer 201 within auxiliary region I includes one or both of test structure 204 and alignment mark; the recess 207 is located in the substrate 200 of the auxiliary area I.
In this embodiment, the scribe line region 203 further includes a protection region II, where the protection region II is located between the auxiliary region I and the chip region 202; the device layer 201 within the guard region II includes a guard ring structure 205.
In this embodiment, the scribe line region 203 further includes a blocking region III, where the blocking region III is located between the auxiliary region I and the protection region II; the device layer 201 within the blocking region III includes a blocking wall structure 206.
In the present embodiment, the width d of the groove 207 ranges from 50 μm to 70 μm; the depth h of the recess 207 ranges from 600 μm to 730 μm.
Correspondingly, the embodiment of the invention also provides a method for forming a chip by adopting the semiconductor structure, please continue to refer to fig. 3 and 6, and continue to refer to fig. 7 on the basis of fig. 6.
Fig. 7 is a schematic diagram of a chip forming method according to an embodiment of the present invention.
With continued reference to fig. 3 and 6, a semiconductor structure is provided, the semiconductor structure comprising: the wafer comprises a substrate 200 and a device layer 201 positioned on the substrate 200, the wafer further comprises a plurality of chip areas 202 and scribe line areas 203 between the adjacent chip areas 202, and the wafer is provided with a first surface 200a on which the device layer 201 is positioned and a second surface 200b opposite to the first surface 200 a; a groove 207 (shown in fig. 5) located within the scribe line region 203, the groove 207 extending from the second face 200b toward the first face 200 a; and a buffer layer 208 positioned in the groove 207, wherein the material toughness of the buffer layer 208 is greater than that of the wafer.
In this embodiment, the material of the buffer layer 208 includes epoxy.
In this embodiment, scribe line region 203 includes an auxiliary region I, and device layer 201 within auxiliary region I includes one or both of test structure 204 and alignment mark; the recess 207 is located in the substrate 200 of the auxiliary area I.
In this embodiment, the scribe line region 203 further includes a protection region II, where the protection region II is located between the auxiliary region I and the chip region 202; the device layer 201 within the guard region II includes a guard ring structure 205.
In this embodiment, the scribe line region 203 further includes a blocking region III, where the blocking region III is located between the auxiliary region I and the protection region II; the device layer 201 within the blocking region III includes a blocking wall structure 206.
In the present embodiment, the width d of the groove 207 ranges from 50 μm to 70 μm; the depth h of the recess 207 ranges from 600 μm to 730 μm.
Referring to fig. 7, dicing street regions 203 are cut from a first surface 200a, so that the chip regions 202 are separated from each other to form a plurality of chips (not shown).
Because the buffer layer 208 can play a role in buffering during the dicing process, in addition, the buffer layer 208 is easier to dicing than the original wafer material, and the influence on the chip area 202 adjacent to the scribe line area 203 (such as edge breakage abnormality of the chip area edge caused by dicing stress) can be reduced, thereby improving the quality of the chips obtained by dicing.
The process of cutting the scribe street regions 203 from the first face 200a includes a mechanical cutting process or a laser cutting process. In this embodiment, the dicing street 203 is cut from the first side 200a by a mechanical cutting process.
It should be noted that fig. 7 only illustrates the position of the saw 301 at a certain point in the cutting process in the mechanical cutting.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
Providing a wafer, wherein the wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between adjacent chip areas, and a first surface on which the device layer is positioned and a second surface opposite to the first surface;
Etching the wafer from the second surface to form a groove in the scribing channel region;
And forming a buffer layer in the groove, wherein the toughness of the buffer layer material is greater than that of the wafer material.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming a buffer layer comprises: forming a buffer material layer on the surfaces of the groove and the second face; and flattening the buffer material layer until the second surface is exposed, so as to form the buffer layer.
3. The method of forming a semiconductor structure of claim 2, wherein the method of forming the buffer material layer comprises an injection molding process.
4. The method of forming a semiconductor structure of claim 1, wherein the recess forming process comprises a plasma etching process.
5. The method of forming a semiconductor structure of claim 1, wherein the material of the buffer layer comprises an epoxy.
6. The method of forming a semiconductor structure of claim 1, wherein the scribe line region comprises an auxiliary region, the device layer within the auxiliary region comprising one or both of a test structure and an alignment mark; the groove is located in the substrate of the auxiliary area.
7. The method of forming a semiconductor structure of claim 6, wherein the scribe line region further comprises a protection region, the protection region being located between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
8. The method of forming a semiconductor structure of claim 7, wherein the scribe line region further comprises a blocking region between the auxiliary region and the protective region; the device layer within the blocking region includes a blocking wall structure.
9. The method of forming a semiconductor structure of claim 1, wherein the recess has a width in a range of 50 μm to 70 μm; the depth of the grooves ranges from 600 μm to 730 μm.
10. A semiconductor structure, comprising:
The wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between adjacent chip areas, wherein the wafer is provided with a first surface on which the device layer is positioned and a second surface opposite to the first surface;
A recess in the scribe line region, the recess extending from the second face toward the first face; and the material toughness of the buffer layer is greater than that of the wafer.
11. The semiconductor structure of claim 10, wherein the material of the buffer layer comprises an epoxy.
12. The semiconductor structure of claim 10, wherein the scribe line region comprises an auxiliary region, the device layer within the auxiliary region comprising one or both of a test structure and an alignment mark; the groove is located in the substrate of the auxiliary area.
13. The semiconductor structure of claim 12, wherein the scribe line region further comprises a protection region, the protection region being located between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
14. The semiconductor structure of claim 13, wherein the scribe line region further comprises a blocking region, the blocking region being located between the auxiliary region and the protection region; the device layer within the blocking region includes a blocking wall structure.
15. The semiconductor structure of claim 10, wherein a width of the recess ranges from 50 μιη to 70 μιη; the depth of the grooves ranges from 600 μm to 730 μm.
16. A method of forming a chip, comprising:
Providing a semiconductor structure, the semiconductor structure comprising:
The wafer comprises a substrate, a device layer positioned on the substrate, a plurality of chip areas and scribing channel areas between adjacent chip areas, wherein the wafer is provided with a first surface on which the device layer is positioned and a second surface opposite to the first surface;
A recess in the scribe line region, the recess extending from the second face toward the first face; the material toughness of the buffer layer is greater than that of the wafer;
and cutting the scribing channel region from the first surface to separate the chip regions from each other so as to form a plurality of chips.
17. The method of forming a chip of claim 16, wherein the scribe line region includes an auxiliary region, the device layer within the auxiliary region including one or both of a test structure and an alignment mark; the groove is located in the substrate of the auxiliary area.
18. The method of forming a chip of claim 17, wherein the scribe line region further comprises a protection region between the auxiliary region and the chip region; the device layer within the guard region includes a guard ring structure.
19. The method of forming a chip of claim 18, wherein the scribe line region further comprises a blocking region between the auxiliary region and the protective region; the device layer within the blocking region includes a blocking wall structure.
20. The method of forming a chip as claimed in claim 16, wherein the width of the recess ranges from 50 μm to 70 μm; the depth of the grooves ranges from 600 μm to 730 μm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211646006.7A CN118231222A (en) | 2022-12-20 | 2022-12-20 | Semiconductor structure, forming method thereof and forming method of chip |
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| CN202211646006.7A CN118231222A (en) | 2022-12-20 | 2022-12-20 | Semiconductor structure, forming method thereof and forming method of chip |
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