CN118213270A - Planarization method of patterned semiconductor substrate - Google Patents
Planarization method of patterned semiconductor substrate Download PDFInfo
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- CN118213270A CN118213270A CN202211626287.XA CN202211626287A CN118213270A CN 118213270 A CN118213270 A CN 118213270A CN 202211626287 A CN202211626287 A CN 202211626287A CN 118213270 A CN118213270 A CN 118213270A
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- liner layer
- semiconductor substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000005498 polishing Methods 0.000 claims abstract description 32
- 239000000126 substance Substances 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 230000005693 optoelectronics Effects 0.000 abstract description 4
- 230000026676 system process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 128
- 230000007547 defect Effects 0.000 description 7
- 238000007517 polishing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000000945 filler Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a planarization method of a patterned semiconductor substrate, which comprises the following steps: 1) Forming a sacrificial liner layer over a substrate; 2) Etching a pattern groove in a substrate and depositing an insulating layer; 3) Depositing a polishing pad layer on the insulating layer; 4) Forming an etching barrier layer on the pattern groove, and etching to remove part of the thickness of the second insulating part; 5) A first chemical mechanical polishing step of polishing the pad layer such that a removal rate of the first insulating portion is smaller than a removal rate of the second insulating portion, a top surface of the second insulating portion being higher than a top surface of the sacrificial pad layer; 6) And performing chemical mechanical polishing for the second time, wherein the removal rate of the second insulating part is larger than that of the sacrificial liner layer, so that the top surface of the second insulating part is flush with the top surface of the substrate when the sacrificial liner layer is removed. The invention realizes a process method for flattening ultra-deep and large patterns, can be used for a micro-electromechanical system process and a silicon-based optoelectronic device process, and can effectively improve the window of the subsequent process and the device performance.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a planarization method of an ultra-deep and large-pattern semiconductor substrate.
Background
The wafer planarization process generally used for silicon-based optoelectronic devices is generally ultra-deep and ultra-large, and presents a significant challenge to the planarization process as compared to the line width of tens of nanometers for IC devices. For example, in a Chemical Mechanical Polishing (CMP) process, the control of defects such as dishing on ultra-large linewidth grooves is a challenge.
For example, during the chemical mechanical polishing process, the filler in the groove, the silicon material on the surface of the silicon wafer and on both sides of the groove are easily removed excessively, so that dishing occurs in the filler in the groove, and as such, the surface defects of the silicon wafer are easily generated due to the excessive removal of the silicon material on both sides of the groove on the surface of the silicon wafer.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for planarizing a patterned semiconductor substrate, which is used for solving the problems of the prior art that the patterned semiconductor is easy to generate a pattern recess during planarization.
To achieve the above and other related objects, the present invention provides a planarization method of a patterned semiconductor substrate, the planarization method comprising: 1) Providing a substrate comprising opposite first and second sides, forming a sacrificial liner layer on the first side of the substrate; 2) Etching a pattern groove in the substrate, and depositing an insulating layer on the sacrificial liner layer and in the pattern groove to fill the pattern groove, wherein the top surface of the first insulating part at the pattern groove is lower than the top surface of the second insulating part on the sacrificial liner layer; 3) Depositing a polishing pad layer on the insulating layer; 4) Forming an etching barrier layer on the first insulating part and part of the second insulating part on two sides of the first insulating part above the pattern groove, and etching to remove part of the thickness of the grinding liner layer and the second insulating part outside the etching barrier layer; 5) Performing a first chemical mechanical polishing to remove the second insulating portion on the sacrificial liner layer, wherein a top surface of the first insulating portion is higher than a top surface of the sacrificial liner layer when the second insulating portion on the sacrificial liner layer is completely removed based on the polishing liner layer such that a removal rate of the first insulating portion is smaller than a removal rate of the second insulating portion; 6) And performing a second chemical mechanical polishing to remove part of the thicknesses of the sacrificial liner layer and the first insulating portion, wherein the removal rate of the first insulating portion is greater than the removal rate of the sacrificial liner layer so that the top surface of the first insulating portion is flush with the top surface of the substrate when the sacrificial liner layer is removed.
Optionally, step 3) further comprises the step of: and depositing a stress layer on the second surface of the substrate, wherein the stress layer is used for applying stress opposite to the insulating layer to the substrate so as to reduce the warpage of the substrate.
Optionally, the material of the stress layer is the same as that of the insulating layer, and the deposition process of the stress layer is the same as that of the insulating layer.
Optionally, the insulating layer includes a silicon dioxide layer formed by a high density plasma chemical vapor deposition process.
Optionally, the sacrificial liner layer comprises a silicon dioxide layer formed by a plasma enhanced chemical vapor deposition process.
Optionally, the abrasive liner layer comprises a silicon nitride layer formed by a chemical vapor deposition process.
Optionally, after the step 4) etching to remove the part of the thickness of the abrasive liner layer and the second insulating portion outside the etching barrier layer, the remaining thickness of the second insulating portion outside the etching barrier layer is 20% -50% of the deposited thickness of the second insulating portion.
Optionally, the total area of the graphic grooves accounts for 3% -10% of the total area of the substrate.
Optionally, the depth of the patterned recess is greater than 2.5 microns and the thickness of the deposited insulating layer on the sacrificial liner layer and in the patterned recess is greater than 3 microns.
Alternatively, the cross-sectional shape of the groove includes one of a rectangle and an inverted trapezoid.
As described above, the planarization method of the patterned semiconductor substrate of the present invention has the following advantageous effects:
The invention covers the substrate with the sacrifice liner layer, and the sacrifice liner layer is used as a protective layer of the substrate and a depletion ratio layer of the insulating layer of the second chemical mechanical polishing, so that the substrate and the insulating layer in the pattern groove can be protected from defects such as dent and the like in the second chemical mechanical polishing, and the top surface of the insulating layer in the pattern groove is flush with the surface of the substrate.
The invention deposits the grinding liner layer on the insulating layer in the pattern groove as a depletion ratio protection layer in the first chemical mechanical grinding, thereby reducing the removal ratio of the insulating layer in the pattern groove in the first chemical mechanical grinding, and ensuring that the insulating layer in the pattern groove has enough residual thickness.
The stress layer is deposited on the back of the substrate at the same time, so that the warpage of the wafer is reduced, and the thickness photoetching-etching process and the flatness of the twice chemical mechanical polishing are greatly improved.
The invention realizes a process method for flattening ultra-deep and large patterns, can be used for a micro-electromechanical system process and a silicon-based optoelectronic device process, and can effectively improve the window of the subsequent process and the device performance.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the application.
Fig. 1 to 10 are schematic structural views showing steps of a method for planarizing a patterned semiconductor substrate according to an embodiment of the present invention.
Description of element reference numerals
101. Substrate and method for manufacturing the same
102. Sacrificial liner layer
103. Graphic groove
104. Insulating layer
1041. First insulating part
1042. Second insulating part
105. Abrasive backing layer
106. Stress layer
107. Etching barrier layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 10, the present embodiment provides a planarization method of a patterned semiconductor substrate, the planarization method including the steps of:
As shown in fig. 1-2, step 1) is first performed to provide a substrate 101, where the substrate 101 includes a first surface and a second surface opposite to each other, and a sacrificial liner layer 102 is formed on the first surface of the substrate 101.
In some embodiments, the substrate 101 may be, for example, a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V compound substrate, or other desired species of substrate.
In some embodiments, the surface of the substrate 101 may be further formed with a structure such as an epitaxial layer, a dielectric layer, and the like.
In some embodiments, the substrate 101 may also be provided with a certain ion doping concentration, such as forming an N-type conductivity or a P-type conductivity, etc.
In some embodiments, the sacrificial liner layer 102 may be a silicon dioxide layer formed by a plasma enhanced chemical vapor deposition process. The thickness of the sacrificial spacer layer 102 may be set according to practical needs, for example, may be set between 100 nm and 10 μm.
In some embodiments, the total area of the patterned recesses 103 may be 3% to 10% of the total area of the substrate 101, for example. In one embodiment, the total area of the patterned recesses 103 is 4.5% of the total area of the substrate 101. For example, the width of the pattern groove 103 may be 1 to 100 micrometers.
In some embodiments, the depth of the pattern groove 103 is greater than 2.5 microns, for example, the depth of the pattern groove 103 may be 3 microns.
As shown in fig. 3 to 4, step 2) is then performed by etching a pattern groove 103 in the substrate 101, and depositing an insulating layer 104 on the sacrificial liner layer 102 and in the pattern groove 103 to fill the pattern groove 103, the top surface of the first insulating portion 1041 at the pattern groove 103 being lower than the top surface of the second insulating portion 1042 on the sacrificial liner layer 102.
In one embodiment, a photolithography process and a dry etching process (such as a reactive ion etching process RIE, an inductively coupled plasma etching process ICP, etc.) may be used to etch the pattern groove 103 in the substrate 101, where the cross-sectional shape of the pattern groove 103 may be one of a rectangle and an inverted trapezoid, and of course, the shape of the pattern groove 103 may also be set according to actual requirements, for example, may be a regular trapezoid, etc., or the corners of the pattern groove 103 may be rounded corners, etc.
In one embodiment, the insulating layer 104 comprises a silicon dioxide layer formed by a high density plasma chemical vapor deposition process. The silicon dioxide layer formed by the plasma enhanced chemical vapor deposition process is used as the sacrificial liner layer 102, and has a certain removal rate selection ratio with the silicon dioxide layer formed by the high-density plasma chemical vapor deposition process as the insulating layer 104 during chemical mechanical polishing, so that the substrate 101 and the insulating layer 104 in the pattern groove 103 can be protected from defects such as dishing during the second chemical mechanical polishing, and the top surface of the insulating layer 104 in the pattern groove 103 is flush with the surface of the substrate 101.
In one embodiment, the thickness of the insulating layer 104 deposited on the sacrificial liner layer 102 and in the patterned recess 103 is greater than 3 microns, for example, the thickness of the insulating layer 104 may be 4 microns.
As shown in fig. 5, step 3) is then performed to deposit a polishing pad layer 105 on the insulating layer 104.
In one embodiment, the abrasive liner layer 105 comprises a silicon nitride layer formed by a chemical vapor deposition process. The silicon nitride layer and the insulating layer 104 have a certain removal rate selection ratio in the chemical mechanical polishing process, so as to reduce the removal ratio of the insulating layer 104 in the pattern groove 103 in the subsequent first chemical mechanical polishing process, so that the insulating layer 104 in the pattern groove 103 has a sufficient residual thickness.
In one embodiment, as shown in fig. 6, step 3) further includes the steps of: a stress layer 106 is deposited on the second surface of the substrate 101, where the stress layer 106 is used to apply a stress opposite to the insulating layer 104 to the substrate 101, so as to reduce the warpage of the substrate 101. In a specific example, the material of the stress layer 106 is the same as the material of the insulating layer 104, and the deposition process of the stress layer 106 is the same as the deposition process of the insulating layer 104. The stress layer 106 is deposited on the back of the substrate 101 at the same time, so as to reduce the warpage of the wafer and greatly improve the flatness of the thickness photoetching-etching process and the subsequent two times of chemical mechanical polishing.
As shown in fig. 7 to 8, step 4) is performed, and an etching stop layer 107 is formed on the first insulating portion 1041 and a portion of the second insulating portion 1042 on both sides thereof above the pattern groove 103, and etching is performed to remove a portion of the thickness of the polishing pad layer 105 and the second insulating portion 1042 except for the etching stop layer 107.
For example, the width of the second insulating portion 1042 covered by the etching barrier layer 107 may be between one tenth and one fifth of the width of the pattern groove 103, so that a portion of the second insulating portion 1042 on both sides of the first insulating portion 1041 remains after etching, and thus, both sides of the first insulating portion 1041 on the pattern groove 103 are not easy to be recessed during the subsequent chemical mechanical polishing process.
In one embodiment, after etching to remove the part of the thickness of the polishing pad layer 105 and the second insulating portion 1042 outside the etching stopper layer 107, the remaining thickness of the second insulating portion 1042 outside the etching stopper layer 107 is 20% -50% of the deposited thickness of the second insulating portion 1042. For example, in one specific example, the remaining thickness of the second insulating portion 1042 other than the etching stopper layer 107 may be 30% of the deposited thickness of the second insulating portion 1042.
As shown in fig. 9, step 5) is performed after that, a first cmp is performed to remove the second insulating portion 1042 on the sacrificial pad layer 102, and the top surface of the first insulating portion 1041 is higher than the top surface of the sacrificial pad layer 102 when the removal rate of the first insulating portion 1041 is smaller than the removal rate of the second insulating portion 1042 based on the polished pad layer 105, so that the second insulating portion 1042 on the sacrificial pad layer 102 is completely removed.
In this embodiment, the polishing pad layer 105 may make the removal rate of the first insulating portion 1041 smaller than the removal rate of the second insulating portion 1042, so that when the second insulating portion 1042 on the sacrificial pad layer 102 is removed completely, the top surface of the first insulating portion 1041 is higher than the top surface of the sacrificial pad layer 102, and the sacrificial pad layer 102 may protect the surface of the substrate 101 and the side surface of the first insulating portion 1041, reduce the side erosion of the first insulating portion 1041, and may serve as a stop layer for the first chemical mechanical polishing.
As shown in fig. 10, finally, step 6) is performed, and a second cmp is performed to remove a portion of the thickness of the sacrificial liner layer 102 and the first insulating portion 1041, where the removal rate of the first insulating portion 1041 is greater than the removal rate of the sacrificial liner layer 102, so that the top surface of the first insulating portion 1041 is flush with the top surface of the substrate 101 when the sacrificial liner layer 102 is removed. The invention covers the substrate 101 with the sacrifice liner layer 102, and is used as a protective layer of the substrate 101 and a depletion ratio layer of the insulating layer 104 of the second chemical mechanical polishing, so that the insulating layer 104 in the substrate 101 and the pattern groove 103 can be protected from defects such as dent and the like in the second chemical mechanical polishing, and the top surface of the insulating layer 104 in the pattern groove 103 is flush with the surface of the substrate 101.
As described above, the planarization method of the patterned semiconductor substrate of the present invention has the following advantageous effects:
The invention covers the sacrificial liner layer 102 on the substrate, and is used as a protective layer of the substrate and a depletion ratio layer of the insulating layer 104 of the second chemical mechanical polishing, so that the substrate and the insulating layer 104 in the pattern groove 103 can be protected from defects such as dent and the like in the second chemical mechanical polishing, and the top surface of the insulating layer 104 in the pattern groove 103 is flush with the surface of the substrate.
The invention deposits the polishing pad layer 105 on the insulating layer 104 in the pattern groove 103 as a depletion ratio protection layer in the first chemical mechanical polishing, thereby reducing the removal ratio of the insulating layer 104 in the pattern groove 103 in the first chemical mechanical polishing, so that the insulating layer 104 in the pattern groove 103 has enough residual thickness.
The invention deposits the stress layer 106 on the back of the substrate at the same time, in order to reduce the warpage of the wafer, in order to greatly improve the thickness photoetching-etching process and the evenness of twice chemical mechanical polishing.
The invention realizes a process method for flattening ultra-deep and large patterns, can be used for a micro-electromechanical system process and a silicon-based optoelectronic device process, and can effectively improve the window of the subsequent process and the device performance.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of planarizing a patterned semiconductor substrate, the method comprising:
1) Providing a substrate comprising opposite first and second sides, forming a sacrificial liner layer on the first side of the substrate;
2) Etching a pattern groove in the substrate, and depositing an insulating layer on the sacrificial liner layer and in the pattern groove to fill the pattern groove, wherein the top surface of a first insulating part at the pattern groove is lower than the top surface of a second insulating part on the sacrificial liner layer;
3) Depositing a polishing pad layer on the insulating layer;
4) Forming an etching barrier layer on the first insulating part above the pattern groove and part of the second insulating part on two sides of the first insulating part, and etching to remove part of the thickness of the second insulating part except the etching barrier layer;
5) Performing a first chemical mechanical polishing to remove the second insulating portion on the sacrificial liner layer, wherein a top surface of the first insulating portion is higher than a top surface of the sacrificial liner layer when the second insulating portion on the sacrificial liner layer is completely removed based on the polishing liner layer such that a removal rate of the first insulating portion is smaller than a removal rate of the second insulating portion;
6) And performing a second chemical mechanical polishing to remove part of the thicknesses of the sacrificial liner layer and the first insulating portion, wherein the removal rate of the first insulating portion is greater than the removal rate of the sacrificial liner layer so that the top surface of the first insulating portion is flush with the top surface of the substrate when the sacrificial liner layer is removed.
2. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the step 3) further comprises the steps of: and depositing a stress layer on the second surface of the substrate, wherein the stress layer is used for applying stress opposite to the insulating layer to the substrate so as to reduce the warpage of the substrate.
3. The planarization method of a patterned semiconductor substrate as recited in claim 2, wherein: the material of the stress layer is the same as that of the insulating layer, and the deposition process of the stress layer is the same as that of the insulating layer.
4. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the insulating layer includes a silicon dioxide layer formed by a high density plasma chemical vapor deposition process.
5. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the sacrificial liner layer includes a silicon dioxide layer formed by a plasma enhanced chemical vapor deposition process.
6. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the abrasive liner layer includes a silicon nitride layer formed by a chemical vapor deposition process.
7. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: and 4) etching to remove part of the thickness of the grinding liner layer and the second insulating part outside the etching barrier layer, wherein the residual thickness of the second insulating part outside the etching barrier layer is 20-50% of the deposited thickness of the second insulating part.
8. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the total area of the pattern grooves accounts for 3% -10% of the total area of the substrate.
9. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the depth of the patterned recess is greater than 2.5 microns and the thickness of the deposited insulating layer on the sacrificial liner layer and in the patterned recess is greater than 3 microns.
10. The planarization method of a patterned semiconductor substrate as recited in claim 1, wherein: the cross-sectional shape of the groove includes one of a rectangle and an inverted trapezoid.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211626287.XA CN118213270A (en) | 2022-12-16 | 2022-12-16 | Planarization method of patterned semiconductor substrate |
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| CN202211626287.XA CN118213270A (en) | 2022-12-16 | 2022-12-16 | Planarization method of patterned semiconductor substrate |
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