CN103928325B - Super-junction device edge epi flattening method - Google Patents
Super-junction device edge epi flattening method Download PDFInfo
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- CN103928325B CN103928325B CN201310009217.4A CN201310009217A CN103928325B CN 103928325 B CN103928325 B CN 103928325B CN 201310009217 A CN201310009217 A CN 201310009217A CN 103928325 B CN103928325 B CN 103928325B
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Abstract
The invention discloses a kind of super-junction device edge epi flattening method; after the complete epitaxial layer of super-junction device trench fill; before grinding; first fill layer oxide film; then use cmp that surface grinding is extremely smooth; re-use wet etching and return the thickness that oxide-film at quarter needs to barrier layer; re-use cmp to be ground surface epitaxial layer offset to planarization; make can effectively remove the extension residual offset that wafer perimeter safeguard measure is formed in this way, make epitaxial layer grind and will not produce epitaxial layer residual because of periphery offset.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of super-junction device edge epi planarization side
Method.
Background technology
In semiconductor technology now, deep groove structure application is relatively broad.As grasped to completely cut off difference as isolation structure
Make the electronic device of voltage, and be applied to super-junction structures semiconductor devices is put down by exhausting the electric charge of state as P-N junction
Weighing apparatus reaches high-breakdown-voltage performance etc..For etching in super junction MOSFET manufacture process and the method filling deep trench,
It is one layer of lightly doped n type epitaxial layer (monocrystalline silicon) of growth on heavily doped N-type silicon substrate, then carve on this epitaxial layer
Erosion deep trench, then again use p-type this deep trench of monocrystalline silicon selective filling, finally with cmp (CMP:
Chemical Mechanical Polishing) technique carries out surface planarisation.Now this deep groove structure is as p-type
Semiconductor column, the both sides of this deep groove structure, as n-type semiconductor post, have i.e. obtained horizontal p-type and N-type have replaced row
The p-type of row and n-type semiconductor post.N-type silicon is filled out in p-type silicon exchange, i.e. substrate or extension and groove by the method
The conduction type of the monocrystalline silicon filling exchanges, and its effect is constant.
In said method, owing to wafer (silicon chip) implements the processing procedure of periphery protection, after selective filling deep trench completes,
I.e. before cmp, wafer perimeter can have higher surface offset (step height) pattern, and about 0.8
Microns, causes in process of lapping, and the extension of peripheral part can not be mechanically and be ground to, and causes wafer perimeter
95 millimeters of outer extension residuals that can produce, as shown in Figures 1 and 2.In Fig. 1,1 is silicon substrate, and 2 and 4 is oxide structure
The barrier layer becoming, 3 barrier layers constituting for nitride, 5 for filling the selective epitaxial layer of groove, and 6 is epitaxial layer residual.
In follow-up processing procedure, these residues can peel off, and affects the yield of product.
Content of the invention
The technical problem to be solved is to provide a kind of super-junction device edge epi flattening method, outside improvement
The grinding effect prolonging.
For solving the problems referred to above, a kind of super-junction device edge epi flattening method of the present invention, comprise to walk as follows
Rapid:
1st step, deposits layer oxide film, one layer of nitride film and second layer oxide-film as barrier layer at silicon chip surface；
2nd step, utilizes photoresist lithographic definition to go out extension trench area；
3rd step, trench area barrier layer performs etching, and removes trench area barrier layer；
4th step, with the further etching groove of dry method, crystal edge protection ring protection silicon chip edge is not etched；
5th step, removes second layer oxide-film and nitride film barrier layer；
6th step, to carrying out monocrystalline silicon or polysilicon epitaxial filling in extension groove, extension fills full groove；
7th step, at silicon chip surface deposition oxidation film；
8th step, carries out cmp to the oxide-film of silicon chip surface deposit；
9th step, oxide-film is carried out back carving by wet etching；
10th step, carries out cmp to silicon chip surface, makes groove epitaxial surface planarize.
Further, in described 1st step, the thickness of two-layer oxide layer and one layer of nitration case isInstitute
It is LPCVD technique by technique, or pecvd process.
Further, in described 4th step, the degree of depth of etching groove is 10～100 μm, and width is 1～10 μm.
Further, in described 6th step, the filling of deep trench uses selective monocrystalline silicon epitaxial growth technology.
Further, in described 7th step, the thickness of the oxide-film of deposit exceeds ground floor oxygen more than epitaxial diposition in groove
Change the height of film, preferably more than the 50% of described height.
Further, in described 8th step, use silica cmp, be ground to oxidation film layer surface
Higher than groove upper epitaxial layer
Further, in described 9th step, using wet etching, the oxide-film on surface returns quarter to barrier layer thickness is
A kind of super-junction device edge epi flattening method of the present invention, after having filled epitaxial layer, grinds it
Before, first fill layer oxide film, then use cmp surface grinding to smooth, re-use wet etching and return
Carve the thickness that needs to barrier layer of oxide-film, re-use cmp and surface epitaxial layer offset is ground to smooth
Changing, effectively eliminating the extension offset that wafer perimeter safeguard measure is formed, making epitaxial layer grind will not be because of periphery offset
High and produce epitaxial layer residual.
Brief description
Fig. 1 is tradition CMP post-job trench profile schematic diagram；
Fig. 2 is tradition CMP operation rear surface extension particle residue schematic diagram；
Fig. 3～12 are each step process schematic diagrames of the present invention；
Figure 13 is the silicon chip surface residual schematic diagram after using the present invention to process；
Figure 14 is present invention process schematic flow sheet.
Description of reference numerals
1 is silicon substrate, and the 2nd, 4 is barrier oxide layers, and 3 is nitride-barrier, and 5 is extension, and 6 is extension residual,
7 is crystal edge protection ring, and 8 is photoresist.
Detailed description of the invention
A kind of super-junction device edge epi flattening method of the present invention, now enumerates an embodiment accompanying drawings
As follows:
Described process comprises the steps of:
1st step, as it is shown on figure 3, at silicon chip 1 surface deposition layer oxide film the 2nd, one layer of nitride film 3 and the second layer
Oxide-film 4 is as barrier layer；Ground floor oxide-film 2 thickness isUse pecvd process deposit, nitrogen
The thickness changing film 3 isUsing LPCVD technique, third layer is oxide layer 4, and thickness is Use pecvd process deposit.
2nd step, as shown in Figure 4, utilizes photoresist 8 lithographic definition to go out extension trench area.
3rd step, as it is shown in figure 5, trench area barrier layer performs etching, removes trench area barrier layer oxide-film and the 2nd, nitrogenizes
Film 3 and oxide layer 4.
4th step, as shown in Figure 6, utilizes crystal edge protection ring 7 to protect silicon chip edge, etches shape by dry method further downward
Becoming groove, the oxide-film 4 under crystal edge protection ring 7 is not etched, and the oxide-film 4 in other regions is etched away a part；
Form gash depth 10～100 μm, width 1～10 μm in silicon substrate 1.
5th step, as it is shown in fig. 7, remove second layer oxide-film 4 and nitride film barrier layer 3, due to crystal edge protection ring 7
Protection, oxide-film 4 and nitride film barrier layer 3 below retain.
6th step, as shown in Figure 8, to carrying out monocrystalline silicon in extension groove or polysilicon epitaxial 6 is filled, extension 6 is filled
Full groove；And epitaxial layer 6 exceeds 2 about 2～5 μm of ground floor oxide-film barrier layer.
7th step, as it is shown in figure 9, in silicon chip surface deposition oxidation film 4 again, the thickness of oxide-film 4 is 3～10 μm,
Require that the cladding thickness above selective epitaxial is 0.5～3 μm.
8th step, as shown in Figure 10, carries out cmp to the oxide-film 4 of silicon chip surface deposit, is ground to oxygen
The thickness that change film 4 exceeds epitaxial layer 6 is
9th step, as shown in figure 11, oxide-film 4 is carried out back carving by wet etching, returns and carves to oxide-film barrier layer 4
Thickness is
10th step, as shown in figure 12, carries out cmp to silicon chip surface, makes groove extension 6 surface planarisation,
Grinding rests on oxide-film barrier layer 2.Extension grinding technics terminates.
Through the silicon chip that Ginding process of the present invention grinds, effectively eliminate the offset that wafer perimeter safeguard measure is formed, do not produce
Raw extension residual, as shown in figure 13, is the silicon chip using after Conventional milling methods and Ginding process operation of the present invention
Displaing micro picture, wherein right figure is improvement figure of the present invention, and compared with left figure conventional method, in figure, number of defects significantly reduces, silicon
Piece surface is clean, and graph outline is clear, it is shown that extension is ground and preferably improved effect by the present invention.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art,
The present invention can have various modifications and variations.All within the spirit and principles in the present invention, any modification of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (7)
1. a super-junction device edge epi flattening method, it is characterised in that: comprise following processing step:
1st step, deposits layer oxide film, one layer of nitride film and second layer oxide-film as barrier layer at silicon chip surface；
2nd step, utilizes photoresist lithographic definition to go out extension trench area；
3rd step, trench area barrier layer performs etching, and removes trench area barrier layer, removes photoresist afterwards；
4th step, utilizes barrier layer to do hard mask, etches silicon substrate by dry method further downward and forms groove, and crystal edge is protected
Ring protection silicon chip edge is not etched；
5th step, removes second layer oxide-film and nitride film barrier layer, due to the protection of crystal edge protection ring, resistance below
Barrier is retained；
6th step, to carrying out monocrystalline silicon or polysilicon epitaxial filling in extension groove, extension fills full groove；
7th step, at silicon chip surface deposition oxidation film；
8th step, carries out cmp to the oxide-film of silicon chip surface deposit；
9th step, oxide-film is carried out back carving by wet etching；
10th step, carries out cmp to silicon chip surface, makes groove epitaxial surface planarize.
2. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 1st step
In, two-layer oxide layer and one layer of nitration case, the thickness of each layer isDeposited oxide layer or nitration case institute
It is LPCVD technique by technique, or pecvd process.
3. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 4th step
In, the degree of depth of etching groove is 10～100 μm, and width is 1～10 μm.
4. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 6th step
In, the filling of deep trench uses selective monocrystalline silicon or selective polysilicon epitaxial growth technique.
5. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 7th step
In, the thickness of the oxide-film of deposit is more than the height beyond ground floor oxide-film after epitaxial diposition in groove.
6. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 8th step
In, using silica cmp, the oxide thickness being ground on groove epitaxial layer is
7. super-junction device edge epi flattening method as claimed in claim 1, it is characterised in that: described 9th step
In, using wet etching, the oxide-film barrier layer of silicon face is returned quarter to thickness is
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315093A (en) * | 2010-07-08 | 2012-01-11 | 上海华虹Nec电子有限公司 | Process method for flattening filled trench |
| CN102446704A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
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| US6250994B1 (en) * | 1998-10-01 | 2001-06-26 | Micron Technology, Inc. | Methods and apparatuses for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies on planarizing pads |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315093A (en) * | 2010-07-08 | 2012-01-11 | 上海华虹Nec电子有限公司 | Process method for flattening filled trench |
| CN102446704A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
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