CN118156155A

CN118156155A - Three-dimensional packaging structure and forming method thereof

Info

Publication number: CN118156155A
Application number: CN202410233660.8A
Authority: CN
Inventors: 杨程
Original assignee: Changdian Technology Management Co ltd
Current assignee: Changdian Technology Management Co ltd
Priority date: 2024-03-01
Filing date: 2024-03-01
Publication date: 2024-06-07

Abstract

The invention relates to a three-dimensional packaging structure and a forming method thereof. The method for forming the three-dimensional packaging structure comprises the following steps: forming a first rewiring layer comprising a first surface and a second surface; attaching a functional chip to the first surface of the first rewiring layer, wherein the functional chip is electrically connected with the first rewiring layer; attaching an active chip to the second surface of the first rewiring layer, wherein the active chip is electrically connected with the first rewiring layer, the active chip comprises a third surface and a fourth surface, the third surface faces the second surface, and a conductive connection structure is at least positioned in the active chip; forming at least a first plastic sealing layer for plastic sealing the active chip; and removing part of the first plastic sealing layer to expose the conductive connection structure. The invention simplifies the manufacturing process of the three-dimensional packaging structure, reduces the manufacturing difficulty of the three-dimensional packaging structure and improves the performance of the three-dimensional packaging structure.

Description

Three-dimensional packaging structure and forming method thereof

Technical Field

The present disclosure relates to integrated circuits, and particularly to a three-dimensional package structure and a method for forming the same.

Background

Currently, the semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, where each generation of IC has smaller and more complex circuitry than the previous generation of ICs. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased and the geometry (i.e., the smallest component that can be created using a manufacturing process) has decreased.

In the package structure, in order to ensure stable electrical connection between the functional chip and the package substrate, a bridge chip is generally disposed between the functional chip and the package substrate, so as to form a 2.5D package structure. The bridge chip is typically bonded to the functional chip, but the technology of bonding between large-scale chips is still not mature. In addition, in the process of manufacturing the three-dimensional packaging structure, the bridge chip is connected to the carrier provided with the re-wiring layer, and after the bridge chip is molded, the functional chip is connected to the surface of the bridge chip, which is away from the re-wiring layer, through the copper column bonding. However, due to the difference of thermal expansion coefficients between the plastic packaging material of the plastic packaging bridging chip and the carrier, deformation such as warping and the like can occur to the plastic packaging body, so that the stability and reliability of connection between the subsequent active chip and the functional chip are affected, and the overall performance and manufacturing yield of the packaging structure are finally affected. In addition, the bridge chip is a passive chip, and the formed packaging structure is only a 2.5D packaging structure, so that the further improvement of the performance of the packaging structure is limited.

Therefore, how to improve the performance of the package structure, simplify the manufacturing process of the package structure, and increase the manufacturing yield of the package structure is a technical problem to be solved currently.

Disclosure of Invention

The invention provides a three-dimensional packaging structure and a forming method thereof, which are used for improving the performance of the packaging structure, simplifying the manufacturing process of the packaging structure and improving the manufacturing yield of the packaging structure.

According to some embodiments, the present invention provides a method for forming a three-dimensional package structure, including the following steps:

Forming a first rewiring layer comprising a first surface and a second surface opposite the first surface;

attaching a functional chip to the first surface of the first rewiring layer, the functional chip being electrically connected with the first rewiring layer;

Attaching an active chip to the second surface of the first rewiring layer, wherein the active chip is electrically connected with the first rewiring layer, the active chip comprises a third surface and a fourth surface opposite to the third surface, the third surface faces the second surface, and a conductive connection structure is at least positioned in the active chip;

forming at least a first plastic layer for plastic packaging the active chip;

and removing part of the first plastic sealing layer to expose the conductive connection structure.

In some embodiments, before attaching the active chip to the second surface of the first redistribution layer, the method further comprises the steps of:

And forming a second plastic sealing layer which coats the functional chip on the first surface of the first rewiring layer.

In some embodiments, the functional chip includes a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer; before attaching the active chip to the second surface of the first redistribution layer, the method further comprises the steps of:

removing part of the second plastic sealing layer to expose the back surface of the functional chip;

And forming a heat dissipation layer covering the back surface of the functional chip.

forming a first conductive connection post on the second surface of the first rewiring layer, wherein the first conductive connection post is electrically connected with the first rewiring layer.

In some embodiments, the specific step of attaching an active chip onto the second surface of the first redistribution layer comprises:

providing an active chip comprising a third surface and a fourth surface opposite the third surface;

Forming a soldering layer on the third surface of the active chip;

and connecting the active chip to the second surface of the first rewiring layer in a direction in which the bonding layer faces the second surface, wherein the bonding layer is electrically connected with the first rewiring layer and the active chip.

In some embodiments, the conductive connection structure includes a first conductive bump on the fourth surface of the active chip, the first molding layer encasing the first conductive bump; the specific steps of exposing the conductive connection structure include:

and removing part of the first plastic sealing layer by adopting a grinding process to expose the first conductive bump.

In some embodiments, the conductive connection structure includes a second conductive bump located within the active chip; the specific steps of exposing the conductive connection structure include:

And removing part of the first plastic sealing layer and part of the active chip by adopting a grinding process, and exposing the second conductive bump.

In some embodiments, after exposing the conductive connection structure, the method further comprises the steps of:

providing a second redistribution layer;

electrically connecting the exposed conductive connection structure with the second redistribution layer, the active chip being located between the first and second redistribution layers;

And forming an extraction conductive bump on the surface of the second redistribution layer, which is away from the active chip, wherein the extraction conductive bump is electrically connected with the second redistribution layer.

According to other embodiments, the present invention further provides a three-dimensional package structure, including:

A first rewiring layer comprising a first surface and a second surface opposite the first surface;

a functional chip located on the first surface of the first rewiring layer, and electrically connected with the first rewiring layer;

the active chip comprises a third surface and a fourth surface opposite to the third surface, the active chip is attached to the second surface of the first rewiring layer, the third surface faces the second surface, and a conductive connection structure is at least located in the active chip;

and the first plastic layer is used for plastic packaging the active chip, and the conductive connecting structure is exposed on the surface of the first plastic layer, which faces away from the first rewiring layer.

In some embodiments, further comprising:

the second plastic layer is positioned on the first surface of the first rewiring layer and at least coats the functional chip.

In some embodiments, the functional chip includes a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer, the back side of the functional chip being exposed to a surface of the second molding layer; the three-dimensional package structure further includes:

And the heat dissipation layer is covered on the back surface of the functional chip.

In some embodiments, the active die has a solder layer on the third surface, the solder layer is soldered on the second surface of the first redistribution layer, and the solder layer electrically connects the first redistribution layer and the active die.

In some embodiments, the conductive connection structure includes a first conductive bump on the fourth surface of the active chip, a bottom surface of the first conductive bump being exposed to a surface of the first molding layer; the three-dimensional package structure further includes:

The second rewiring layer is positioned on one side, away from the first rewiring layer, of the active chip, and the first conductive bump is electrically connected with the second rewiring layer.

In some embodiments, the conductive connection structure includes a second conductive bump within the active chip, a bottom surface of the second conductive bump being exposed to the fourth surface of the active chip; the three-dimensional package structure further includes:

and the second rewiring layer is positioned on one side of the active chip, which is away from the first rewiring layer, and the second conductive bump is electrically connected with the second rewiring layer.

According to the three-dimensional packaging structure and the forming method thereof provided by the embodiments of the invention, the functional chip and the active chip are electrically connected by forming the first rewiring layer, and the functional chip and the active chip do not need to be directly bonded and connected, so that the manufacturing process of the packaging structure is simplified, and the manufacturing difficulty of the packaging structure is reduced. According to the invention, after the functional chip is attached to the first surface of the first rewiring layer, the active chip is attached to the second surface of the first rewiring layer, so that the influence of the process of attaching the active chip on the functional chip is avoided, the probability of deformation such as warpage in the package structure is reduced, and the performance of the package structure is improved. The invention adopts the process of bridging the chip to form the active chip, the active chip can be used as the bridging chip, a conductive connecting structure is at least positioned in the active chip, and the conductive connecting structure is exposed on the surface of a first plastic layer for plastic packaging the active chip, so that power signals and other electric signals (such as control electric signals) can be transmitted to the active chip through the conductive connecting structure, thereby forming a three-dimensional packaging structure, and realizing effective improvement of the performance of the packaging structure. According to other embodiments of the invention, the welding layer is arranged on the third surface of the active chip, and the active chip is connected to the second surface of the first rewiring layer through the welding layer, so that the problem of high bonding difficulty caused by direct bonding of the copper column on the active chip and the first rewiring layer is avoided, the manufacturing process of the packaging structure is further simplified, and the manufacturing difficulty of the packaging structure is reduced. Moreover, the solder layer can also act as a stress relief layer, relieving stress between the first redistribution layer and the active die, thereby further improving the performance of the package structure.

Drawings

FIG. 1 is a flow chart of a method for forming a three-dimensional package structure in accordance with an embodiment of the present invention;

Fig. 2-13 are schematic views of the main process structure of the embodiment of the present invention in the process of forming a three-dimensional package structure.

Detailed Description

The following describes in detail the three-dimensional package structure and the forming method thereof with reference to the accompanying drawings.

The embodiment provides a method for forming a three-dimensional package structure, fig. 1 is a flowchart of a method for forming a three-dimensional package structure in the embodiment of the invention, and fig. 2 to fig. 13 are schematic process structures of the embodiment of the invention in the process of forming the three-dimensional package structure. As shown in fig. 1 to 13, the method for forming the three-dimensional package structure includes the following steps:

Step S11, forming a first redistribution layer 21, where the first redistribution layer 21 includes a first surface 211 and a second surface 212 opposite to the first surface 211, as shown in fig. 2;

Step S12, mounting a functional chip 30 onto the first surface 211 of the first redistribution layer 21, wherein the functional chip 30 is electrically connected to the first redistribution layer 21, as shown in fig. 3;

step S13, attaching an active chip 80 onto the second surface 212 of the first redistribution layer 21, where the active chip 80 is electrically connected to the first redistribution layer 21, and the active chip 80 includes a third surface 801 and a fourth surface 802 opposite to the third surface 801, the third surface 801 faces the second surface 212, and a conductive connection structure is at least located in the active chip 80, as shown in fig. 8;

Step S14, forming at least a first plastic layer 90 for plastic packaging the active chip 80, as shown in fig. 9;

In step S15, a portion of the first molding layer 90 is removed, exposing the conductive connection structure, as shown in fig. 10 or fig. 13.

In some embodiments, the specific steps of mounting the functional chip 30 onto the first surface 211 of the first redistribution layer 21 include:

Providing a functional chip 30, the functional chip 30 comprising a front side 301 and a back side 302 opposite to the front side 301;

the functional chip 30 is bonded to the first surface 211 of the first redistribution layer 21, and the front surface of the functional chip 30 faces the first surface 211 of the first redistribution layer 21.

For example, the first re-wiring layer 21 may be formed on the carrier 20. In one example, the first re-wiring layer 21 includes a first layer of insulating material and a high density of first circuit traces 22 within the first layer of insulating material. The functional chip 30 may include not only active devices but also passive devices. The active device described in this embodiment mode refers to an electronic device that requires an external power source to operate normally. In one example, the front surface 301 of the functional chip 30 is provided with bonding bumps 31. The functional chip 30 is flip-chip mounted on the first surface 211 of the first redistribution layer 21, that is, the bonding bump 31 on the front surface 301 of the functional chip 30 is bonded and connected to the first surface 211 of the first redistribution layer 21, so that a wire bonding process is not required, and the manufacturing difficulty of the three-dimensional package structure is further reduced. When bonding the functional chip 30 to the first redistribution layer 21, due to the supporting effect of the carrier 20 on the first redistribution layer 21, deformation such as warpage of the first redistribution layer 21 during the process of attaching the functional chip 30 to the first redistribution layer 21 is avoided, thereby contributing to further improving the performance of the three-dimensional package structure. In an example, the number of the functional chips 30 is plural, and the plural functional chips 30 are arranged in a direction perpendicular to the first surface 211 or in a direction parallel to the first surface 211. The structures of the plurality of functional chips 30 may be the same or different, thereby further expanding the functions of the three-dimensional package structure.

In some embodiments, before attaching the active chip 80 to the second surface 212 of the first redistribution layer 21, the method further includes the steps of:

a second plastic layer 40 is formed on the first surface 211 of the first redistribution layer 21 to encapsulate the functional chip 30, as shown in fig. 4.

In some embodiments, the functional chip includes a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer; before attaching the active chip 80 to the second surface 212 of the first redistribution layer 21, the method further includes the steps of:

Removing a portion of the second molding layer 40, exposing the back surface 302 of the functional chip 30, as shown in fig. 5;

A heat dissipation layer 60 is formed overlying the back side 302 of the functional chip 30, as shown in fig. 6.

In an example, after the functional chip 30 is mounted on the first surface 211 of the first redistribution layer 21, a first adhesive (not shown in the drawing) may be filled between the front surface 301 of the functional chip 30 and the first surface 211 of the first redistribution layer 21 to enhance the connection strength between the functional chip 30 and the first redistribution layer 21. Thereafter, the carrier 20 is removed, and the functional chip 30 is encapsulated with an epoxy molding compound (Epoxy Molding Compound, EMC) to form the second molding layer 40 on the first surface 211 of the first redistribution layer 21, as shown in fig. 4. Thereafter, a grinding process is used to remove a portion of the second molding layer 40, exposing the back surface 302 of the functional chip 30. Next, a metal material is deposited on the surface of the second molding layer 40 facing away from the first redistribution layer 21, so as to form the heat dissipation layer 60, and the heat dissipation layer 60 covers at least the back surface 302 of the functional chip 30. By providing the heat dissipation layer 60 on the back surface 302 of the functional chip 30, the heat dissipation performance of the functional chip 30 is enhanced, and the heat transfer of the heat generated by the functional chip 30 to the first redistribution layer 21 is reduced, thereby enhancing the heat dissipation capability of the three-dimensional package structure as a whole. In an example, the heat dissipation layer 60 has a single-layer structure, so as to simplify the manufacturing process of the three-dimensional package structure. In another example, the heat dissipation layer 60 has a multi-layered structure to further enhance the heat dissipation performance of the heat dissipation layer 60.

In another example, instead of filling the first adhesive between the front surface 301 of the functional chip 30 and the first surface 211 of the first redistribution layer 21, the bonding bump 31 may be directly encapsulated with the second encapsulation layer 40, so as to further simplify the manufacturing process of the three-dimensional package structure.

First conductive connection pillars 70 are formed on the second surface 212 of the first redistribution layer 21, and the first conductive connection pillars 70 are electrically connected to the first redistribution layer 21, as shown in fig. 7.

In some embodiments, the specific steps of attaching the active chip 80 to the second surface 212 of the first redistribution layer 21 include:

providing an active chip 80, the active chip 80 comprising a third surface 801 and a fourth surface 802 opposite to the third surface 801;

Forming a bonding layer 82 on the third surface 801 of the active die 80;

the active chip 80 is connected to the second surface 212 of the first redistribution layer 21 in a direction in which the bonding layer 82 faces the second surface 212, and the bonding layer 82 electrically connects the first redistribution layer 21 and the active chip 80, as shown in fig. 8.

In some embodiments, the conductive connection structure includes a first conductive bump 81 located on the fourth surface 802 of the active chip 80, the first plastic layer 90 encasing the first conductive bump 81; the specific steps of exposing the conductive connection structure include:

A grinding process is used to remove a portion of the first molding layer 90, exposing the first conductive bump 81, as shown in fig. 9.

Providing a second redistribution layer 100;

electrically connecting the exposed conductive connection structure with the second re-wiring layer 100, the active chip 80 being located between the first re-wiring layer 21 and the second re-wiring layer 100;

An outgoing conductive bump 101 is formed on a surface of the second redistribution layer 100 facing away from the active chip 80, and the outgoing conductive bump 101 is electrically connected to the second redistribution layer 100, as shown in fig. 10.

The active chip 80 in this embodiment refers to a chip that requires external power to operate properly. The conductive connection structure in this embodiment is located at least in the active chip 80, which means that at least part of the conductive connection structure extends from the fourth surface of the active chip 80 to the inside of the active chip 80 in a direction perpendicular to the fourth surface 802 of the active chip 80. For example, a deposition process and a photolithography process may be used to form a plurality of the first conductive connection pillars 70 on the second surface 212 of the first redistribution layer 21, and the first conductive connection pillars 70 are electrically connected to the first redistribution layer 21, for extracting electrical signals in the first redistribution layer 21 or transmitting control signals to the first redistribution layer 21. When the thickness of the active chip 80 is thin, the conductive connection structure may include a third conductive bump on the third surface 801 of the active chip 80, the first conductive bump 81 on the fourth surface 802 of the active chip 80, and a second conductive connection post inside the active chip 80, the second conductive connection post being electrically connected to at least the first conductive bump 81. In one example, the second conductive connection pillars extend through the active die 80. Then, solder is applied to the third conductive bump to form the solder layer 82. Next, the solder layer 82 is soldered to the second surface 212 of the first redistribution layer 21. Because the active chip 80 is electrically connected to the second surface 212 of the first redistribution layer 21 through the solder layer 82, the problem of high bonding difficulty (such as high bonding alignment difficulty between the copper pillar and the first redistribution layer) caused by direct bonding between the copper pillar on the active chip and the first redistribution layer is avoided, thereby further simplifying the manufacturing process of the three-dimensional package structure and reducing the manufacturing difficulty of the three-dimensional package structure. Moreover, the bonding layer can also serve as a stress release layer to balance the stress generated in the bonding process of the active chip 80 and the first redistribution layer 21, so that the bonding stress is prevented from being gathered in the first redistribution layer 21 and the active chip 80, and the performance of the three-dimensional package structure is further improved. Next, a second adhesive (not shown in the drawing) is filled between the second surface 212 of the first re-wiring layer 21 and the third surface of the active chip 80 to enhance the connection strength between the active chip 80 and the first re-wiring layer 21, and the second adhesive can also help to relieve stress generated due to the mismatch of thermal expansion coefficients between the first re-wiring layer 21 and the active chip 80. In other embodiments, the second adhesive may not be provided. Then, the active chip 80 and the first conductive connection pillars 70 are encapsulated with an encapsulating material such as an epoxy molding compound, so as to form the first encapsulating layer 90 on the second surface 212 of the first redistribution layer 21. By forming the second plastic sealing layer 40 and the first plastic sealing layer 90 on opposite sides of the first redistribution layer 21, stress on opposite sides of the first redistribution layer 21 may be balanced, so that the probability of deformation of the first redistribution layer 21 is reduced, and thus the performance of the three-dimensional package structure is further improved. In addition, since the mounting and molding processes of the functional chip 30 are completed before the first molding layer 90 is formed, the influence of the process of forming the first molding layer 90 on the mounting of the functional chip 30 is avoided, thereby realizing further improvement of the performance of the three-dimensional package structure.

After forming the first molding layer 90, a portion of the first molding layer 90 may be removed by a grinding process, thereby exposing a bottom surface of the first conductive bump 81 (i.e., a surface of the first conductive bump 81 facing away from the first redistribution layer 21) and a bottom surface of the first conductive connection post 70 (i.e., a surface of the first conductive connection post 70 facing away from the first redistribution layer 21). After the first conductive bump 81 and the first conductive connection post 70 are exposed through the grinding process, the first conductive bump 81 and the second redistribution layer 100 and the first conductive connection post 70 and the second redistribution layer 100 are bonded. Since the first conductive bumps 81 and the first conductive connection pillars 70 have been exposed through the grinding process, it is possible to reduce the influence of the warpage of the first molding layer 90 on the electrical connection of the active chip 80 and the second redistribution layer 100, and further improvement of the performance of the three-dimensional package structure is achieved. Thereafter, an outgoing conductive bump 101 may be formed on a surface of the second redistribution layer 100 facing away from the active chip 80 using an electroplating process, the outgoing conductive bump 101 being electrically connected to the second redistribution layer 100, as shown in fig. 10.

In this embodiment, the active chip 80 is used to connect the second redistribution layer 100 and the first redistribution layer 21, that is, the active chip 80 is used as a bridge chip in a package structure, and the conductive connection structure exposed to the first plastic layer 90 is used to transmit a power signal and other control signals to the active chip 80. In an example, the active chip 80 may be SRAM (Static Random Access Memory ). In another example, the active chip 80 may include low power circuitry (e.g., input/output circuitry), a power switch integrated with a voltage regulator, and the like.

In other embodiments, the conductive connection structure includes a second conductive bump 110 located within the active die 80; the specific steps of exposing the conductive connection structure include:

portions of the first molding layer 90 and portions of the active die 80 are removed, exposing the second conductive bumps 110, as shown in fig. 12.

For example, when the thickness of the active chip 80 is thicker, the active chip 80 may include a chip body and a passivation layer covering the chip body. A second conductive bump 110 is disposed in the chip body of the active chip 80 (e.g., the second conductive bump 110 penetrates the chip body), and the passivation layer is located on a surface of the chip body facing away from the first redistribution layer 21. In an example, after the active chip 80 is attached to the second surface 212 (as shown in fig. 11) of the first redistribution layer 21, the active chip 80 and the first conductive connection pillars 70 may be encapsulated multiple times with an encapsulation material such as an epoxy molding compound to ensure that the active chip 80 and the first conductive connection pillars 70 can be sufficiently encapsulated. Thereafter, portions of the first molding layer 90 and the passivation layer in the active chip 80 may be removed by a grinding process, thereby exposing the bottom surfaces of the second conductive bumps 110 (i.e., the surfaces of the second conductive bumps 110 facing away from the first redistribution layer 21) and the bottom surfaces of the first conductive connection pillars 70 (i.e., the surfaces of the first conductive connection pillars 70 facing away from the first redistribution layer 21), as shown in fig. 12. Next, the second conductive bump 110 and the second redistribution layer 100 and the first conductive connection post 70 and the second redistribution layer 100 are bonded. Thereafter, an outgoing conductive bump 101 may be formed on a surface of the second redistribution layer 100 facing away from the active chip 80 using an electroplating process, the outgoing conductive bump 101 being electrically connected to the second redistribution layer 100, as shown in fig. 13.

The present embodiment also provides a three-dimensional package structure, which may be formed by using the method for forming a three-dimensional package structure as shown in fig. 1 to 13. A schematic view of the three-dimensional package structure may be seen in fig. 10 and 13. As shown in fig. 2 to 13, the three-dimensional package structure includes:

a first rewiring layer 21, the first rewiring layer 21 comprising a first surface 211 and a second surface 212 opposite the first surface 211;

A functional chip 30 located on the first surface 211 of the first redistribution layer 21, and the functional chip 30 is electrically connected to the first redistribution layer 21;

An active chip 80 including a third surface 801 and a fourth surface 802 opposite to the third surface 801, wherein the active chip 80 is mounted on the second surface 212 of the first redistribution layer 21, the third surface 801 faces the second surface 212, and a conductive connection structure is at least located in the active chip 80;

a first plastic layer 90 encapsulates the active chip 80, and the conductive connection structure is exposed to a surface of the first plastic layer 90 facing away from the first redistribution layer 21.

The active chip 80 is formed by a bridge chip process, and the active chip 80 may be used as a bridge chip, the conductive connection structure is at least located in the active chip 80, and the conductive connection structure is exposed on the surface of the first plastic layer 90 of the active chip 80, so that the power signal and other electrical signals (such as control electrical signals) can be transmitted to the active chip 80 through the conductive connection structure, thereby forming a three-dimensional package structure, and realizing effective improvement of the performance of the package structure.

In some embodiments, the functional chip 30 includes a front side 301 and a back side 302 opposite the front side 301, the functional chip 30 is bonded to the first surface 211 of the first redistribution layer 21, and the front side of the functional chip 30 faces the first surface 211 of the first redistribution layer 21. In this embodiment, the functional chip 30 is flip-chip mounted on the first surface 211 of the first redistribution layer 21, so that a wire bonding process is not required, and the manufacturing difficulty of the three-dimensional package structure is further reduced.

In some embodiments, the three-dimensional package structure further comprises:

the second plastic layer 40 is located on the first surface 211 of the first redistribution layer 21, and the second plastic layer 40 at least covers the functional chip 30.

In some embodiments, the functional chip includes a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer, the back side 302 of the functional chip 30 being exposed to a surface of the second molding layer 40; the three-dimensional package structure further includes:

The heat dissipation layer 60 covers the back surface 302 of the functional chip 30, so as to enhance the heat dissipation performance of the functional chip 30 and the three-dimensional package structure as a whole.

In some embodiments, the third surface 801 of the active die 80 has a bonding layer 82 thereon, the bonding layer 82 is bonded to the second surface 212 of the first redistribution layer 21, and the bonding layer 82 electrically connects the first redistribution layer 21 and the active die 80. In this embodiment, the active chip 80 is connected to the second surface 212 of the first redistribution layer 21 through the solder layer 82, so that the problem of high bonding difficulty caused by direct bonding of the copper pillar on the active chip and the first redistribution layer is avoided, thereby simplifying the manufacturing process of the three-dimensional packaging structure and reducing the manufacturing difficulty of the three-dimensional packaging structure. Moreover, the bonding layer 82 can also act as a stress relief layer, relieving stress between the first redistribution layer 21 and the active die 80, thereby further improving the performance of the three-dimensional package structure.

In some embodiments, the conductive connection structure includes a first conductive bump 81 located on the fourth surface 802 of the active chip 80, a bottom surface of the first conductive bump 81 being exposed to a surface of the first molding layer 90; the three-dimensional package structure further includes:

A second redistribution layer 100 is located on a side of the active chip 80 facing away from the first redistribution layer 21, and the first conductive bump 81 is electrically connected to the second redistribution layer 100.

In some embodiments, the conductive connection structure includes a second conductive bump 110 located within the active chip 80, a bottom surface of the second conductive bump 110 being exposed to the fourth surface 802 of the active chip 80; the three-dimensional package structure further includes:

and a second redistribution layer 100 located on a side of the active chip 80 facing away from the first redistribution layer 21, and the second conductive bump 100 is electrically connected to the second redistribution layer 100.

According to the three-dimensional packaging structure and the forming method thereof provided by some embodiments of the present invention, the functional chip and the active chip are electrically connected by forming the first redistribution layer, and direct bonding connection of the functional chip and the active chip is not required, so that the manufacturing process of the packaging structure is simplified, and the manufacturing difficulty of the packaging structure is reduced. According to the embodiment, after the functional chip is attached to the first surface of the first rewiring layer, the active chip is attached to the second surface of the first rewiring layer, so that the influence of the process of attaching the active chip on the functional chip is avoided, the probability of deformation such as warping inside the packaging structure is reduced, and the performance of the packaging structure is improved. In this embodiment, the active chip is formed by using a bridge chip process, and the active chip may be used as a bridge chip, and a conductive connection structure is at least located in the active chip, and the conductive connection structure is exposed on a surface of a first plastic layer of the active chip for plastic packaging, so that a power signal and other electrical signals (such as control electrical signals) can be transmitted to the active chip through the conductive connection structure, thereby forming a three-dimensional package structure, and realizing effective improvement of performance of the package structure. According to other embodiments of the present invention, a soldering layer is disposed on the third surface of the active chip, and the active chip is connected to the second surface of the first redistribution layer through the soldering layer, so that the problem of high bonding difficulty caused by direct bonding of the copper pillar on the active chip and the first redistribution layer is avoided, and thus, the manufacturing process of the package structure is further simplified, and the manufacturing difficulty of the package structure is reduced. Moreover, the solder layer can also act as a stress relief layer, relieving stress between the first redistribution layer and the active die, thereby further improving the performance of the package structure.

The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims

1. The method for forming the three-dimensional packaging structure is characterized by comprising the following steps of:

forming at least a first plastic layer for plastic packaging the active chip;

2. The method of forming a three-dimensional package structure of claim 1, further comprising, prior to attaching an active die to the second surface of the first redistribution layer, the steps of:

3. The method of forming a three-dimensional package structure of claim 2, wherein the functional chip includes a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer; before attaching the active chip to the second surface of the first redistribution layer, the method further comprises the steps of:

4. The method of forming a three-dimensional package structure of claim 1, further comprising, prior to attaching an active die to the second surface of the first redistribution layer, the steps of:

5. The method of forming a three-dimensional package structure of claim 1, wherein the specific step of attaching an active die to the second surface of the first redistribution layer comprises:

Forming a soldering layer on the third surface of the active chip;

6. The method of claim 1, wherein the conductive connection structure comprises a first conductive bump on the fourth surface of the active chip, the first molding layer encapsulating the first conductive bump; the specific steps of exposing the conductive connection structure include:

7. The method of forming a three-dimensional package structure of claim 1, wherein the conductive connection structure comprises a second conductive bump within the active die; the specific steps of exposing the conductive connection structure include:

8. The method of forming a three-dimensional package structure of claim 1, further comprising the steps of, after exposing the conductive connection structure:

providing a second redistribution layer;

9. A three-dimensional package structure, comprising:

10. The three-dimensional package structure of claim 9, further comprising:

11. The three-dimensional package structure of claim 10, wherein the functional chip comprises a front side and a back side opposite the front side, the front side of the functional chip facing the first surface of the first redistribution layer, the back side of the functional chip being exposed to a surface of the second molding layer; the three-dimensional package structure further includes:

12. The three-dimensional package structure of claim 9, wherein the third surface of the active chip has a solder layer thereon, the solder layer is soldered to the second surface of the first redistribution layer, and the solder layer electrically connects the first redistribution layer and the active chip.

13. The three-dimensional package structure of claim 9, wherein the conductive connection structure comprises a first conductive bump on the fourth surface of the active chip, a bottom surface of the first conductive bump being exposed to a surface of the first molding layer; the three-dimensional package structure further includes:

14. The three-dimensional package structure of claim 9, wherein the conductive connection structure comprises a second conductive bump within the active die, a bottom surface of the second conductive bump being exposed to the fourth surface of the active die; the three-dimensional package structure further includes: