CN118113660B - FPGA delay optimization method, device, equipment, storage medium and program product - Google Patents
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Abstract
The invention relates to the technical field of FPGA (field programmable gate array), and discloses an FPGA delay optimization method, device, equipment, storage medium and program product, wherein the method comprises the following steps: acquiring an FPGA netlist to be optimized and corresponding physical information; extracting a preset number of key paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information; enumerating all look-up table combinations based on the critical path; determining the benefits of each lookup table combination, sorting, and reconstructing a Boolean function based on a sorting result to obtain an optimized substitution lookup table combination; updating the FPGA netlist to be optimized and corresponding physical information based on the alternative lookup table combination; and judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information. The method improves the delay optimization benefit and the optimization efficiency of the critical path.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to an FPGA delay optimization method, device, equipment, storage medium and program product.
Background
The critical path delay is a core index used to determine the performance of mapping a given user design to an FPGA chip, and the magnitude of the critical path delay affects the processing efficiency of the FPGA chip. Therefore, it is necessary to provide an FPGA delay optimization method to optimize the critical path delay.
Disclosure of Invention
In view of the above, the invention provides a method, a device, equipment, a storage medium and a program product for optimizing FPGA delay, so as to solve the problem of optimizing FPGA critical path delay.
In a first aspect, the present invention provides a method for optimizing FPGA latency, the method comprising:
Acquiring an FPGA netlist to be optimized and corresponding physical information, wherein the type of the physical information comprises layout information and wiring information;
Extracting a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information, wherein the preset number of critical paths are the paths with the longest delay in the FPGA netlist to be optimized and the corresponding physical information;
Enumerating all the lookup table combinations based on the critical path, wherein the lookup table combinations comprise a first lookup table and a second lookup table, and the output of the first lookup table is connected to the input of the second lookup table;
Determining the benefits of each lookup table combination, sorting, performing Boolean function reconstruction based on the sorting result to obtain an optimized alternative lookup table combination, wherein the alternative lookup table combination comprises a third lookup table and a fourth lookup table, and the output of the third lookup table is connected to the input of the fourth lookup table;
Updating the FPGA netlist to be optimized and corresponding physical information based on the alternative lookup table combination;
and judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
The FPGA delay optimization method provided by the embodiment of the invention improves the delay optimization benefits and the optimization efficiency of the critical path.
In an alternative embodiment, extracting a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information includes:
Inquiring whether the physical information contains the connection relation between ports or not to determine the type of the physical information;
if the connection relation between the ports is included, the type of the physical information is wiring information, a preset number of key paths are extracted, and the preset number is a constant which is greater than or equal to 1;
If the connection relation among the ports is not contained, the type of the physical information is layout information, and 1 critical path is extracted in each iterative optimization period.
The FPGA delay optimization method provided by the embodiment of the invention can provide different execution flows based on different types of the input FPGA netlist and the corresponding physical information, so that the benefit of the optimization result is ensured.
In an alternative embodiment, the boolean function reconstruction based on the ranking result comprises:
obtaining a target lookup table combination with highest benefit based on the sorting result, and obtaining the input condition of the target lookup table combination;
Performing preparation calculation based on the target lookup table combination to obtain evaluation margin of each input signal of the target lookup table combination;
determining all alternative look-up table combinations based on the input conditions of the target look-up table combinations;
determining the benefits of each alternative lookup table combination, and sorting from high to low;
Screening is performed based on the ranking results of the benefits of each alternative look-up table combination to obtain a target alternative look-up table combination.
According to the FPGA delay optimization method provided by the embodiment of the invention, the reconstruction is performed based on the Boolean function so as to obtain the alternative lookup table combination capable of equivalently replacing the lookup table combination, and the signals on the critical paths are moved to the non-critical paths so as to realize the delay optimization of the critical paths, thereby improving the optimization benefits and the optimization efficiency.
In an alternative embodiment, determining all alternative combinations of look-up tables based on the input of the target combination of look-up tables includes:
based on the number of input signals of the lookup table combinations and the constraint on the number of input of the substitution lookup table combinations, permutation and combination are carried out to determine all substitution lookup table combinations.
According to the FPGA delay optimization method provided by the embodiment of the invention, the optimization efficiency of reconstruction of the Boolean function is improved by enumerating the alternative lookup table combination.
In an alternative embodiment, the benefit of a look-up table combination is the product of the minimum evaluation margin of the previous look-up table input signal and the maximum evaluation margin of the next look-up table input signal in the look-up table combination;
The evaluation margin is calculated based on the following formula:
Where slack_e is the evaluation margin;
the slack is a margin of the signal, and the margin is used for representing a difference value between an expected time when the signal arrives at the port and an actual time when the signal arrives at the port;
the slack_max is the largest margin among all input signals in the lookup table combination;
the slack_min is the smallest margin in all input signals in the look-up table combination;
epsilon is a preset constant;
copy is a variable, and is a preset constant when the output of a previous look-up table in the combination of look-up tables is not only connected to the input of a next look-up table in the combination of look-up tables, and is 0 when the output of a previous look-up table in the combination of look-up tables is only connected to the input of a next look-up table in the combination of look-up tables.
According to the FPGA delay optimization method provided by the embodiment of the invention, the benefits are calculated through the method, and the lookup table combinations and the substitution lookup table combinations are ordered, so that the lookup table combinations with larger benefits are preferably reconstructed and the substitution lookup table combinations with larger benefits are selected, and the optimization effect is more remarkable.
In an alternative embodiment, the filtering based on the ranking results of the benefits of each alternative look-up table combination to obtain the target alternative look-up table combination includes:
Sequentially judging whether each alternative lookup table combination is legal or not based on the ordering result of the benefits of each alternative lookup table combination;
If legal alternative lookup table combinations exist in all the alternative lookup table combinations, taking the alternative lookup table combination with the highest benefit in the legal alternative lookup table combinations as a target alternative lookup table combination;
if the legal alternative lookup table combination does not exist in all the alternative lookup table combinations, the characterization lookup table combination cannot be optimized, and the optimization flow is ended.
According to the FPGA delay optimization method provided by the embodiment of the invention, the optimized result is screened in a way of calculating the truth table, so that delay optimization benefits are ensured.
In an alternative embodiment, updating the FPGA netlist to be optimized and the corresponding physical information based on the combination of the alternative look-up tables includes:
updating the FPGA netlist to be optimized based on the alternative lookup table combination;
if the type of the physical information is layout information, gradually laying out the layout information based on the updated FPGA netlist to be optimized so as to update the layout information;
And if the type of the physical information is wiring information, carrying out progressive layout and progressive wiring on the wiring information based on the updated FPGA netlist to be optimized so as to update the wiring information.
According to the FPGA delay optimization method provided by the embodiment of the invention, the fact that newly added lookup table nodes possibly exist in the netlist after the Boolean function reconstruction is completed is considered, so that physical information is required to be updated in a progressive layout or progressive layout and wiring mode according to different physical information types, and accordingly the updated netlist and layout information are ensured to still correspond.
In an alternative embodiment, determining whether delay optimization exists based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information includes:
Obtaining a corresponding preset number of updated critical paths based on the updated FPGA netlist to be optimized and the corresponding physical information;
Judging whether the delay of the updated critical path is reduced, if the delay is not reduced, indicating that delay optimization does not exist, and if the delay is reduced, indicating that delay optimization exists;
If the type of the physical information is layout information and delay optimization exists, outputting an optimized netlist and layout information; if the delay optimization does not exist, all changes are cleared, and the original input netlist and layout information are output;
If the type of the physical information is wiring information and delay optimization exists, the current reconstruction update is stored, the next iteration process is carried out, and if the delay optimization does not exist, the next iteration process is directly carried out.
According to the FPGA delay optimization method provided by the embodiment of the invention, the time sequence analysis precision is taken into consideration, the large-scale single optimization is carried out when the precision is difficult to ensure, and an iteration mechanism is introduced under the condition that the precision can be ensured, so that the optimization benefits are improved as much as possible.
In an alternative embodiment, the truth table replacing the look-up table combination is calculated by a boolean function reconstruction solver, the functions are expressed in a redundant manner inside the boolean function reconstruction solver, and the functions are solved by using bit operations.
According to the FPGA delay optimization method provided by the embodiment of the invention, the Boolean function solver for bit operation is reconstructed, a core part in the bit operation is extracted, so that a lot of repeated operations are reduced, the performance advantage of the solver is fully exerted, and the efficiency of the embodiment is greatly improved.
In a second aspect, the present invention provides an FPGA delay optimization device, including:
The acquisition module is used for acquiring the FPGA netlist to be optimized and corresponding physical information, wherein the type of the physical information comprises layout information and wiring information;
The extraction module is used for extracting a preset number of key paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information;
An enumeration module for enumerating all the lookup table combinations based on the critical path, wherein the lookup table combinations comprise a first lookup table and a second lookup table, and the output of the first lookup table is connected to the input of the second lookup table;
the reconstruction module is used for determining the benefits of each lookup table combination, sequencing, and performing Boolean function reconstruction based on the sequencing result to obtain an optimized alternative lookup table combination, wherein the alternative lookup table combination comprises a third lookup table and a fourth lookup table, and the output of the third lookup table is connected to the input of the fourth lookup table;
The updating module is used for updating the FPGA netlist to be optimized and the corresponding physical information based on the alternative lookup table combination;
And the confirmation module is used for judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
In a third aspect, the present invention provides a computer device comprising: the FPGA delay optimization method comprises a memory and a processor, wherein the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the FPGA delay optimization method of the first aspect or any corresponding implementation mode is executed.
In a fourth aspect, the present invention provides a computer readable storage medium, where computer instructions are stored on the computer readable storage medium, where the computer instructions are configured to cause a computer to perform the FPGA delay optimization method according to the first aspect or any implementation manner corresponding to the first aspect.
In a fifth aspect, the present invention provides a computer program product comprising computer instructions for causing a computer to perform the FPGA delay optimization method of the first aspect or any of its corresponding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram of an FPGA delay optimization method according to an embodiment of the invention;
FIG. 2 is a flow diagram of a Boolean function reconstruction process according to an embodiment of the invention;
FIG. 3 is another flow diagram of a Boolean function reconstruction process according to an embodiment of the invention;
FIG. 4 is a flow diagram of latency optimization based on layout information according to an embodiment of the present invention;
FIG. 5 is a flow diagram of delay optimization based on routing information in accordance with an embodiment of the present invention;
FIG. 6 is a block diagram of the structure of an FPGA delay optimization device according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
FPGA delay optimization is a key ring to ensure FPGA design performance, stability and efficiency. The FPGA delay optimization is carried out based on function reconstruction by redesigning or adjusting the structure and the behavior of the function so as to achieve the purposes of optimizing the FPGA delay and improving the overall performance, however, the traditional method for carrying out FPGA delay optimization based on function reconstruction is less, and the main pain point is long running time and small optimizing gain.
According to the embodiment of the invention, the netlist of the FPGA and the corresponding physical information are operated, so that the critical path delay of the FPGA is reduced. Specifically, the multi-thread and the high-efficiency solving method are used for carrying out high-efficiency solving under the condition of smaller running memory, meanwhile, the optimizing benefits are improved through multiple means such as multi-path optimization and sequencing optimization, and the optimizing range is expanded as much as possible through supporting the sharing of input and multiple output branches, so that the optimizing benefits are further improved. In addition, in order to further improve the operation efficiency and be suitable for more scenes, the embodiment of the invention designs corresponding optimization flows aiming at different physical information inputs. Therefore, by implementing the method and the device, delay optimization benefits and optimization efficiency of the critical path are remarkably improved.
According to an embodiment of the present invention, there is provided an FPGA delay optimization method embodiment, it should be noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logic sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than what is shown or described herein.
In this embodiment, an FPGA delay optimization method is provided, fig. 1 is a schematic flow diagram of an FPGA delay optimization method according to an embodiment of the present invention, and as shown in fig. 1, the flow includes the following steps:
Step S101, obtaining an FPGA netlist to be optimized and corresponding physical information.
The physical information is divided into two major categories, namely layout information and wiring information, wherein the wiring information comprises the layout information.
An FPGA netlist can be understood as an abstract circuit formed based on private nodes, where private is a basic element of the abstract circuit, such as a lookup table that is strongly related to embodiments of the present invention.
Step S102, extracting a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist and the corresponding physical information, wherein the preset number of critical paths are the paths with the longest delay in the FPGA netlist to be optimized and the corresponding physical information.
Specifically, the critical path consists of a plurality of basic logic units on the FPGA chip and a plurality of pins of each basic logic unit, and is the path with the longest delay in physical information.
Furthermore, the embodiment provides a targeted operation flow based on different inputs, performs large-scale single optimization on the input as layout information, and introduces an iteration mechanism under the condition that the input is wiring information.
Step S103, enumerating all the lookup table combinations based on the critical path.
Specifically, based on the logic nodes on the critical path, any two consecutive logic nodes can be regarded as a lookup table combination, and the possible lookup table combinations on the critical path are enumerated through an enumeration method.
Further, the combination of look-up tables includes a first look-up table and a second look-up table, and an output of the first look-up table is connected to an input of the second look-up table.
Step S104, determining the benefits of each lookup table combination, sorting, and reconstructing the Boolean function based on the sorting result to obtain the optimized alternative lookup table combination.
Specifically, based on the margin of the input signals of the lookup table combination, the evaluation margin of the input signals is calculated, and the benefit of the lookup table combination is calculated by the evaluation margin.
Further, the boolean function reconstruction in this embodiment essentially regards an n-input look-up table as a boolean function of n-variable, so that for a set of consecutive look-up table combinations LUTA, LUTB, if LUTA has an input number a and LUTB has an input number b, a set of consecutive LUTA, LUTB may represent a boolean function F having an input number a+b-1, and attempt to replace the look-up table combinations LUTA, LUTB with an equivalent set of replacement look-up table combinations LUTC, LUTD based on the boolean function, so-called equivalents, i.e. LUTC, LUTD may represent the same boolean function F.
Further, the reconstruction method is that, for a determined lookup table combination LUTA, LUTB, the input condition of the lookup table combination is obtained, and all possible substitution lookup table combinations are enumerated in combination with the constraint on the input number of substitution lookup table combinations LUTC, LUTD.
Further, a third look-up table and a fourth look-up table are included in the alternative look-up table combination, and an output of the third look-up table is connected to an input of the fourth look-up table.
Step S105, updating the FPGA netlist to be optimized and the corresponding physical information based on the alternative lookup table combination.
Specifically, there may be newly added look-up table nodes in the netlist after the reconstruction is completed, so that the netlist needs to be updated by means of an EDA tool based on the updated netlist in a progressive layout or progressive layout and wiring mode to ensure that the updated netlist and layout information still correspond.
And S106, judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
Specifically, the optimization result depends on the input netlist and the corresponding physical information, if the input physical information is layout information, the output is layout information, and if the input physical information is wiring information, the output is wiring information.
According to the FPGA delay optimization method provided by the embodiment, different processing flows are designed aiming at different physical information types, and when layout information with difficult guarantee of accuracy is processed, large-scale single optimization is performed, as shown in fig. 4; the wiring information with guaranteed processing precision is that an iteration mechanism is introduced, so that the optimization benefit can be guaranteed more effectively, as shown in fig. 5; in addition, the Boolean function formed by each lookup table combination is obtained and reconstructed through obtaining the critical path, so that the delay optimization of the critical path is realized, and the delay optimization benefit and the optimization efficiency are remarkably improved.
In some alternative embodiments, whether the physical information contains connection relations among ports is queried to determine the type of the physical information;
if the connection relation between the ports is included, the type of the physical information is wiring information, a preset number of key paths are extracted, and the preset number is a constant which is greater than or equal to 1;
If the connection relation among the ports is not contained, the type of the physical information is layout information, and 1 critical path is extracted in each iterative optimization period.
Specifically, if the input is an FPGA netlist and the corresponding layout information thereof, n key paths are found based on the input information, wherein n is a artificially defined constant which is greater than or equal to 1, and if n is equal to 3, the first three key paths with the longest delay are found; if the input is the FPGA netlist and the corresponding wiring information, 1 critical path is extracted in each iterative optimization period.
In some alternative embodiments, as shown in fig. 2, the step S104 includes:
And a step a1, obtaining a target lookup table combination with highest benefit based on the sequencing result, and obtaining the input condition of the target lookup table combination.
And a2, performing preparation calculation based on the target lookup table combination to obtain the evaluation margin of each input signal of the target lookup table combination.
Step a3, determining all the alternative lookup table combinations based on the input condition of the target lookup table combination.
Step a4, determining the benefit of each alternative lookup table combination based on the evaluation margin of the input signal, and sequencing from high to low.
And a step a5, screening based on the sorting result of the benefits of each alternative lookup table combination to obtain a target alternative lookup table combination.
The combination of the target lookup tables for which the highest benefit is obtained based on the sorting result is assumed to be LUTA, LUTB, and the boolean function reconstruction in this embodiment essentially regards an n-input lookup table LUT as a boolean function of n-variable, so that for a set of consecutive LUTA, LUTB, if the number of inputs of LUTA is a and the number of inputs of LUTB is b, the set of consecutive LUTA, LUTB can represent a boolean function F with an input number of a+b-1, and attempts to replace the equivalent set of consecutive LUTC and LUTD based on the boolean function reconstruction, so-called equivalent, i.e., LUTC and LUTD can represent the same boolean function F.
As shown in fig. 3, inputs of the reconstruction process are LUTA and LUTB, and first, a preparation operation is performed based on the inputs, the preparation operation including a remainder calculation of LUTB, and an evaluation margin calculation of an input signal. The remainder of the LUTB is calculated as a truth table of LUTB with LUTA outputs of 0 and 1, respectively, assuming that the original truth table of LUTB with two inputs is 1010, and bit 0 is connected to LUTA output, then the remainder of LUTB is 00 when LUTA output is 0, and the remainder of LUTB is 11 when LUTA output is 1.
After the preparation calculation is finished, all LUTC and LUTD input conditions are enumerated, profits are calculated for each condition, the order is from high to low, the results are screened sequentially from high to low based on the order of the profits, so that the lookup table combination LUTC and the LUTD which can equivalently replace the lookup table combination LUTA and LUTB are obtained, the delay optimization of a key path is realized through the multi-thread multi-path optimization and ordering optimization mode, and the optimization profits and the optimization efficiency are improved.
In some alternative embodiments, step a3 includes: based on the number of input signals of the lookup table combinations and the constraint on the number of input of the substitution lookup table combinations, permutation and combination are carried out to determine all substitution lookup table combinations.
Based on the input condition of the target lookup table combination LUTA, LUTB, the method for determining all the alternative lookup table combinations LUTC, LUTD is: all possible LUTC, LUTD combinations are enumerated based on the number of LUTA, LUTB inputs and the number of inputs constraints on LUTC and LUTD. For example, for a set of LUTA for 3 inputs and LUTB for 4 inputs, the following combinations will be enumerated: {3 input LUTC,4 input LUTD }, {4 input LUTC,3 input LUTD }, {2 input LUTC,5 input LUTD }, {5 input LUTC,2 input LUTD }; after the input signal distribution is determined, it is necessary to further determine which bit of the corresponding LUT each input signal is specifically connected to, and by connecting the signal with large margin to the bit with high delay and the signal with small margin to the bit with small delay, the overall delay is more uniform and the maximum delay is reduced.
In some alternative embodiments, the benefit of a look-up table combination is the product of the minimum evaluation margin of the previous look-up table input signal and the maximum evaluation margin of the next look-up table input signal in the look-up table combination;
The evaluation margin is calculated based on the following formula:
Where slack_e is the evaluation margin;
the slack is a margin of the signal, and the margin is used for representing a difference value between an expected time when the signal arrives at the port and an actual time when the signal arrives at the port;
the slack_max is the largest margin of all input signals in the combination of two consecutive look-up tables;
the slack_min is the smallest margin in all input signals in the two consecutive look-up table combinations;
epsilon is a preset constant;
copy is a variable, and is a preset constant when the output of a previous look-up table in a combination of look-up tables is not only connected to the input of a next look-up table in the combination of look-up tables, and is 0 when the output of a previous look-up table in the combination of look-up tables is only connected to the input of a next look-up table in the combination of look-up tables.
And sorting the lookup table combinations and the alternative lookup table combinations by calculating benefits, so that the lookup table combinations with larger benefits are preferably reconstructed and the alternative lookup table combinations with larger benefits are selected, and the optimization effect is more remarkable.
In some alternative embodiments, step a5 includes: sequentially judging whether each alternative lookup table combination is legal or not based on the ordering result of the benefits of each alternative lookup table combination;
If legal alternative lookup table combinations exist in all the alternative lookup table combinations, taking the alternative lookup table combination with the highest benefit in the legal alternative lookup table combinations as a target alternative lookup table combination;
if the legal alternative lookup table combination does not exist in all the alternative lookup table combinations, the characterization lookup table combination cannot be optimized, and the optimization flow is ended.
After all enumerated alternative look-up table combined benefit calculations are completed, the benefits are ranked from high to low and an attempt is made to convert LUTA, LUTB to LUTC, LUTD based on the beginning of the ranking. At this time, whether each group of alternative lookup table combinations are legal or not needs to be verified, if legal results exist in the alternative lookup table combinations, the alternative lookup table combination with the highest benefit is reserved as a target alternative lookup table combination; if all the alternative lookup table combinations are traversed to have no legal result, the group of lookup table combinations based on the key path cannot be optimized, and the optimization flow is directly ended. And verifying the substitution lookup table combination after the Boolean function reconstruction to obtain a feasible key path delay optimization result.
In some alternative embodiments, step a5 further comprises:
Sequentially calculating truth tables of the alternative lookup table combinations based on the sorting results of the benefits of the alternative lookup table combinations;
If the truth table of a group of alternative lookup tables can be successfully calculated, the alternative lookup table combination is characterized as legal;
if the truth table cannot be obtained by all the alternative lookup table combinations, the characterization lookup table combinations cannot be optimized, and the optimization flow is ended.
And judging whether each group of substitution lookup table combinations reconstructed by the Boolean function are legal or not by calculating a truth table. Since the input signals for LUTC and LUTD have been determined, if the truth table for LUTC and LUTD can be successfully calculated, it means that LUTA, LUTB can be converted to LUTC, LUTD. If traversing to a condition where LUTC and LUTD truth tables can be calculated, return directly to LUTC, LUTD. Otherwise, the next input allocation situation is traversed, if LUTC and LUTD of the truth table cannot be calculated after all the input allocation situations are traversed, the LUTA and LUTB cannot be reconstructed, and the process is finished directly. Through calculation of the truth table, whether the continuous lookup table combination LUTA and LUTB can be equivalently replaced by a group of continuous replacement lookup tables LUTC and LUTD is verified, so that the validity of the optimization result is ensured.
In some alternative embodiments, the step S105 includes:
updating the FPGA netlist to be optimized based on the alternative lookup table combination;
if the type of the physical information is layout information, gradually laying out the layout information based on the updated FPGA netlist to be optimized so as to update the layout information;
And if the type of the physical information is wiring information, carrying out progressive layout and progressive wiring on the wiring information based on the updated FPGA netlist to be optimized so as to update the wiring information.
Considering that newly added lookup table nodes possibly exist in the netlist after the completion of the Boolean function reconstruction, according to different types of physical information, the physical information is updated in a progressive layout or progressive layout and wiring mode through the self-contained functions in the EDA tool, so that the updated netlist and layout information still correspond.
In some alternative embodiments, the step S106 includes:
Obtaining a corresponding preset number of updated critical paths based on the updated FPGA netlist to be optimized and the corresponding physical information;
Judging whether the delay of the updated critical path is reduced, if the delay is not reduced, indicating that delay optimization does not exist, and if the delay is reduced, indicating that delay optimization exists;
If the type of the physical information is layout information and delay optimization exists, outputting an optimized netlist and layout information; if the delay optimization does not exist, all changes are cleared, and the original input netlist and layout information are output;
If the type of the physical information is wiring information and delay optimization exists, the current reconstruction update is stored, the next iteration process is carried out, and if the delay optimization does not exist, the next iteration process is directly carried out.
Judging whether delay optimization exists or not based on the updated netlist and the physical information, namely whether delay of a critical path is reduced or not, if the delay of the critical path is not reduced, indicating that delay optimization does not exist, and if the delay of the critical path is reduced, indicating that delay optimization exists.
The optimization flow of the layout information is shown in fig. 4, if delay optimization exists, the updated netlist and the layout information are reserved, otherwise, all changes are cleared to reserve the input netlist and the layout information.
The optimization flow of the wiring information is shown in fig. 5, if delay optimization exists, the current reconstruction update is saved, the next iteration process is entered, and if no delay optimization exists, the next iteration process is entered directly. And (3) the iteration process is carried out until the iteration round number reaches the upper limit a of the iteration round number or reaches the upper limit b of the continuous iteration non-optimization round number, namely, if the iteration round number does not reach the upper limit a of the iteration round number or the continuous iteration non-optimization round number does not reach the upper limit b, the iteration condition is considered to be met. Wherein a and b are constants set in advance, a is larger than or equal to b, and a netlist and corresponding wiring information after the final iteration is finished are output.
By considering that the accuracy of the delay information obtained based on different physical information is different, two different optimization flows are designed, and the obtained delay information is always in obvious error with the final actual result based on the optimization of the layout information, so that multiple iterations are not needed, the running time is greatly reduced, and the running efficiency is improved; based on the optimization of the wiring information, the accuracy of the delay information obtained by the time sequence analysis tool is very close to the actual situation, so that one key path can be optimized at a time by an iteration means, and the iteration result with the optimization effect is saved, so that the optimization effect is accumulated.
In some alternative embodiments, step a5 further comprises: the truth table for replacing the lookup table combination is obtained by calculating through a Boolean function reconstruction solver, the interior of the Boolean function reconstruction solver expresses the function in a redundant mode, and the function is solved by using bit operation.
The solver expresses the functions in a redundant mode, so that the storage space is greatly saved, for example, in general, LUTA and LUTB are 6 input LUTs, and then the number of inputs of the boolean function formed by the solver is 6+6-1=11. Whereas a boolean function representing 11 variables by a truth table requires 211 bits of memory, if we use a remainder form, only the truth table of LUTA (26 bits) and the remainder of LUTB (25 x 2) are needed, for a total of 128 bits of memory.
The solver furthermore integrates a way of combining DC-based recording with DC masking, solving the DC problem completely by bit manipulation, so that there is little overhead in the presence of DC. However, if the solver is directly used, the inputs of the solver are LUTA, LUTB and the input constraint conditions of the LUTC and LUTD, the return value of the solver is the combination of LUTC and LUTD which meet the constraint conditions, and the direct use cannot meet the requirements well, so that there is an optimization space in performance. Therefore, the embodiment performs secondary development on the solver, extracts the core links therein, and integrates the core links into the framework of the embodiment. After extraction, the input to the solver becomes: 1. LUTA, LUTB Yu Zishi, 2, an input combination of LUTC, LUTD, 3, DC recordings.
Therefore, compared with the direct use of the solver, the method omits a plurality of repeated operation links, thereby improving the operation efficiency, and the Boolean function formed by the LUTA and the LUTB can be expressed under the storage resource as small as possible through the residual expression, so that the method is easier to use in the subsequent trial transformation links.
The embodiment also provides an FPGA delay optimizing device, which is used for implementing the above embodiment and the description of the preferred embodiment are omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The embodiment provides an FPGA delay optimizing apparatus, as shown in fig. 6, including:
The obtaining module 501 is configured to obtain an FPGA netlist to be optimized and corresponding physical information, where the type of the physical information includes layout information and routing information.
The extracting module 502 is configured to extract a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information.
An enumeration module 503, configured to enumerate all combinations of lookup tables based on the critical path, where the combinations of lookup tables include a first lookup table and a second lookup table, and an output of the first lookup table is connected to an input of the second lookup table.
And a reconstruction module 504, configured to determine benefits of each lookup table combination, perform ranking, perform boolean function reconstruction based on the ranking result, and obtain an optimized alternative lookup table combination, where the alternative lookup table combination includes a third lookup table and a fourth lookup table, and an output of the third lookup table is connected to an input of the fourth lookup table.
And the updating module 505 is configured to update the FPGA netlist to be optimized and the corresponding physical information based on the alternative look-up table combination.
And the confirmation module 506 is configured to determine whether delay optimization exists based on the updated FPGA netlist to be optimized and the corresponding physical information, and determine an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
In some alternative embodiments, the extraction module 502 includes:
And the inquiring sub-module is used for inquiring whether the physical information contains the connection relation between the ports so as to determine the type of the physical information.
In some alternative embodiments, the reconstruction module 504 includes:
The sub-module for obtaining input signals is used for obtaining the target lookup table combination with highest benefit based on the sequencing result and obtaining the input condition of the target lookup table combination.
And the preparation calculation sub-module is used for carrying out preparation calculation based on the target lookup table combination to obtain the evaluation margin of each input signal of the target lookup table combination.
And the function reconstruction sub-module is used for determining all the alternative lookup table combinations based on the input conditions of the target lookup table combinations.
And the sequencing sub-module is used for determining the benefits of each alternative lookup table combination based on the evaluation margin of the input signal and sequencing from high to low.
And the screening sub-module is used for screening based on the sorting result of the benefits of each alternative lookup table combination so as to obtain the target alternative lookup table combination.
In some alternative embodiments, the function reconstruction submodule includes:
And the permutation and combination unit is used for permutation and combination based on the number of input signals of the lookup table combinations and the constraint on the number of input signals of the substitution lookup table combinations, and determining all substitution lookup table combinations.
In some alternative embodiments, the screening sub-module includes:
and a calculation profit unit for calculating the profit of each alternative lookup table.
In some alternative embodiments, the screening sub-module further comprises:
And the legal judging unit is used for judging whether the result of each alternative lookup table is legal or not.
In some alternative embodiments, the legal judgment unit includes:
and the calculation truth table subunit is used for verifying whether each alternative lookup table combination is legal or not by calculating the truth table of each alternative lookup table combination.
In some alternative embodiments, the update module 505 includes:
and the updating netlist sub-module is used for updating the FPGA netlist to be optimized based on the alternative lookup table combination.
In some alternative embodiments, the validation module 506 includes:
And the updated critical path sub-module is used for obtaining a corresponding preset number of updated critical paths based on the updated FPGA netlist to be optimized and the corresponding physical information.
And the delay calculation sub-module is used for judging whether the delay of the updated critical path is reduced.
In some alternative embodiments, the computing truth table subunit includes:
A solver component for providing a boolean function solver to calculate a truth table for the alternative look-up table combinations.
Further functional descriptions of the above respective modules are the same as those of the above corresponding embodiments, and are not repeated here.
The FPGA delay optimization device in this embodiment is presented in the form of functional units, where the units are ASIC (Application SPECIFIC INTEGRATED Circuit) circuits, processors and memories that execute one or more software or firmware programs, and/or other devices that can provide the above functions.
The embodiment of the invention also provides computer equipment, which is provided with the FPGA delay optimizing device shown in the figure 6.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 7, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 7.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Portions of the present invention may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or aspects in accordance with the present invention by way of operation of the computer. Those skilled in the art will appreciate that the form of computer program instructions present in a computer readable medium includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (14)
1. An FPGA delay optimization method, comprising:
Acquiring an FPGA netlist to be optimized and corresponding physical information, wherein the type of the physical information comprises layout information and wiring information;
extracting a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information, wherein the preset number of critical paths are the paths with the longest delay in the FPGA netlist to be optimized and the corresponding physical information;
Enumerating all combinations of look-up tables based on the critical path, the combinations of look-up tables including a first look-up table and a second look-up table, and an output of the first look-up table being connected to an input of the second look-up table;
determining the benefits of each lookup table combination, sorting, and carrying out Boolean function reconstruction based on the sorting result to obtain an optimized alternative lookup table combination, wherein the alternative lookup table combination comprises a third lookup table and a fourth lookup table, and the output of the third lookup table is connected to the input of the fourth lookup table;
updating the FPGA netlist to be optimized and corresponding physical information based on the substitution lookup table combination;
And judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
2. The method of claim 1, wherein the extracting a preset number of critical paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information comprises:
inquiring whether the physical information contains connection relations among ports or not to determine the type of the physical information;
if the connection relation between the ports is included, the type of the physical information is wiring information, the preset number of key paths are extracted, and the preset number is a constant which is greater than or equal to 1;
And if the connection relation between the ports is not contained, the type of the physical information is layout information, and 1 critical path is extracted in each iterative optimization period.
3. The method of claim 1, wherein the performing boolean function reconstruction based on the ranking result comprises:
obtaining a target lookup table combination with highest benefit based on the sorting result, and obtaining the input condition of the target lookup table combination;
Performing preparation calculation based on the target lookup table combination to obtain evaluation margin of each input signal of the target lookup table combination;
Determining all of the alternative look-up table combinations based on the input conditions of the target look-up table combinations;
Determining the benefit of each alternative lookup table combination based on the evaluation margin of the input signal, and sorting from high to low;
and screening based on the sorting result of the benefits of each alternative lookup table combination to obtain a target alternative lookup table combination.
4. A method according to claim 3, wherein said determining all of said alternative look-up table combinations based on input conditions of said target look-up table combinations comprises:
And based on the number of input signals of the lookup table combinations and the constraint on the number of input signals of the substitution lookup table combinations, performing permutation and combination to determine all the substitution lookup table combinations.
5. A method according to claim 3, wherein the benefit of the combination of look-up tables is the product of the minimum evaluation margin of the previous look-up table input signal and the maximum evaluation margin in the subsequent look-up table input signal in the combination of look-up tables;
the evaluation margin is calculated based on the following formula:
Where slack_e is the evaluation margin;
A slot is a margin of a signal that characterizes a difference between an expected time of arrival of the signal at a port and an actual time of arrival of the signal at the port;
the slack_max is the largest margin among all input signals in the lookup table combination;
slack_min is the smallest of the margins in all input signals in the look-up table combination;
epsilon is a preset constant;
copy is a variable, and is a preset constant when the output of a previous look-up table in the combination of look-up tables is not only connected to the input of a next look-up table in the combination of look-up tables, and is 0 when the output of a previous look-up table in the combination of look-up tables is only connected to the input of a next look-up table in the combination of look-up tables.
6. The method of claim 3, wherein said filtering based on the ranked results of the benefits of each of said alternative look-up table combinations to obtain a target alternative look-up table combination comprises:
sequentially judging whether each alternative lookup table combination is legal or not based on the sorting result of the benefits of each alternative lookup table combination;
if legal alternative lookup table combinations exist in all the alternative lookup table combinations, taking the alternative lookup table combination with the highest benefit in the legal alternative lookup table combinations as the target alternative lookup table combination;
If the legal alternative lookup table combination does not exist in all the alternative lookup table combinations, the lookup table combinations are characterized to be not optimized, and the optimization flow is ended.
7. The method of claim 6, wherein the sequentially determining whether each of the alternate look-up table combinations is valid based on the ranking result of the benefits of each of the alternate look-up table combinations comprises:
sequentially calculating truth tables of the alternative lookup table combinations based on the sorting results of benefits of the alternative lookup table combinations;
If the truth table of a group of the alternative lookup tables can be successfully calculated, the alternative lookup table combination is characterized as legal;
If the truth table cannot be obtained by all the alternative lookup table combinations, the lookup table combinations are characterized to be not optimized, and the optimization flow is ended.
8. The method of claim 1, wherein updating the netlist and corresponding physical information of the FPGA to be optimized based on the combination of alternative look-up tables comprises:
updating the FPGA netlist to be optimized based on the substitution lookup table combination;
If the type of the physical information is layout information, gradually laying out the layout information based on the updated FPGA netlist to be optimized so as to update the layout information;
And if the type of the physical information is wiring information, carrying out progressive layout and progressive wiring on the wiring information based on the updated FPGA netlist to be optimized so as to update the wiring information.
9. The method of claim 1, wherein the determining whether delay optimization exists based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information, comprises:
obtaining a corresponding preset number of updated critical paths based on the updated FPGA netlist to be optimized and the corresponding physical information;
Judging whether the delay of the updated critical path is reduced, if the delay is not reduced, indicating that delay optimization does not exist, and if the delay is reduced, indicating that delay optimization exists;
if the type of the physical information is layout information and delay optimization exists, outputting an optimized netlist and layout information; if the delay optimization does not exist, all changes are cleared, and the original input netlist and layout information are output;
If the type of the physical information is wiring information and delay optimization exists, the current reconstruction update is stored, the next iteration process is entered, and if the delay optimization does not exist, the next iteration process is entered directly.
10. The method of claim 7, wherein the truth table for the alternate look-up table combination is calculated by a boolean function reconstruction solver that expresses the function internally by a remainder and solves using bit operations.
11. An FPGA delay optimisation apparatus, the apparatus comprising:
the acquisition module is used for acquiring the FPGA netlist to be optimized and corresponding physical information, wherein the type of the physical information comprises layout information and wiring information;
the extraction module is used for extracting a preset number of key paths corresponding to the type of the physical information based on the FPGA netlist to be optimized and the corresponding physical information;
an enumeration module, configured to enumerate all combinations of look-up tables based on the critical path, where the combinations of look-up tables include a first look-up table and a second look-up table, and an output of the first look-up table is connected to an input of the second look-up table;
The reconstruction module is used for determining the benefits of each lookup table combination, sequencing, and performing Boolean function reconstruction based on the sequencing result to obtain an optimized alternative lookup table combination, wherein the alternative lookup table combination comprises a third lookup table and a fourth lookup table, and the output of the third lookup table is connected to the input of the fourth lookup table;
The updating module is used for updating the FPGA netlist to be optimized and the corresponding physical information based on the alternative lookup table combination;
And the confirmation module is used for judging whether delay optimization exists or not based on the updated FPGA netlist to be optimized and the corresponding physical information, and determining an optimization result of the FPGA netlist to be optimized and the corresponding physical information.
12. A computer device, comprising:
A memory and a processor in communication with each other, the memory having stored therein computer instructions which, upon execution, cause the processor to perform the method of any of claims 1 to 10.
13. A computer-readable storage medium, comprising:
the computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any of claims 1 to 10.
14. A computer program product comprising computer instructions for causing a computer to perform the method of any one of claims 1 to 10.
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