CN117291128B - Method, computer device and medium for automating chip design engineering - Google Patents
Method, computer device and medium for automating chip design engineering Download PDFInfo
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Abstract
The application relates to the field of computer technology and provides a method, computer equipment and medium for chip design engineering automation. The method includes obtaining a first logic design code and a first command; parsing the commands to determine a plurality of place and route policies and a corresponding plurality of design suites; a plurality of design suites are mobilized, and the first logic design codes are respectively and comprehensively operated to obtain a plurality of corresponding layout and wiring results; respectively carrying out time sequence analysis on the layout wiring results to obtain a plurality of corresponding time sequence analysis results; selecting one or more timing analysis results meeting the timing constraint requirements based on the timing constraint requirements; selecting an optimal timing analysis result and a corresponding first design kit of the plurality of design kits; the first design suite is selectively mobilized to perform a synthesis operation on the second logic design code based on differences between the first logic design code and the second logic design code. Thus improving the degree of automation and improving the efficiency.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, a computer device, and a medium for chip design engineering automation.
Background
In the fields of data centers, internet of vehicles, high-performance computing, communication, aviation, consumer electronics, etc., there is a great deal of demand for chip design, such as the need to design various types of intelligent network cards. In chip design engineering, logic design of a primary function is sometimes implemented using, for example, a field programmable gate array (Field Programmable Gate Array, FPGA) and is operated by a graphical user interface (Graphics User Interface, GUI) of a development tool, such as selecting a design suite, to generate an executable logic file. A large number of register transfer stages (Register Transfer Level, RTL) need to be created in the chip design engineering and multiple code iterations are performed. In the prior art, a graphic user interface of a development tool is used for selecting a design suite and executing comprehensive operation, files are required to be imported one by one and complicated operation is required, so that the efficiency is low, errors are easy to occur, and the overall optimization is not facilitated.
For this reason, the present application provides a method, a computer device, and a medium for automating chip design engineering, which are used to solve the technical problems in the prior art.
Disclosure of Invention
In a first aspect, the present application provides a method for chip design engineering automation. The method comprises the following steps: obtaining a first logic design code associated with a first chip design and a first command; parsing the first command to determine a plurality of place and route policies and to determine a plurality of design suites of a development tool that are in one-to-one correspondence with the plurality of place and route policies; the plurality of design kits of the development tool are mobilized, and the first logic design codes are respectively and comprehensively operated to obtain a plurality of layout and wiring results which are in one-to-one correspondence with the plurality of layout and wiring strategies; respectively carrying out time sequence analysis on the plurality of layout wiring results to obtain a plurality of time sequence analysis results which are in one-to-one correspondence with the plurality of layout wiring results; selecting one or more timing analysis results from the plurality of timing analysis results that meet the timing constraint requirements based on the timing constraint requirements associated with the first chip design; selecting an optimal timing analysis result corresponding to the first logic design code from the one or more timing analysis results, wherein the optimal timing analysis result corresponds to a first place and route result of the plurality of place and route results, the first place and route result corresponds to a first place and route policy of the plurality of place and route policies, the first place and route policy corresponds to a first design suite of the plurality of design suites; the first design suite is selectively mobilized to perform a synthesis operation on a second logic design code associated with the first chip design based on differences between the first logic design code and the second logic design code.
According to the first aspect of the application, the requirements of the front-end circuit logic design and the verification requirements of the rear-end physical layout file are considered, and the requirements can be conveniently integrated into various development tools so as to improve the degree of automation of comprehensive operation, improve the overall efficiency and reduce the error probability.
In a possible implementation manner of the first aspect of the present application, the method further includes: parsing the first command to determine a first policy run, invoking the plurality of design suites of the development tool based on the first policy run.
In one possible implementation manner of the first aspect of the present application, the first policy operation manner includes invoking, in parallel, at least one design suite of the plurality of design suites corresponding to at least one of the plurality of place and route policies.
In a possible implementation manner of the first aspect of the present application, the first policy running manner further includes a code update configuration, and the first logic design code is selectively updated in a process of mobilizing the plurality of design suites of the development tool based on the code update configuration.
In a possible implementation manner of the first aspect of the present application, the first policy operation manner further includes a computing cluster submitting policy, based on which the plurality of layout wiring policies are submitted to the respective computing clusters in order to mobilize the plurality of design suites of the development tool.
In a possible implementation manner of the first aspect of the present application, each timing analysis result of the plurality of timing analysis results includes a logic gate setup time and a logic gate hold time of a layout result corresponding to the timing analysis result of the plurality of layout results.
In a possible implementation manner of the first aspect of the present application, the timing constraint requirement includes a maximum logic gate setup time and a minimum logic gate hold time.
In a possible implementation manner of the first aspect of the present application, the optimal timing analysis result is a risk-lowest result.
In a possible implementation manner of the first aspect of the present application, when a difference between the first logic design code and the second logic design code is smaller than a preset threshold value, the first design suite is mobilized to perform a comprehensive operation on the second logic design code.
In a possible implementation manner of the first aspect of the present application, when a difference between the first logic design code and the second logic design code exceeds the preset threshold, the plurality of design suites of the development tool are mobilized to perform comprehensive operation and timing analysis on the second logic design code, and a second design suite of the plurality of design suites corresponding to an optimal timing analysis result corresponding to the second logic design code is determined.
In a possible implementation manner of the first aspect of the present application, the first logic design code is a register transfer level code.
In a possible implementation manner of the first aspect of the present application, the plurality of placement and routing strategies includes one or more of the following: the layout and wiring strategy with the shortest running time, the layout and wiring strategy with the optimal area and the layout and wiring strategy with the shortest wiring delay.
In a possible implementation manner of the first aspect of the present application, the plurality of placement and routing strategies each conform to a layout design requirement associated with the first chip design, the layout design requirement including a routing specification and a transistor density.
In a possible implementation manner of the first aspect of the present application, the first chip is designed for a data center, a car networking, a high performance computing, a communication, an aviation or a consumer electronics.
In a possible implementation manner of the first aspect of the present application, the first chip design is a field programmable gate array chip, the development tool is a field programmable gate array development tool, and the first command is based on a tool command language.
In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.
In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a chip design engineering provided in an embodiment of the present application;
FIG. 2 is a schematic flow chart of a method for chip design engineering automation according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
Fig. 1 is a schematic diagram of a chip design engineering according to an embodiment of the present application. As shown in fig. 1, the chip design engineering includes a plurality of nodes, and in fig. 1, a system design node 101, a function allocation node 102, an analog circuit design simulation node 103, a digital circuit design simulation node 104, a digital-analog hybrid design simulation node 105, a logic design node 106, a synthesis node 107, and a back-end simulation design node 110 are schematically shown. At the system design node 101, a specification definition of the chip design is determined, including a requirement analysis and a determination of an overall design direction, such as determining a cost control level, a power consumption sensitivity level, a supported connection mode, a system security level, and the like, and an application scenario requirement, a user requirement, an industry protocol standard requirement, and the like may also be considered. On the basis of the specification definition of the chip design determined by the system design node 101, the function allocation node 102 further determines design details of the chip architecture, the service module, the power supply system, and the like, including performing function allocation and unit division, such as determining interactions, specific interfaces, and the like between the systems. Next, for the design and simulation of the analog circuit portion, the simulation is performed by the analog circuit design simulation node 103; and for the design and simulation of the digital circuit portion, through digital circuit design simulation node 104. After the respective corresponding circuit designs and simulation verification are completed through the analog circuit design simulation node 103 and the digital circuit design simulation node 104, respectively, the digital-analog mixed design simulation node 105 is executed to integrate the analog circuit part and the digital circuit part of the chip design, thereby verifying that the chip design has the required functions, the correctness of the logic time sequence and the like, and providing the corresponding standard specifications, the coding style and the environment architecture of the unified verification platform and the like through the verification methodology. The circuit design solution obtained at the digital-to-analog hybrid design simulation node 105 is then converted into logic design code, such as register transfer level (Register Transfer Level, RTL) code, at logic design node 106, which may be, for example, RTL code compiled. In the whole chip design engineering, a large number of register transmission level codes may need to be generated, and multiple code iterations may need to be performed, for example, the functional allocation and circuit logic design of the chip design may be adjusted due to the requirement change, the feedback of the subsequent nodes, and the like. Then, at the synthesis node 107, the logic design code is converted into a gate level circuit netlist (netlist), and circuit layout (floor plan) and routing (routing) are performed to obtain a specific circuit routing structure, and finally, a logic executable file is obtained. Then, at the back-end simulation design node 110, integrated circuit layout design and rule detection is completed for subsequent chip manufacturers to perform chip fabrication. Here, the logic design code obtained at the logic design node 106 and the logic executable file obtained at the synthesis node 107 represent the results of front-end emulation design, that is, register transfer level code description of hardware behavior, structure and data flow of the circuitry under the chip design scheme, and generation of corresponding gate level circuit netlists and logic executable files. The back-end simulation design node 110 generates an integrated circuit layout on the basis of a logic executable file, that is, converts the result of logic synthesis (gate-level netlist) into a physical layout file on the basis of physical design through a layout and wiring technology, wherein the physical layout file contains the shape, area and position information of each hardware unit on a chip. Rule checking at the back-end simulation design node 110 includes design rule checking (Design Rule Check, DRC) verification, e.g., to determine that the layout design complies with the relevant design rule requirements of the manufacturing process and meets timing, area, power consumption, etc., and layout logic diagram matching (Layout Versus Schematics, LVS) verification, i.e., to determine a match between the physical layout file and the outcome of the front-end simulation design. The feedback from the back-end design-emulation node 110 may enable the modification of the circuit logic design in the front-end design-emulation link, which requires the generation of new register transfer level codes and code iteration, and thus requires the comprehensive operation of the new logic design codes to obtain a new logic executable file. The logic design node 106 and the synthesis node 107 serve as intermediate links between the front-end simulation design link and the back-end simulation design link, which means conversion from the front-end circuit logic design to the back-end physical layout file. Therefore, on one hand, the requirements of the circuit logic design of the front end, including frequent code iteration and a large amount of simulation verification, and on the other hand, the requirements of the verification of the physical layout file of the back end, including compliance with the relevant rules of the manufacturing process, such as compliance with the constraints of wiring specifications and transistor density, are required to be considered. In addition, development tools such as automated synthesis operations of electronic design automation (Electronic Design Automation) are typically used to import logical executables and perform synthesis operations. However, manual selection of the design suite and multiple button operations, such as importing the required logic executables one by one, are required on the EDA software's operating interface, which results in inefficiency and error-prone. In addition, the front-end design link needs to perform simulation verification and code iteration frequently, and feedback of the back-end simulation design link may also cause code iteration, so new codes need to be imported frequently, which all increase the operation complexity and difficulty of the comprehensive node 107. Therefore, the embodiment of the application provides a method for chip design engineering automation, which not only considers the requirements of front-end circuit logic design and the verification requirements of rear-end physical layout files, but also can be conveniently integrated into various development tools so as to improve the automation degree of comprehensive operation, improve the overall efficiency and reduce the error probability. As described in further detail below in connection with fig. 2.
Fig. 2 is a schematic flow chart of a method for chip design engineering automation according to an embodiment of the present application. As shown in fig. 2, the method for chip design engineering automation includes the following steps.
Step S202: a first logic design code associated with a first chip design is obtained along with a first command.
Step S204: the first command is parsed to determine a plurality of place and route policies and a plurality of design suites of a development tool that are in one-to-one correspondence with the plurality of place and route policies.
Step S206: and invoking the plurality of design kits of the development tool, and respectively carrying out comprehensive operation on the first logic design codes to obtain a plurality of layout and wiring results which are in one-to-one correspondence with the plurality of layout and wiring strategies.
Step S208: and respectively carrying out time sequence analysis on the plurality of layout wiring results to obtain a plurality of time sequence analysis results which are in one-to-one correspondence with the plurality of layout wiring results.
Step S210: one or more timing analysis results that meet the timing constraint requirements are selected from the plurality of timing analysis results based on the timing constraint requirements associated with the first chip design.
Step S212: and selecting an optimal time sequence analysis result corresponding to the first logic design code from the one or more time sequence analysis results, wherein the optimal time sequence analysis result corresponds to a first layout wiring result in the plurality of layout wiring results, the first layout wiring result corresponds to a first layout wiring strategy in the plurality of layout wiring strategies, and the first layout wiring strategy corresponds to a first design kit in the plurality of design kits.
Step S214: the first design suite is selectively mobilized to perform a synthesis operation on a second logic design code associated with the first chip design based on differences between the first logic design code and the second logic design code.
Referring to the above steps, in step S202, a first logic design code and a first command are obtained. Here, the first logic design code is associated with a first chip design. In some embodiments, the first logic design code is a register transfer level code. The first logic design code includes the functional assignment of the first chip design, the circuit logic design, and the like. The first logic design code may be an entirety or a portion of the first chip design. For example, the first chip design is a data processor for a data center, and the first logic design code may be the entirety of the data processor or may be one or more modules, units, modules, etc. in the data processor. In the entire chip design engineering, a large number of logic design codes associated with the first chip design need to be generated, for example, corresponding logic design codes are generated for respective modules, units, modules, etc. of the first chip design, and code iterations need to be performed frequently. Here, the first command is used to promote the degree of automation of the chip design engineering. By obtaining the first command at step S202, a mode of manually operating a graphical user interface or the like is replaced. The first command may be obtained through, for example, a keyboard or any other suitable input device. Next, at step S204, the first command is parsed to determine a plurality of place and route policies and a plurality of design suites of the development tool that are in one-to-one correspondence with the plurality of place and route policies. Here, the development tool may be, for example, electronic design automation software, such as a field programmable gate array development tool for designing a field programmable gate array chip. Parsing the first command may be by, for example, command line parsing or any suitable text parsing means. By parsing the first command, a plurality of placement and routing strategies may be determined. As described above, the key link affecting the development efficiency of the chip design is the transition from the front-end simulation design link to the back-end simulation design link, which not only needs to consider frequent code iteration and a large number of simulation verifications of the front-end simulation design, but also needs to consider the physical layout related requirements of the back-end. Therefore, through different layout and wiring strategies, namely in the process of performing comprehensive operation, namely in the process of converting logic design codes into a gate-level circuit netlist and performing layout and wiring to finally obtain a logic executable file, the logic executable file can be optimized and adjusted, so that the requirements of application scenes can be better adapted, for example, the requirements of industries or communication protocols where the logic design codes are located on time sequence operation can be met, and the requirements of specific application scenes such as fields of data centers, internet of vehicles, high-performance computing, communication, aviation, consumer electronics and the like can be better adapted. The development tool provides different design suites, and the existing development tool can be conveniently adapted to realize automation operation by analyzing the first command to determine a plurality of layout wiring strategies and determining a plurality of design suites corresponding to the plurality of layout wiring strategies one by one.
With continued reference to fig. 2, in step S206, the plurality of design suites of the development tool are mobilized, and the first logic design codes are respectively comprehensively operated to obtain a plurality of layout and wiring results corresponding to the plurality of layout and wiring strategies one to one. In some embodiments, the various placement and routing strategies may include, for example, shortest run-time, area optimization, shortest routing delay, etc., which focus on a certain aspect or feature, exerting an impact on the comprehensive operation of the same logic design code, resulting in a corresponding optimization effect on the final logic executable. Here, since a plurality of design suites are determined by parsing the first command in step S204, the plurality of design suites of the development tool may be automatically mobilized in step S206, that is, the design suite on the graphical user interface does not need to be manually selected, so that the manual selection of the design suite on the operation interface of the EDA software and the multiple button operations may be avoided, which is advantageous for improving efficiency and reducing error probability. Next, in step S208, the plurality of layout and wiring results are respectively subjected to timing analysis to obtain a plurality of timing analysis results corresponding to the plurality of layout and wiring results one by one. And a plurality of layout and wiring results which are in one-to-one correspondence with the plurality of layout and wiring strategies and reflect optimization on different emphasis or characteristics, but all the layout and wiring results are required to meet the overall time sequence constraint requirement, so that the risk of chip design errors can be reduced, and the process preparation condition changes such as voltage and temperature conditions can be better dealt with. To this end, in step S210, one or more timing analysis results that meet the timing constraint requirements are selected from the plurality of timing analysis results based on the timing constraint requirements associated with the first chip design. Here, the timing constraint requirements associated with the first chip design may relate to an application scenario, industry, communication protocol, etc. of the first chip design.
With continued reference to fig. 2, based on a plurality of layout and routing strategies, the comprehensive operation process of the first logic design code is respectively optimized and adjusted to obtain a plurality of layout and routing results, then the plurality of layout and routing results are respectively subjected to time sequence analysis to obtain a plurality of time sequence analysis results corresponding to the plurality of layout and routing results one by one, and one or more time sequence analysis results meeting the time sequence constraint requirements are selected from the plurality of time sequence analysis results. Next, in step S212, an optimal timing analysis result corresponding to the first logic design code is selected from the one or more timing analysis results. In some embodiments, the optimal timing analysis results are the lowest risk timing analysis results, which helps to improve system stability. In other embodiments, the optimal timing analysis results may refer to any suitable timing analysis aspect of the risk assessment system. In some application scenarios, such as data centers, device interconnection, etc., there are high requirements on data transmission rate, response time, bit error rate, etc., and these are reflected in the chip design to have corresponding requirements on setup time and hold time between logic gates inside the chip, and other timing analysis characteristics, etc. For this reason, it is necessary to consider the complex situations of the chip in actual production and actual application, such as the change of process corner conditions in the manufacturing process, the influence of operating voltage, external temperature, etc., that is, consider the possibility that the chip can still work normally in extreme cases, and select the optimal time sequence analysis result corresponding to the first logic design code from the one or more time sequence analysis results under these considerations, thereby having good system stability and lower error risk. In addition, an optimal timing analysis result selected from the one or more timing analysis results corresponds to a first one of the plurality of place and route results, the first place and route result corresponding to a first one of the plurality of place and route strategies, the first place and route strategy corresponding to a first one of the plurality of design suites. Thus, on the one hand, the comprehensive operation process of the first logic design code is optimized and adjusted through various layout and wiring strategies, and one or more time sequence analysis results meeting the time sequence constraint requirements are selected based on the time sequence constraint requirements associated with the first chip design; on the other hand, an optimal time sequence analysis result is selected from the one or more time sequence analysis results, and then a first design kit corresponding to the optimal time sequence analysis result is determined. The various routing strategies may be executed in any suitable manner, for example, the various routing strategies may be executed in parallel, which is beneficial to shortening the running time and trying as many routing strategies as possible, and the routing results obtained under the routing strategies respectively need to be subjected to timing analysis to determine whether the routing results meet the timing constraint requirements. For this reason, the optimal timing analysis result is further selected from the timing analysis results meeting the timing constraint requirements, so that the corresponding first layout and wiring policy and the corresponding first design kit can be determined. Therefore, different layout and wiring strategies can be tried, a plurality of corresponding design suites can be automatically mobilized through a first command, and finally the optimal time sequence analysis result and the first design suite are selected, so that the obtained first design suite not only reflects the optimization and adjustment of the comprehensive operation process, but also meets the time sequence constraint requirement. In addition, the front-end design link needs to perform simulation verification and code iteration frequently, and feedback of the back-end simulation design link may also cause code iteration, so new codes need to be imported frequently, which all increase the operation complexity and difficulty of the comprehensive node 107. To this end, in step S214, for a second logic design code associated with the first chip design, the first design suite is selectively mobilized to perform a synthesis operation on the second logic design code based on differences between the first logic design code and the second logic design code. Therefore, when the difference between the first logic design code and the second logic design code is smaller, the first design suite and the corresponding layout and wiring strategies can be mobilized to comprehensively operate the second logic design code, so that various layout and wiring strategies do not need to be tried aiming at the second logic design code, and the layout and wiring results obtained by comprehensively operating the second logic design code by using the first design suite can also meet the requirement of time sequence constraint and have lower risk. In the process of chip design engineering, a large number of code iterations may involve only simpler changes, so that under the condition that the code amount changes are small in two times of running engineering, a first design suite and a corresponding first layout and wiring strategy which are obtained for a first logic design code can be run, and thus, the resource occupation can be further reduced and the overall efficiency can be improved. In general, by comparing the respective amounts of engineering code of the first logical design code and the second logical design code, when the amount of engineering code that is altered is small or occupies a small amount, the difference between the two can be considered small. In addition, when the difference between the first logic design code and the second logic design code relates to a modification of the architecture level, such as a modification of the top-level architecture of the chip, or relates to a modification of macro-level factors, such as the data transmission rate, etc., such similar modification may have a large influence on the time analysis result, so that it may be necessary to perform comprehensive operations under multiple layout and routing policies again on the second logic design code and select a new layout and routing policy and corresponding design suite that better meet the requirements of the second logic design code.
Thus, the method for automating chip design engineering shown in fig. 2 needs to consider, on the one hand, the requirements of the front-end circuit logic design, including frequent code iterations and a large number of simulation verifications, and on the other hand, the verification requirements of the back-end physical layout files, including compliance with the relevant rules of the manufacturing process, such as compliance with the constraints of wiring specifications and transistor density, and also consider the problems of inefficiency and error-prone caused by manually operating the development tools. To this end, the method for automating chip design engineering shown in fig. 2, on the one hand, optimizes and adjusts the comprehensive operation process of the first logic design code through various layout and wiring strategies, and selects one or more timing analysis results conforming to the timing constraint requirements based on the timing constraint requirements associated with the first chip design; on the other hand, an optimal time sequence analysis result is selected from the one or more time sequence analysis results, and then a first design kit corresponding to the optimal time sequence analysis result is determined. Therefore, different layout and wiring strategies can be tried, a plurality of corresponding design suites can be automatically mobilized through a first command, and finally the optimal time sequence analysis result and the first design suite are selected, so that the obtained first design suite not only reflects the optimization and adjustment of the comprehensive operation process, but also meets the time sequence constraint requirement. When the difference between the first logic design code and the second logic design code is smaller, the first design suite and the corresponding layout and wiring strategies can be mobilized to comprehensively operate the second logic design code, so that various layout and wiring strategies do not need to be tried aiming at the second logic design code, and a layout and wiring result obtained by comprehensively operating the second logic design code by using the first design suite can also meet the requirement of time sequence constraint and has lower risk. Therefore, the requirements of the front-end circuit logic design and the verification requirements of the rear-end physical layout file are considered, and the front-end circuit logic design and the verification requirements of the rear-end physical layout file can be conveniently integrated into various development tools so as to improve the degree of automation of comprehensive operation, improve the overall efficiency and reduce the error probability.
In one possible implementation, the first command is parsed to determine a first policy run, and the plurality of design suites of the development tool are mobilized based on the first policy run. In some embodiments, the first policy run includes mobilizing, in parallel, at least one of the plurality of design suites corresponding to at least one of the plurality of place and route policies. In some embodiments, the first policy run further includes a code update configuration based on which the first logic design code is selectively updated in invoking the plurality of design suites of the development tool. In some embodiments, the first policy run further includes a computing cluster commit policy based on which to commit the plurality of place and route policies to respective computing clusters to mobilize the plurality of design suites of the development tool. In this way, the code can be updated and configured, and the customized configuration can be performed for the execution of each layout and wiring strategy, for example, the first strategy operation mode with the maximum parallelism can be adopted according to the available computing power resources, so that the overall time consumption is shortened. In addition, an appropriate computing cluster submitting strategy can be selected according to the situation of the computing clusters, and each layout and wiring strategy can be automatically submitted to different high-performance computing cluster servers with sufficient running memory space, so that the servers for running comprehensive engineering do not need to be selected manually, and the time for waiting to run due to insufficient memory can be saved.
In one possible implementation, each of the plurality of timing analysis results includes a logic gate setup time and a logic gate hold time for a place-and-route result of the plurality of place-and-route results corresponding to the timing analysis result. In some embodiments, the timing constraint requirements include a maximum logic gate setup time and a minimum logic gate hold time. In some embodiments, the optimal timing analysis result is a least risk result. In some application scenarios, such as data centers, device interconnection, etc., there are high requirements on data transmission rate, response time, bit error rate, etc., and these are reflected in the chip design to have corresponding requirements on setup time and hold time between logic gates inside the chip, and other timing analysis characteristics, etc. For this reason, it is necessary to consider the complex situations of the chip in actual production and actual application, such as the change of process corner conditions in the manufacturing process, the influence of operating voltage, external temperature, etc., that is, consider the possibility that the chip can still work normally in extreme cases, and select the optimal time sequence analysis result corresponding to the first logic design code from the one or more time sequence analysis results under these considerations, thereby having good system stability and lower error risk. The timing constraint requirements include, among other things, a maximum logic gate setup time and a minimum logic gate hold time. This helps ensure the correctness of the sequential logic. By selecting the lowest risk result as the optimal timing analysis result, the accuracy of the timing logic in various extreme cases can be ensured.
In one possible implementation, the first design suite is mobilized to perform a comprehensive operation on the second logic design code when a difference between the first logic design code and the second logic design code is less than a preset threshold. In the process of chip design engineering, a large number of code iterations may involve only simpler changes, so that under the condition that the code amount changes are small in two times of running engineering, a first design suite and a corresponding first layout and wiring strategy which are obtained for a first logic design code can be run, and thus, the resource occupation can be further reduced and the overall efficiency can be improved. In general, by comparing the respective amounts of engineering code of the first logical design code and the second logical design code, when the amount of engineering code that is altered is small or occupies a small amount, the difference between the two can be considered small. The preset threshold may be set to a certain number or a certain proportion of engineering code amounts, which means that the altered engineering code amounts are smaller than the preset number or the preset proportion when the difference between the first logic design code and the second logic design code is smaller than the preset threshold, so that the first design suite may be mobilized to perform the integrated operation on the second logic design code. Therefore, various layout and wiring strategies do not need to be tried aiming at the second logic design code, and the layout and wiring result obtained by comprehensively operating the second logic design code by utilizing the first design suite can also meet the time sequence constraint requirement and has lower risk, so that the degree of automation and the overall efficiency are improved.
In one possible implementation, when the difference between the first logic design code and the second logic design code exceeds the preset threshold, the plurality of design suites of the development tool are mobilized, comprehensive operation and timing analysis are respectively performed on the second logic design code, and a second design suite of the plurality of design suites corresponding to an optimal timing analysis result corresponding to the second logic design code is determined. When the difference exceeds a preset threshold, for example, the amount of modified engineering code exceeds a preset amount or a preset ratio, and when, for example, the difference between the first logic design code and the second logic design code relates to a modification on the architecture level, such as a modification on the top-level architecture of the chip, or relates to a modification on a macro-level factor, such as a data transmission rate, etc., such that similar modification may have a great influence on the time analysis result, it may be necessary to perform comprehensive operations under various layout and wiring strategies again on the second logic design code and select a new layout and wiring strategy and corresponding design suite that better meet the requirements of the second logic design code.
In one possible implementation, the first logic design code is a register transfer level code. The first logic design code may be a register transfer level code under any suitable development tool as long as it is available to convert a circuit design scheme into a logic design code.
In one possible implementation, the plurality of placement and routing strategies includes one or more of: the layout and wiring strategy with the shortest running time, the layout and wiring strategy with the optimal area and the layout and wiring strategy with the shortest wiring delay. The plurality of place and route strategies may include any suitable and any number of place and route strategies for optimizing and adjusting the process of transcoding a logic design to a gate level netlist and then placing and routing to a final logic executable. The plurality of types of layout and wiring strategies may include a plurality of types of layout and wiring strategies that achieve the same optimization objective according to different specifications, and for example, the area optimization or the wiring delay minimization may be achieved according to different specifications.
In one possible implementation, the plurality of placement and routing strategies each conform to a layout design requirement associated with the first chip design, the layout design requirement including a routing specification and a transistor density. The various layout and wiring strategies are used for optimizing and adjusting the process of converting the logic design codes into the gate-level circuit netlist and then carrying out layout and wiring to obtain the final logic executable file. On the one hand, the requirements of the circuit logic design of the front end, including frequent code iteration and a large amount of simulation verification, and on the other hand, the requirements of the verification of the physical layout file of the back end, including compliance with the relevant rules of the manufacturing process, such as compliance with the constraints of wiring specifications, transistor density and the like, are considered. Therefore, by limiting the layout and wiring strategies to meet the layout design requirements associated with the first chip design, consistency between the front end and the rear end is maintained, and the overall efficiency of chip design engineering is improved.
In one possible implementation, the first chip is designed for use in a data center, internet of vehicles, high performance computing, communications, aviation, or consumer electronics. Through different layout and wiring strategies, namely in the process of performing comprehensive operation, namely in the process of converting logic design codes into a gate-level circuit netlist and performing layout and wiring to finally obtain a logic executable file, the logic executable file can be optimized and adjusted, so that the requirements of application scenes can be better adapted, for example, the requirements of industries or communication protocols where the logic design codes are located on time sequence operation can be met, and the requirements of specific application scenes such as the fields of data centers, internet of vehicles, high-performance computing, communication, aviation, consumer electronics and the like can be better adapted. The development tool provides different design suites, and the existing development tool can be conveniently adapted to realize automation operation by analyzing the first command to determine a plurality of layout wiring strategies and determining a plurality of design suites corresponding to the plurality of layout wiring strategies one by one.
In one possible implementation, the first chip design is a field programmable gate array chip, the development tool is a field programmable gate array development tool, and the first command is based on a tool command language. In this way, it can be conveniently integrated into various development tools in order to promote the degree of automation of the integrated operations.
Fig. 3 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 300 includes: one or more processors 310, a communication interface 320, and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected by a bus 340. Optionally, the computing device 300 may further include an input/output interface 350, where the input/output interface 350 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 310 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 300 performing various operations may refer to specific details in the above-described embodiments, such as the processor 310 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the embodiment of the present application, the computing device 300 may be used to implement some or all of the functions of one or more components in the apparatus embodiments described above, and the communication interface 320 may be used in particular for communication functions and the like necessary for implementing the functions of these apparatuses, components, and the processor 310 may be used in particular for processing functions and the like necessary for implementing the functions of these apparatuses, components.
It should be appreciated that the computing device 300 of fig. 3 may include one or more processors 310, and that the plurality of processors 310 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or the plurality of processors 310 may constitute a processor sequence or processor array, or the plurality of processors 310 may be separated into primary and secondary processors, or the plurality of processors 310 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 300 shown in FIG. 3, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 300 may include more or fewer components than shown in fig. 3, or combine certain components, or split certain components, or have a different arrangement of components.
Processor 310 may take many specific forms, for example, processor 310 may include one or more combinations of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and embodiments of the present application are not limited in detail. Processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be formed by a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 310 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 320 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.
The memory 330 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 330 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 330 may also be used to store program code and data such that processor 310 invokes the program code stored in memory 330 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 300 may contain more or fewer components than shown in FIG. 3, or may have a different configuration of components.
Bus 340 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 340 may be divided into an address bus, a data bus, a control bus, and the like. The bus 340 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 3 for clarity of illustration, but does not represent only one bus or one type of bus.
The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.
Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.
Claims (16)
1. A method for chip design engineering automation, the method comprising:
obtaining a first logic design code associated with a first chip design and a first command;
parsing the first command to determine a plurality of place and route policies and to determine a plurality of design suites of a development tool that are in one-to-one correspondence with the plurality of place and route policies;
the plurality of design kits of the development tool are mobilized, and the first logic design codes are respectively and comprehensively operated to obtain a plurality of layout and wiring results which are in one-to-one correspondence with the plurality of layout and wiring strategies;
Respectively carrying out time sequence analysis on the plurality of layout wiring results to obtain a plurality of time sequence analysis results which are in one-to-one correspondence with the plurality of layout wiring results;
selecting one or more timing analysis results from the plurality of timing analysis results that meet the timing constraint requirements based on the timing constraint requirements associated with the first chip design;
selecting an optimal timing analysis result corresponding to the first logic design code from the one or more timing analysis results, wherein the optimal timing analysis result corresponds to a first place and route result of the plurality of place and route results, the first place and route result corresponds to a first place and route policy of the plurality of place and route policies, the first place and route policy corresponds to a first design suite of the plurality of design suites;
the first design suite is selectively mobilized to perform a synthesis operation on a second logic design code associated with the first chip design based on differences between the first logic design code and the second logic design code.
2. The method according to claim 1, wherein the method further comprises: parsing the first command to determine a first policy run, invoking the plurality of design suites of the development tool based on the first policy run.
3. The method of claim 2, wherein the first policy run comprises invoking at least one of the plurality of design suites corresponding to at least one of the plurality of place and route policies in parallel.
4. The method of claim 3, wherein the first policy run further comprises a code update configuration based on which the first logical design code is selectively updated in invoking the plurality of design suites of the development tool.
5. The method of claim 4, wherein the first policy run further comprises a computing cluster commit policy based on which to commit the plurality of place and route policies to the respective computing clusters to mobilize the plurality of design suites of the development tool.
6. The method of claim 1, wherein each of the plurality of timing analysis results comprises a logic gate setup time and a logic gate hold time for a place and route result of the plurality of place and route results corresponding to the timing analysis result.
7. The method of claim 6, wherein the timing constraint requirements include a maximum logic gate setup time and a minimum logic gate hold time.
8. The method of claim 7, wherein the optimal timing analysis result is a risk-minimized result.
9. The method of claim 1, wherein the first design suite is mobilized to perform a synthesis operation on the second logic design code when a difference between the first logic design code and the second logic design code is less than a preset threshold.
10. The method of claim 1, wherein when a difference between the first logical design code and the second logical design code exceeds a preset threshold, invoking the plurality of design suites of the development tool, performing a comprehensive operation and a timing analysis on the second logical design code, respectively, and determining a second design suite of the plurality of design suites corresponding to an optimal timing analysis result corresponding to the second logical design code.
11. The method of claim 1, wherein the first logic design code is a register transfer level code.
12. The method of claim 1, wherein the plurality of place and route strategies includes one or more of: the layout and wiring strategy with the shortest running time, the layout and wiring strategy with the optimal area and the layout and wiring strategy with the shortest wiring delay.
13. The method of claim 1, wherein the plurality of place-and-route strategies each conform to a layout design requirement associated with the first chip design, the layout design requirement including a route specification and a transistor density.
14. The method of claim 1, wherein the first chip design is a field programmable gate array chip, the development tool is a field programmable gate array development tool, and the first command is based on a tool command language.
15. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 14 when executing the computer program.
16. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 14.
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