CN118073403A - Super junction device terminal structure - Google Patents
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- CN118073403A CN118073403A CN202410466824.1A CN202410466824A CN118073403A CN 118073403 A CN118073403 A CN 118073403A CN 202410466824 A CN202410466824 A CN 202410466824A CN 118073403 A CN118073403 A CN 118073403A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 123
- 210000005056 cell body Anatomy 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 29
- 230000015556 catabolic process Effects 0.000 abstract description 12
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- 229910052710 silicon Inorganic materials 0.000 abstract description 6
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- 238000010586 diagram Methods 0.000 description 10
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- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- 230000002787 reinforcement Effects 0.000 description 1
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Abstract
The invention relates to the technical field of superjunction devices, in particular to a terminal structure of a superjunction device, wherein an etching area on the upper layers of an n-type semiconductor column and a p-type semiconductor column is provided with a p-type cell body region extension well and an insulating medium layer which are adjacent to each other, and the p-type cell body region extension well and the insulating medium layer respectively cross at least one n-type semiconductor column and one p-type semiconductor column. According to the invention, the insulating dielectric layer is introduced, and the second metal electrode extends to the insulating dielectric layer, so that a composite terminal structure of the field plate and the dielectric slot terminal is formed; the insulating dielectric layer has a higher breakdown electric field than the silicon layer, and the second metal electrode extending to the insulating dielectric layer provides a high electric field for the terminal region, so that when breakdown occurs, the super junction device terminal structure has a higher surface electric field peak value and smoother electric field distribution; and under the same pressure resistance, the terminal structure of the super junction device occupies smaller chip area, which is beneficial to reducing the manufacturing cost of the chip.
Description
Technical Field
The invention relates to the technical field of superjunction devices, in particular to a terminal structure of a superjunction device.
Background
In recent years, with the development of new energy automobiles and other emerging industries, the demand for high-power, high-voltage-withstanding and high-reliability power devices has increased dramatically. The super junction device is used as one of typical representatives of the power device, has the advantages of high voltage resistance, low on-resistance and the like, and can meet the requirements of a power electronic system on miniaturization and high efficiency of the power electronic device. The superjunction device has two areas, namely a cell and a terminal, the cell bears the main function of the superjunction device, and the edge area of the cell has curvature effect, which easily leads to the reduction of the withstand voltage of the device, so that the terminal area is required to play a role in reinforcement. The current common terminal forming process is to extend the P/N columns alternately formed in the cell region to the terminal region, and reduce the influence of curvature effect of the cell edge region by increasing the terminal length, so that the device withstand voltage is improved. The terminal has a simple structure, occupies a large amount of chip area, and increases the chip manufacturing cost.
In order to save the cost of the chip, various junction terminal technologies such as a field plate, a field limiting ring, a cut-off terminal and the like are proposed, the electric field distribution of a terminal area is improved, and the terminal area is optimized. For example, the field plate technology covers the medium and the electrode on the surface of the curved junction at the edge of the cell to form a field plate structure, so that the electric field lines at the curved junction are turned to the field plate, and the terminal electric field distribution is effectively optimized. However, the electrode edges of the field plates can generate extremely high potential differences, and the requirements on the medium are high, so that an upper limit for pressure resistance optimization exists. The truncated termination technology enables the cell edge to be terminated in the dielectric groove, so that the termination area is greatly reduced, however, the termination technology needs deep groove etching and dielectric filling on the silicon layer, and has high process requirements.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a terminal structure of a superjunction device, which aims to solve the problem of poor voltage resistance of the existing superjunction device.
The technical scheme of the invention is as follows:
A super junction device termination structure, comprising a first metal electrode, an n-type semiconductor substrate on the first metal electrode; the n-type semiconductor substrate is provided with an n-type semiconductor drift region, a plurality of p-type semiconductor columns are arranged at intervals in the left end etching region of the n-type semiconductor drift region, columns between adjacent p-type semiconductor columns are defined as n-type semiconductor columns, and the n-type semiconductor columns and the p-type semiconductor columns are alternately arranged; the etching areas of the upper layers of the n-type semiconductor columns and the p-type semiconductor columns are provided with adjacent p-type cell body region extension wells and insulating medium layers, and the p-type cell body region extension wells and the insulating medium layers respectively at least cross one n-type semiconductor column and one p-type semiconductor column; the p-type cell body region extension well and the insulating medium layer are provided with a second metal electrode; an n-type semiconductor well region is arranged in the right end etching region of the n-type semiconductor drift region, and a third metal electrode is arranged on the n-type semiconductor well region.
The super junction device terminal structure is characterized in that the etching depth of the insulating medium layer is larger than the depth of the p-type cell body region extension well.
The super junction device terminal structure is characterized in that the insulating dielectric layer is made of silicon dioxide or silicon nitride.
The super junction device terminal structure, wherein the donor impurity doping concentration of the n-type semiconductor substrate is greater than that of the n-type semiconductor drift region.
The super junction device terminal structure comprises an n-type semiconductor well region, a super junction device terminal structure and a semiconductor drift region, wherein the donor impurity doping concentration of the n-type semiconductor well region is larger than that of the n-type semiconductor drift region.
The super junction device terminal structure comprises a p-type cell body region extension well, wherein the acceptor impurity doping concentration of the p-type cell body region extension well is larger than that of the p-type semiconductor column.
The super junction device terminal structure comprises an insulating dielectric layer, a p-type cell body region extending well, a p-type semiconductor column and a p-type semiconductor column, wherein the number of the insulating dielectric layer crossing the n-type semiconductor column and the p-type semiconductor column is larger than that of the p-type cell body region extending well crossing the n-type semiconductor column and the p-type semiconductor column.
The super junction device terminal structure comprises a p-type cell body region extension well and an insulating medium layer, wherein the p-type cell body region extension well and the insulating medium layer cross all n-type semiconductor columns and p-type semiconductor columns.
The beneficial effects are that: compared with the traditional terminal structure, the invention has the key innovation that an insulating medium layer is introduced on the surface of the terminal, and a second metal electrode (source electrode) is extended to the insulating medium layer to form a composite terminal structure of the field plate and the medium slot terminal; compared with a silicon layer, the insulating dielectric layer introduced by the composite terminal structure has a higher breakdown electric field, and the source electrode extending to the insulating dielectric layer provides a high electric field for the terminal area, so that the super junction device terminal structure provided by the invention has higher surface electric field peak value and smoother electric field distribution when breakdown occurs; compared with the traditional terminal structure, the super junction device terminal structure provided by the invention has the advantage that the withstand voltage is obviously improved; and under the same pressure resistance, the super junction device terminal structure provided by the invention occupies smaller chip area, and is beneficial to reducing the chip manufacturing cost.
Drawings
Fig. 1 is a cross-sectional view of a termination structure of a superjunction device according to the present invention.
Fig. 2 is a perspective view of a termination structure of a superjunction device according to the present invention.
Fig. 3 is a cross-sectional view of a termination structure of other alternative superjunction devices of the present invention.
Fig. 4 is a doping concentration distribution diagram obtained by performing process simulation on the super junction device terminal structure provided in embodiment 1 of the present invention in Sentaurus TCAD.
Fig. 5 is a cross-sectional view of a conventional device termination structure provided in comparative example 1.
Fig. 6 is a doping concentration profile obtained by performing a process simulation in Sentaurus TCAD of the conventional device termination structure provided in comparative example 1.
Fig. 7 is a surface electric field distribution diagram of the super junction device according to embodiment 1 of the present invention when the terminal structure breaks down.
Fig. 8 is a surface electric field distribution diagram of the conventional device provided in comparative example 1 at the time of breakdown of the termination structure.
Fig. 9 is a diagram showing a drain-source voltage-current relationship when the terminal structure of the superjunction device provided in embodiment 1 of the present invention is tested for withstand voltage.
Fig. 10 is a graph showing a drain-source voltage-current relationship when a conventional device terminal structure provided in comparative example 1 is tested for withstand voltage.
Detailed Description
The invention provides a super junction device terminal structure, which is used for making the purposes, technical schemes and effects of the invention clearer and more definite, and is further described in detail below. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1-2, the present invention provides a superjunction device termination structure, which includes a first metal electrode 7, an n-type semiconductor substrate 6 on the first metal electrode 7; an n-type semiconductor drift region 5 is arranged on the n-type semiconductor substrate 6, a plurality of p-type semiconductor columns 4 are arranged at intervals in the left end etching region of the n-type semiconductor drift region 5, columns between adjacent p-type semiconductor columns 4 are defined as n-type semiconductor columns 51, and the n-type semiconductor columns 51 and the p-type semiconductor columns 4 are alternately arranged; the etching areas of the upper layers of the n-type semiconductor column 51 and the p-type semiconductor column 4 are provided with a p-type cell body region extension well 2 and an insulating medium layer 3 which are adjacent to each other, and the p-type cell body region extension well 2 and the insulating medium layer 3 respectively at least cross one n-type semiconductor column 51 and one p-type semiconductor column 4; the p-type cell body region extension well 2 and the insulating medium layer 3 are provided with a second metal electrode 1; an n-type semiconductor well region 9 is arranged in the right end etching region of the n-type semiconductor drift region 5, and a third metal electrode 8 is arranged on the n-type semiconductor well region 9.
In the invention, first, P-type semiconductor columns 4 and N-type semiconductor columns 51 (i.e. alternating P/N columns) alternately formed in a cell region (i.e. a region covered by a P-type cell body extension well) are extended to a terminal region, then shallow trench etching and insulating medium filling are carried out on a partial region of the terminal region close to the edge of the cell to form an insulating medium layer 3, and meanwhile, a second metal electrode 1 (i.e. a source electrode) is extended from the surface of the P-type cell body extension well 2 to the surface of the insulating medium layer 3, so that a composite terminal structure of a field plate and a medium trench terminal (i.e. a super junction device terminal structure of the invention) is formed; the super junction device terminal structure technology uses the insulating medium to replace the silicon layer on the terminal surface, the optimization of the electric field on the terminal surface is more effective than that of a field plate technology, and meanwhile, the alternating P/N columns and the insulating medium shallow grooves are combined, so that the terminal structure technology is easier than that of a cut-off terminal technology in terms of technological requirements, and the adjustment of the internal electric field is more flexible. Therefore, the technology can effectively improve the withstand voltage, save the manufacturing cost of the chip, and enrich the means of optimizing the withstand voltage of the terminal aiming at different superjunction devices.
Specifically, compared with a silicon layer, the insulating dielectric layer introduced by the super junction device terminal structure has a higher breakdown electric field, and the source electrode extending to the insulating dielectric layer provides a high electric field for the terminal area, so that the super junction device terminal structure provided by the invention has higher surface electric field peak value and smoother electric field distribution when breakdown occurs; compared with the traditional terminal structure, the super junction device terminal structure provided by the invention has the advantage that the withstand voltage is obviously improved; and under the same pressure resistance, the super junction device terminal structure provided by the invention occupies smaller chip area, and is beneficial to reducing the chip manufacturing cost.
In some embodiments, the insulating dielectric layer is etched to a depth greater than a depth of the p-type cell body extension well. In this embodiment, since the electric field extends outward from the P-type cell body region, when the etching depth of the insulating dielectric layer is greater than that of the extension well of the P-type cell body region, the high electric field can be ensured to fall on the insulating dielectric layer which is more resistant to breakdown as much as possible, and the arrangement can improve the withstand voltage.
In some embodiments, the material of the insulating dielectric layer is silicon dioxide or silicon nitride, but is not limited thereto.
In some embodiments, the n-type semiconductor substrate has a donor impurity doping concentration that is greater than a donor impurity doping concentration of the n-type semiconductor drift region. The donor impurity may be, for example, phosphorus or arsenic, etc. In this example, since the substrate is to be connected to the first metal electrode, it must be heavily doped to form an ohmic contact with the first metal electrode, reducing resistance.
In some embodiments, the n-type semiconductor well region has a donor impurity doping concentration greater than a donor impurity doping concentration of the n-type semiconductor drift region.
In some embodiments, the acceptor impurity doping concentration of the p-type cell body region extension well is greater than the acceptor impurity doping concentration of the p-type semiconductor column. By way of example, the acceptor impurity may be boron. In this embodiment, the p-type cell body extension well is also heavily doped because the second metal electrode is connected.
In some embodiments, the number of insulating dielectric layers spanning the n-type semiconductor pillars and the p-type semiconductor pillars is greater than the number of p-type cell body region extension wells spanning the n-type semiconductor pillars and the p-type semiconductor pillars. In this embodiment, since the insulating dielectric layer plays a role of withstand voltage, the longer the insulating dielectric layer is, the more withstand voltage is high, that is, the number of insulating dielectric layers crossing the n-type semiconductor pillars and the p-type semiconductor pillars is large. The p-type cell body region does not take on the function of withstand voltage, and its function is to introduce an electric field from the electrode, so that a large length is not required.
In some embodiments, the number of p-type cell body extension wells and insulating dielectric layers that span across the n-type semiconductor pillars and p-type semiconductor pillars may be designed as desired, as shown by way of example in fig. 3, and the p-type cell body extension wells and insulating dielectric layers may span across all of the n-type semiconductor pillars and p-type semiconductor pillars.
The invention is further illustrated by the following examples:
Example 1
There is provided a superjunction device termination structure as shown in fig. 1, comprising a first metal electrode 7, an n-type semiconductor substrate 6 on said first metal electrode 7; an n-type semiconductor drift region 5 is arranged on the n-type semiconductor substrate 6, a plurality of p-type semiconductor columns 4 are arranged at intervals in the left end etching region of the n-type semiconductor drift region 5, columns between adjacent p-type semiconductor columns 4 are defined as n-type semiconductor columns 51, and the n-type semiconductor columns 51 and the p-type semiconductor columns 4 are alternately arranged; the etching areas of the upper layers of the n-type semiconductor column 51 and the p-type semiconductor column 4 are provided with a p-type cell body region extension well 2 and an insulating medium layer 3 which are adjacent to each other, and the p-type cell body region extension well 2 and the insulating medium layer 3 respectively at least cross one n-type semiconductor column 51 and one p-type semiconductor column 4; the p-type cell body region extension well 2 and the insulating medium layer 3 are provided with a second metal electrode 1; an n-type semiconductor well region 9 is arranged in the right end etching region of the n-type semiconductor drift region 5, and a third metal electrode 8 is arranged on the n-type semiconductor well region 9. In this embodiment, the second metal electrode 1 is used as a source electrode of the super junction device terminal structure, the first metal electrode 7 and the third metal electrode 8 are used as drains of the super junction device terminal structure, the second metal electrode 1 is in direct contact with the insulating medium region 3, when the super junction device terminal structure works in the cut-off region, the drain potential is higher than the source electrode potential, and a high voltage exists between the two electrodes.
Fig. 4 is a doping concentration distribution diagram of the super junction device terminal structure provided in this embodiment obtained by performing a process simulation in Sentaurus TCAD.
Comparative example 1
Comparative example 1 provides a schematic diagram of a conventional termination device structure as shown in fig. 5, which includes a metal electrode 15 and an n-type semiconductor substrate 14 on the metal electrode 15; the n-type semiconductor substrate 14 is provided with an n-type semiconductor drift region 13; the n-type semiconductor drift region 13 has a plurality of p-type semiconductor pillars 12 therein, and the n-type semiconductor drift region 13 and the p-type semiconductor pillars 12 are alternately arranged; the upper layer end of the n-type semiconductor drift region 13 and the p-type semiconductor column 12 is provided with a p-type cell body region extension well 11; the upper layer of the p-type cell body region extension well 11 is provided with a metal electrode 10; one end of the n-type semiconductor drift region 13 is provided with an n-type semiconductor well region 17, and a metal electrode 16 is arranged on the upper layer of the n-type semiconductor well region 17. Fig. 6 is a doping concentration profile of the conventional termination structure obtained by performing a process simulation in Sentaurus TCAD.
Test example 1
The superjunction termination device structures in example 1 and comparative example 1 were held at zero potential for the source electrode and gradually raised to the drain potential, and when the breakdown current reached 0.1mA, the device was considered to reach breakdown conditions. Fig. 7 is a surface electric field distribution diagram of the super junction termination device structure provided in example 1 when breakdown occurs. Fig. 8 is a surface electric field distribution diagram of the conventional termination device structure of comparative example 1 at breakdown. As can be seen from comparing fig. 7 and fig. 8, when the device breaks down, the maximum electric field on the surface of the superjunction termination device structure provided in embodiment 1 of the present invention is higher than that of the conventional termination device structure. In addition, the surface electric field of the superjunction terminal device structure provided in the embodiment 1 is smoother when the device breaks down, and the surface electric field of the traditional terminal device structure is in severe oscillation, so that the surface electric field of the superjunction terminal device structure provided in the embodiment 1 is more reasonably distributed when the device breaks down, and a higher electric field can be introduced into the silicon layer, so that the terminal withstand voltage is effectively improved.
Fig. 9 is a diagram showing the drain-source voltage-current relationship when the super junction termination device structure provided in this embodiment 1 is tested for withstand voltage, fig. 10 is a diagram showing the drain-source voltage-current relationship when the conventional termination device structure provided in comparative example 1 is tested for withstand voltage, and it can be seen from comparison between fig. 9 and fig. 10 that the withstand voltage of the super junction termination device structure provided in this embodiment 1 is improved by at least 20% compared with the withstand voltage of the conventional termination device structure, and the novel super junction termination device structure can provide a larger optimizing space for the withstand voltage of the termination device for different super junction manufacturing processes.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (8)
1. A super junction device terminal structure, which is characterized by comprising a first metal electrode and an n-type semiconductor substrate positioned on the first metal electrode; the n-type semiconductor substrate is provided with an n-type semiconductor drift region, a plurality of p-type semiconductor columns are arranged at intervals in the left end etching region of the n-type semiconductor drift region, columns between adjacent p-type semiconductor columns are defined as n-type semiconductor columns, and the n-type semiconductor columns and the p-type semiconductor columns are alternately arranged; the etching areas of the upper layers of the n-type semiconductor columns and the p-type semiconductor columns are provided with adjacent p-type cell body region extension wells and insulating medium layers, and the p-type cell body region extension wells and the insulating medium layers respectively at least cross one n-type semiconductor column and one p-type semiconductor column; the p-type cell body region extension well and the insulating medium layer are provided with a second metal electrode; an n-type semiconductor well region is arranged in the right end etching region of the n-type semiconductor drift region, and a third metal electrode is arranged on the n-type semiconductor well region.
2. The superjunction device termination structure of claim 1, wherein the insulating dielectric layer has an etch depth greater than a depth of the p-type cell body region extension well.
3. The superjunction device termination structure of claim 1, wherein the insulating dielectric layer is of silicon dioxide or silicon nitride.
4. The superjunction device termination structure of claim 1, wherein the n-type semiconductor substrate has a donor impurity doping concentration greater than a donor impurity doping concentration of the n-type semiconductor drift region.
5. The superjunction device termination structure of claim 1, wherein the n-type semiconductor well region has a donor impurity doping concentration greater than a donor impurity doping concentration of the n-type semiconductor drift region.
6. The superjunction device termination structure of claim 1, wherein the acceptor impurity doping concentration of the p-type cell body region extension well is greater than the acceptor impurity doping concentration of the p-type semiconductor column.
7. The superjunction device termination structure of claim 1, wherein the number of insulating dielectric layers spanning n-type semiconductor pillars and p-type semiconductor pillars is greater than the number of p-type cell body region extension wells spanning n-type semiconductor pillars and p-type semiconductor pillars.
8. The superjunction device termination structure of claim 1, wherein the p-type cell body extension well and insulating dielectric layer spans all of the n-type semiconductor pillars and the p-type semiconductor pillars.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007116190A (en) * | 2006-12-12 | 2007-05-10 | Toshiba Corp | Semiconductor element and its manufacturing method |
| CN108054195A (en) * | 2017-12-08 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Semiconductor power device and preparation method thereof |
| CN110993557A (en) * | 2018-10-02 | 2020-04-10 | 英飞凌科技奥地利有限公司 | Method for forming an insulating layer in a semiconductor body and transistor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007116190A (en) * | 2006-12-12 | 2007-05-10 | Toshiba Corp | Semiconductor element and its manufacturing method |
| CN108054195A (en) * | 2017-12-08 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Semiconductor power device and preparation method thereof |
| CN110993557A (en) * | 2018-10-02 | 2020-04-10 | 英飞凌科技奥地利有限公司 | Method for forming an insulating layer in a semiconductor body and transistor device |
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