CN117980993A

CN117980993A - Ferroelectric memory, data reading method and electronic device

Info

Publication number: CN117980993A
Application number: CN202180101882.9A
Authority: CN
Inventors: 张敏; 张恒; 杨喜超; 吕杭炳; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2024-05-03
Also published as: WO2023097528A1

Abstract

The embodiment of the application provides a ferroelectric memory, a data reading method and electronic equipment, which can amplify a reading voltage window of the ferroelectric memory, wherein the ferroelectric memory comprises one or more memory cell subarrays, and each memory cell subarray comprises ferroelectric memory cells distributed in an array manner; in the memory cell subarray, ferroelectric memory cells positioned in the same column are connected with the same local bit line, and ferroelectric memory cells positioned in the same row are connected with the same word line; ferroelectric memory cells in the same row are also connected to the same plate line; a row of gain units are also arranged in the memory unit subarray, and a gain unit is correspondingly arranged in the ferroelectric memory units positioned in the same column; the gain unit comprises an amplifying transistor, wherein the control end of the amplifying transistor is connected with a local bit line connected with the column of ferroelectric memory cells, the first end of the amplifying transistor is connected with a global bit line, and the second end of the amplifying transistor is connected with a source line.

Description

Ferroelectric memory, data reading method and electronic device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a ferroelectric memory, a data reading method, and an electronic device.

Background

A ferroelectric random access memory (ferroelectric random access memory, feRAM), which may also be referred to as a "ferroelectric memory", which performs data storage by utilizing the characteristic that a ferroelectric material can undergo spontaneous polarization and the polarization intensity can be reoriented with the action of an external electric field; when the electric field is removed, part of the polarization state can be maintained, the polarization intensity is called remnant polarization, and the electric field in the same direction is applied by utilizing the difference of the remnant polarization direction, and the flip charges are different, so that the data "0" and "1" can be stored.

The memory structure of the ferroelectric memory mainly comprises a single tube single capacitor (1transistor 1 capacitor,1T1C), a double tube double capacitor (2transistor 2 capacitor,2T1C), a double tube single capacitor (2transistor 1 capacitor,2T1C) and the like. Each memory cell of the 1T1C memory structure comprises 1transistor and 1 ferroelectric material capacitor, the structure is simple, the memory density is high, but in order to ensure the good miniature characteristic of the memory, the size of the ferroelectric material capacitor is smaller, the charge stored in the ferroelectric material capacitor is smaller, and the turnover charge generated when an electric field is applied is smaller, so that the ferroelectric memory of the 1T1C memory structure has the problem of smaller read voltage window.

Disclosure of Invention

The application provides a ferroelectric memory, a data reading method and electronic equipment, which can solve the problems of small reading voltage window and the like of the existing ferroelectric memory structure.

In a first aspect, a ferroelectric memory is provided, the ferroelectric memory comprising one or more subarrays of ferroelectric memory cells, each subarray of ferroelectric memory cells comprising a row of gain cells and an array of distributed ferroelectric memory cells; wherein, the ferroelectric memory cells in the same column are electrically connected with the same local bit line, and the ferroelectric memory cells in the same row are electrically connected with the same word line; ferroelectric memory cells in the same row are also electrically connected to the same plate line; a gain unit is correspondingly arranged on ferroelectric memory units positioned in the same column; the gain unit includes an amplifying transistor; the control end of the amplifying transistor is connected with the local bit line connected with the column of ferroelectric memory cells, the first end of the amplifying transistor is connected with the global bit line, and the second end of the amplifying transistor is connected with the source line. When reading data, different voltages are preset on the source line and the global bit line, the overturn charges generated by the ferroelectric memory unit can be accumulated and converted on the local bit line to form local bit line voltage, the amplifying transistor can be turned on or off under the action of the local bit line voltage, when the amplifying transistor is turned on or off, different reading voltages can be read on the global bit line, namely, the line voltage of the global bit line or the line voltage of the source line, and the voltage window formed by the line voltage of the global bit line or the line voltage of the source line is larger than the voltage window formed by the overturn charges of the ferroelectric memory unit on the local bit line, and when reading data, the overturn charges on the ferroelectric memory unit are amplified on the local bit line to form the reading voltage window on the global bit line, so that the amplification of the reading window is realized.

In one possible implementation, the gain unit further includes a first transistor, a control terminal of the first transistor is electrically connected to the first control line, a first terminal of the first transistor is electrically connected to the write bit line, and a second terminal of the first transistor is electrically connected to the local bit line to which the control terminal of the amplifying transistor is connected. The first transistor is connected with a write bit line and a local bit line connected with a control end of the amplifying transistor respectively, and can charge the local bit line during writing and precharge the control end of the amplifying transistor during reading data.

In one possible implementation, the gain unit further includes a second transistor, a control terminal of the second transistor being connected to the second control line, a first terminal of the second transistor being connected to the write bit line, and a second terminal of the second transistor being connected to the global bit line. The second transistors are respectively connected with a write bit line and a global bit line connected with the first end of the amplifying transistor, and the first end of the amplifying transistor can be precharged when data is read.

In one possible implementation, in the memory cell sub-array, the control terminals of the first transistors of the gain cells located in the same row are connected to the same first control line; the control ends of the second transistors of the gain units positioned in the same row are connected with the same second control line, and the gain units in the same memory unit subarray share the first control line and the second control line, so that the integration level can be improved, and the area of the ferroelectric memory can be reduced.

In one possible implementation, the ferroelectric memory includes a plurality of memory cell sub-arrays in which first ends of amplifying transistors of gain cells located in the same column are electrically connected to the same global bit line, and second ends of amplifying transistors of gain cells located in the same column are connected to the same source line; the first ends of the first transistors of the gain units positioned in the same column are connected with the same writing bit line; the first ends of the second transistors of the gain units positioned in the same column are connected with the same writing bit line; the second ends of the second transistors of the gain units in the same column are connected with the same global bit line, and the source line, the global bit line and the write bit line can be shared by a plurality of memory unit subarrays, so that the integration level can be improved, and the area of the ferroelectric memory can be reduced.

In one possible implementation, the gain unit further includes a first transistor, a control terminal of the first transistor is electrically connected to the first control line, a first terminal of the first transistor is electrically connected to a global bit line connected to the first terminal of the amplifying transistor, and a second terminal of the first transistor is electrically connected to a local bit line connected to the control terminal of the amplifying transistor.

In one possible implementation, in the memory cell sub-array, the control terminals of the first transistors of the gain cells located in the same row are connected to the same first control line.

In one possible implementation, a ferroelectric memory includes a plurality of memory cell sub-arrays; in the multiple memory cell subarrays, the first ends of the amplifying transistors of the gain cells positioned in the same column are connected with the same global bit line, and the second ends of the amplifying transistors of the gain cells positioned in the same column are connected with the same source line; the first ends of the first transistors of the gain cells located in the same column are connected to the same global bit line.

In one possible implementation, the ferroelectric memory cell includes an access transistor and a ferroelectric capacitor, a control terminal of the access transistor being electrically connected to the word line; the first end of the access transistor is electrically connected with the local bit line, the second end of the access transistor is electrically connected with the first polar plate of the ferroelectric capacitor, and the second polar plate of the ferroelectric capacitor is electrically connected with the plate line. The ferroelectric capacitor is used for storing data, the difference of voltage differences between the first polar plate and the second polar plate represents different data, the access transistor is respectively connected with the local bit line and the first polar plate of the ferroelectric capacitor, and when the access transistor is conducted, the data can be written into the ferroelectric capacitor or the data stored in the ferroelectric capacitor can be read.

In a second aspect, there is provided a data reading method of the ferroelectric memory as in the first aspect, the method comprising: pre-charging a first end of the amplifying transistor to a first level different from a source line voltage, wherein the source line voltage is a second level; applying an actuation voltage to the target ferroelectric memory cell; the data stored in the read target ferroelectric memory cell is determined according to the read voltage on the global bit line.

In one possible implementation, before determining the data stored by the read target ferroelectric memory cell according to the read voltage on the global bit line, the method further comprises: the control end of the amplifying transistor is pre-charged to the third level, and when the control end of the amplifying transistor is at the third level, the amplifying transistor is in an off state.

In one possible implementation, the gain unit includes a first transistor, a control terminal of the first transistor is connected to the first control line, a first terminal of the first transistor is connected to the write bit line, a second terminal of the first transistor is connected to a local bit line to which a control terminal of the amplifying transistor is connected, and precharging the control terminal of the amplifying transistor to the third level includes: the first transistor is controlled to be turned on, a third level is output to the write bit line, and the control end of the amplifying transistor is precharged to the third level.

In one possible implementation, the gain unit further includes a second transistor, a control terminal of the second transistor is connected to the first control line, a first terminal of the second transistor is connected to the write bit line, a second terminal of the second transistor is connected to a global bit line to which a first terminal of the amplifying transistor is connected, and precharging the first terminal of the amplifying transistor to a first level different from a first source line voltage includes: the second transistor is controlled to be turned on, and a first level different from the source line voltage is output to the write bit line.

In one possible implementation, the gain unit includes a first transistor, a control terminal of the first transistor is connected to a first control line, a first terminal of the first transistor is connected to a global bit line connected to a first terminal of the amplifying transistor, a second terminal of the first transistor is connected to a local bit line connected to a control terminal of the amplifying transistor, and precharging the control terminal of the amplifying transistor to a third level includes: the first transistor is controlled to be turned on, and a third level is output to the global bit line.

In one possible implementation, pre-charging the first terminal of the amplifying transistor to a first level different from the source line voltage includes: the first level is output to the global bit line, and the first terminal of the amplifying transistor is precharged to a first level different from the source line voltage.

In one possible implementation, determining the data stored by the read target ferroelectric memory cell according to the read voltage on the global bit line includes: when the read voltage is at the second level, determining that the data stored in the read target ferroelectric memory cell is at the first logic value; and when the read voltage is a fourth level, determining that the data stored in the read target ferroelectric memory cell is a second logic value, wherein the fourth level is a difference value between the first level and the leakage quantity of the amplifying transistor in the off state.

In one possible implementation, if it is determined that the logic value stored in the read target ferroelectric memory cell is the first logic value, the method further includes: the first logic value is written back to the target ferroelectric memory cell.

In one possible implementation, the ferroelectric memory cell includes an access transistor and a ferroelectric capacitor, a control terminal of the access transistor is electrically connected to the word line, a first terminal of the access transistor is electrically connected to the local bit line, a second terminal of the access transistor is electrically connected to a first plate of the ferroelectric capacitor, a second plate of the ferroelectric capacitor is electrically connected to the plate line, the gain cell includes a first transistor, a control terminal of the first transistor is connected to the first control line, a first terminal of the first transistor is connected to the write bit line, a second terminal of the first transistor is connected to the local bit line, and writing back a first logic value to the target ferroelectric memory cell includes: controlling the access transistor of the target ferroelectric memory cell to be turned on; controlling the first transistor to be conducted, and outputting a high-level signal to a write bit line corresponding to the target ferroelectric memory cell; outputting a low level signal to a plate line connected to the target ferroelectric memory cell; and outputting a low-level signal to a write bit line except the write bit line corresponding to the target ferroelectric memory cell in the memory cell subarray.

In one possible implementation, the ferroelectric memory cell includes an access transistor and a ferroelectric capacitor, a control terminal of the access transistor is electrically connected to the word line, a first terminal of the access transistor is electrically connected to the local bit line, a second terminal of the access transistor is electrically connected to a first plate of the ferroelectric capacitor, a second plate of the ferroelectric capacitor is electrically connected to the plate line, the gain cell includes a first transistor, a control terminal of the first transistor is connected to the first control line, a first terminal of the first transistor is connected to the global bit line, a second terminal of the first transistor is connected to the local bit line, and writing back a first logic value to the target ferroelectric memory cell includes: controlling the access transistor of the target ferroelectric memory cell to be turned on; controlling the first transistor to be conducted, and outputting a high-level signal to a global bit line corresponding to the target ferroelectric memory cell; outputting a low level signal to a plate line connected to the target ferroelectric memory cell; and outputting a low-level signal to a global bit line except the global bit line corresponding to the target ferroelectric memory cell in the memory cell subarray.

In a third aspect, there is provided an electronic device comprising a circuit board and a ferroelectric memory electrically connected to the circuit board, wherein the ferroelectric memory is a ferroelectric memory as provided in the first aspect.

Drawings

Fig. 1 is a schematic system architecture of an electronic device according to an embodiment of the present application;

fig. 2 is a schematic diagram of a ferroelectric hysteresis loop according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present application;

Fig. 4 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present application;

Fig. 6 is a schematic structural diagram of a ferroelectric memory according to another embodiment of the present application;

FIG. 7 is a schematic diagram of a memory cell sub-array according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a memory cell sub-array according to another embodiment of the present application;

FIG. 9a is a schematic diagram of a memory cell sub-array according to an embodiment of the present application;

FIG. 9b is a schematic diagram illustrating another memory cell sub-array according to an embodiment of the present application;

FIG. 10a is a schematic diagram of a memory cell sub-array according to another embodiment of the present application;

FIG. 10b is a schematic diagram illustrating another memory cell sub-array according to another embodiment of the present application;

FIG. 11 is a flowchart of a data writing method according to an embodiment of the present application;

FIG. 11a is a flowchart illustrating a data writing method according to another embodiment of the present application;

FIG. 11b is a flowchart illustrating a data writing method according to another embodiment of the present application;

FIG. 12a is a flowchart of a data writing method according to another embodiment of the present application;

FIG. 12b is a flowchart illustrating a data writing method according to another embodiment of the present application;

FIG. 13a is a schematic waveform diagram of a write operation according to an embodiment of the present application;

FIG. 13b is a schematic waveform diagram of a write operation according to another embodiment of the present application;

FIG. 14 is a flowchart of a data reading method according to an embodiment of the present application;

FIG. 15 is a flowchart of another data reading method according to an embodiment of the present application;

FIG. 15a is a flowchart of a data reading method according to another embodiment of the present application;

FIG. 15b is a flowchart illustrating a data reading method according to another embodiment of the present application;

FIG. 16a is a flowchart of a data reading method according to another embodiment of the present application;

FIG. 16b is a flowchart illustrating a data reading method according to another embodiment of the present application;

FIG. 17 is a schematic waveform diagram of a data read operation according to another embodiment of the present application;

FIG. 17a is a schematic diagram illustrating a process for writing back a first logic value according to an embodiment of the present application;

FIG. 17b is a flowchart illustrating a first logic value write-back process according to another embodiment of the present application;

FIG. 18a is a schematic waveform diagram of a data read operation according to an embodiment of the present application;

FIG. 18b is a schematic waveform diagram illustrating a data read operation according to another embodiment of the present application;

Fig. 19 is a schematic structural diagram of a data read-write device according to an embodiment of the present application.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. For example, a plurality of processing units refers to two or more processing units.

Furthermore, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to the orientation in which the components in the drawings are schematically disposed, and it should be understood that these directional terms may be relative concepts, which are used for descriptive and clarity with respect thereto, and which may be correspondingly varied according to the variation in orientation in which the components in the drawings are disposed. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the dimensional relationships between the parts in the drawings do not reflect actual dimensional relationships.

In embodiments of the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "electrically connected" may be a direct electrical connection or an indirect electrical connection via an intermediary.

In the embodiment of the present application, the term "module" is generally a functional structure divided according to logic, and the "module" may be implemented by pure hardware or a combination of hardware and software. In the embodiment of the present application, "and/or" describes the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may represent: a alone, B alone, and both A and B.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the embodiment of the present application, a metal-oxide-semiconductor field effect transistor (MOSFET) may be used as the transistor, and the transistor is classified into two types of an N (negative) transistor and a P (positive) transistor. The transistor includes a source (source), a drain (drain), and a gate (gate), and can be turned on or off by controlling the level of the gate of the input transistor. When the transistor is turned on, the source electrode and the drain electrode are turned on to generate an on current, and when the grid electrode level of the transistor is different, the magnitude of the on current generated between the source electrode and the drain electrode is also different; when the transistor is turned off, the source electrode and the drain electrode are not turned on, and no current is generated. In an embodiment of the present application, the gate of the transistor is also referred to as a control terminal, the source is referred to as a first terminal, and the drain is referred to as a second terminal; or the gate is called the control terminal, the drain is called the first terminal, and the source is called the second terminal. In addition, the N-type transistor is conducted when the level of the control end is high, the first end and the second end are conducted, and conduction current is generated between the first end and the second end; the N-type transistor is turned off when the level of the control end is low, the first end and the second end are not turned on, and no current is generated. The P-type transistor is conducted when the level of the control end is low, and the first end and the second end are conducted to generate conducting current; the P-type transistor is turned off when the level of the control terminal is high, the first terminal and the second terminal are not turned on, and no current is generated.

The embodiment of the application provides electronic equipment. The electronic device may include electronic products such as a mobile phone (mobile phone), a tablet (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, and the like. The embodiment of the application does not limit the specific form of the electronic device.

Fig. 1 is a schematic architecture diagram of an electronic device according to an exemplary embodiment of the present application. As shown in fig. 1, the electronic device 100 includes: memory 110, processor 120, input device 130, output device 140, and the like. Those skilled in the art will appreciate that the configuration of the electronic device shown in fig. 1 does not constitute a limitation of the electronic device 100, and the electronic device 100 may include more or fewer components than those shown in fig. 1, or may combine some of the components shown in fig. 1, or may be arranged differently than the components shown in fig. 1.

The memory 110 is used to store software programs and modules. The memory 110 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data created according to the use of the electronic device (such as audio data, image data, phonebook, etc.), and the like. Further, the memory 110 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transferred to each other. The external memory 111 includes, for example, a hard disk, a usb disk, a floppy disk, and the like. The internal memory 112 includes, for example, a random access memory, a read only memory, and the like. The random access memory may be, for example, a ferroelectric random access memory, hereinafter referred to as a ferroelectric memory.

The processor 120 is a control center of the electronic device 100, connects various parts of the entire electronic device 100 using various interfaces and lines, and performs various functions of the electronic device 100 and processes data by running or executing software programs and/or modules stored in the memory 110 and calling data stored in the memory 110, thereby performing overall monitoring of the electronic device 100. Optionally, the processor 120 may include one or more processing units. For example, the processor 120 may include a central processing unit (central processing unit, CPU), an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor, a digital signal processor (DIGITAL SIGNAL processor), a neural network processor, other application-specific integrated circuits (ASICs), and the like. In fig. 1, the processor 120 is taken as an example of a CPU, and the CPU may include an operator 121 and a controller 122. The arithmetic unit 121 acquires data stored in the internal memory 112, processes the data stored in the internal memory 112, and normally returns the processed result to the internal memory 112. The controller 122 may control the operator 121 to process the data, and the controller 122 may also control the external memory 111 and the internal memory 112 to store the data or read the data.

The input device 130 is used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device 100. By way of example, the input device 130 may include a touch screen, as well as other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Alternatively, the touch screen may comprise two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends the touch point coordinates to the processor 120, and can receive and execute commands sent from the processor 120. In addition, the touch screen may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, power switch keys, etc.), a trackball, mouse, joystick, etc. The controller 122 in the processor 120 may also control the input device 130 to receive an input signal or not. In addition, entered numeric or character information received by the input device 130, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 112.

The output device 140 is used for outputting signals corresponding to the data input by the input device 130 and stored in the internal memory 112. For example, the output device 140 outputs a sound signal or a video signal. The controller 122 in the processor 120 may also control the output device 140 to output a signal or not.

The thick arrow in fig. 1 is used to indicate the transmission of data, and the direction of the thick arrow indicates the direction of data transmission. For example, a single arrow between the input device 130 and the internal memory 112 indicates that data received by the input device 130 is transferred to the internal memory 112. For another example, double-headed arrows between the operator 121 and the internal memory 112 indicate that data stored in the internal memory 112 may be transferred to the operator 121, and data processed by the operator 121 may be transferred to the internal memory 112. Thin arrows in fig. 1 represent components that can be controlled by the controller 122. By way of example, the controller 122 may control the external memory 111, the internal memory 112, the operator 121, the input device 130, the output device 140, and the like.

Optionally, the electronic device 100 as shown in fig. 1 may also include various sensors. Such as gyroscopic sensors, hygrometric sensors, infrared sensors, magnetometer sensors, etc., are not described in detail herein. Optionally, the electronic device may further include a wireless fidelity (WIRELESS FIDELITY, wiFi) module, a bluetooth module, etc., which will not be described in detail herein.

It will be appreciated that in embodiments of the present application, an electronic device (e.g., the electronic device shown in fig. 1 described above) may perform some or all of the steps in embodiments of the present application, which are merely examples, and embodiments of the present application may also perform other operations or variations of the various operations. Furthermore, the various steps may be performed in a different order presented in accordance with embodiments of the application, and it is possible that not all of the operations in the embodiments of the application may be performed. The embodiments of the present application may be implemented alone or in any combination, and the present application is not limited thereto.

The ferroelectric memory performs data storage by utilizing the characteristics that spontaneous polarization can occur in the ferroelectric material and the polarization state can be reoriented along with the action of an external electric field. As shown in fig. 2, fig. 2 shows a schematic diagram of a hysteresis loop of a ferroelectric material. When an electric field is applied to a ferroelectric crystal, the central atom stays at a low energy state position I along the electric field, whereas when an electric field flip is applied to the same ferroelectric crystal, the central atom moves in the crystal along the direction of the electric field and stays at another low energy state position II. A large number of central atoms are mobile-coupled in a crystal unit cell to form ferroelectric domains that form polarized charges (also called flipped charges) under the action of an electric field. In order to ensure that the applied electric field is capable of reversing the polarization state of the ferroelectric material, the electric field strength should be greater than the coercive field strength Ec of the ferroelectric material, which refers to the reverse electric field strength required for the remanent polarization of the ferroelectric material to return to zero. For example, from position I in FIG. 2 to position II in FIG. 2, an electric field greater than-Ec needs to be applied to the ferroelectric material, and from position II in FIG. 2 to position I in FIG. 2, an electric field greater than +ec needs to be applied to the ferroelectric material.

The ferroelectric domain has higher inversion charge (shown as Q1 in fig. 2) when it is inverted under an electric field, and has lower inversion charge (shown as Q0 in fig. 2) when it is not inverted under an electric field, and the binary stable state of the ferroelectric material enables the ferroelectric material to be used as a memory, and the difference of the remnant polarization directions is utilized to apply the electric field in the same direction, so that the generated inversion charges are different, and the ferroelectric material can be used for storing data "0" and "1". When an electric field is applied to the ferroelectric material crystal, the central atoms move in the crystal along the direction of the electric field, and when the atoms move, the atoms pass through an energy barrier, so that charge breakdown is caused, after the electric field is removed, the central atoms can keep unchanged positions, and the polarization state can be kept, so that the ferroelectric material has the characteristic of non-volatility when used as a memory.

Illustratively, as shown in FIG. 2, assuming one polarization state (as represented by position I in FIG. 2) is a "0" state, the other polarization state (as represented by position II in FIG. 2) is a "1" state. Taking a ferroelectric material capacitor (hereinafter referred to simply as a ferroelectric capacitor) as an example, the ferroelectric capacitor refers to a capacitor using a ferroelectric material as a medium, and thus may have different polarization states, for example, a "0" state or a "1" state, an electric field applied to the ferroelectric capacitor in the "0" state may generate a charge Q0, an electric field applied to the ferroelectric capacitor in the "1" state may generate a charge Q1, the charge Q0 or the charge Q1 may be accumulated and converted into a read voltage, and data stored in the ferroelectric capacitor may be recognized according to the difference of the read voltage.

Memory Cells (MC) of ferroelectric memories include structures of 2T2C, 2T1C, 1T1C, and the like. A memory cell refers to the smallest structure of a memory used to access information or data, and is called "2T2C" if it contains two transistors (transistors) and two capacitors (capacitors); if two transistors (transistors) and one capacitor (capacitor) are included, then the transistor is called as '2T 1C'; if a transistor (transmitter) and a capacitor (capacitor) are included, it is called "1T1C".

FIG. 3 is a schematic diagram of a ferroelectric memory with a 2T2C memory structure, where the ferroelectric memory shown in FIG. 3 includes memory cells MC distributed in an array, each memory cell MC includes 2 access transistors and 2 ferroelectric capacitors, and the memory cell MC shown in FIG. 3 includes an access transistor T1, an access transistor T2 and a ferroelectric capacitor C1, and a ferroelectric capacitor C2, where control terminals of the access transistor T1 and the access transistor T2 are connected to Word Lines (WL) as in FIG. 3, a first terminal of the access transistor T1 is connected to Bit Lines (BL) as in FIG. 3, and a second terminal of the access transistor T1 is connected to a first plate of the ferroelectric capacitor C1; the first terminal of the access transistor T2 is connected to the bit line BLN1, the second terminal of the access transistor T2 is connected to the first plate of the ferroelectric capacitor C2, and the ferroelectric capacitor C1 and the second plate of the ferroelectric capacitor C2 are connected to the plate line (PLATE LINE, PL), as shown by the plate line PL1 in fig. 3.

Wherein word line WL1 is used to control the switching of access transistors T1, T2; plate line PL1 is used to charge ferroelectric capacitors C1, C2 to be polarized; the bit lines BL1 and BLN1 are used to write or read data into or from the ferroelectric capacitors C1 and C2 of the memory cell MC. When the word line WL1 controls the access transistors T1, T2 to be turned on, the first plate of the ferroelectric capacitor C1 is turned on with the bit line BL1, and the first plate of the ferroelectric capacitor C2 is turned on with the bit line BLN1, so that data on the bit line BL1 can be stored in the ferroelectric capacitor C1, data on the bit line BLN1 can be stored in the capacitor C2, or data stored in the ferroelectric capacitor C1 can be read through the bit line BL1, and data stored in the ferroelectric capacitor C2 can be read through the bit line BLN 1.

When data is stored, if the ferroelectric capacitor C1 stores "1", the corresponding "0" will be stored in the ferroelectric capacitor C2, if the ferroelectric capacitor C1 stores "0", the ferroelectric capacitor C2 stores "1", two pieces of data with opposite storage states are stored in the two ferroelectric capacitors in each memory cell MC, when the data stored in the memory cell MC is read, the voltages of the ferroelectric capacitor C1 and the ferroelectric capacitor C2 are simultaneously read, and are in contrast to each other, even if the voltages of the stored data "1" and the stored data "0" deviate, the corresponding data can be accurately read through the comparison of the read voltages of the ferroelectric capacitor C1 and the ferroelectric capacitor C2, so that the robustness of the 2T2C structure is higher, but because the read voltage formed by the inversion charges generated by the ferroelectric capacitor C1 and the ferroelectric capacitor C2 is read when the data is read, the capacitor size in the memory is small, the capacity is low, the charge capable of being stored is limited, the read voltage window is small, and each memory cell comprises 2 access transistors and 2 ferroelectric capacitors, so that the storage density is low and the storage cost is high.

Fig. 4 shows a ferroelectric memory of a 2T1C memory structure, and the ferroelectric memory shown in fig. 4 includes memory cells MC distributed in an array, each memory cell MC including 2 access transistors and 1 ferroelectric capacitor, for example, the memory cell MC shown in fig. 4 includes an access transistor T1, an amplifying transistor T2 and a ferroelectric capacitor C. Wherein the control terminal of the access transistor T1 is connected to the word line WL1, the first terminal of the access transistor T1 is connected to the bit line BL1, the second terminal of the access transistor T1 is connected to the first plate of the ferroelectric capacitor C1, the second plate of the ferroelectric capacitor C1 is connected to the plate PL1, the control terminal of the amplifying transistor T2 is connected to the first plate of the ferroelectric capacitor C1, the first terminal of the amplifying transistor T2 is connected to the bit line BL1, and the second terminal of the amplifying transistor T2 is connected to the Source Line (SL), such as the source line SL1 shown in fig. 4. The 2T1C memory structure includes an amplifying transistor T2 for amplifying a signal in addition to a conventional access transistor T1 for storing data and a ferroelectric capacitor C. When the access transistor T1 is turned on, the first plate of the ferroelectric capacitor C is connected to the bit line BL1, so that data on the bit line BL1 can be stored in the ferroelectric capacitor C, when data is read, the voltage on the ferroelectric capacitor C is converted into a current between the first end and the second end of the amplifying transistor T2 by the amplifying transistor T2, and when the data is read, if the flip charge is smaller, the obtained voltage is smaller, and when the channel current is regulated by the gate voltage, a larger current can be obtained between the first end and the second end of the amplifying transistor T2, so that the read window is larger, but when the current signal is read, the peripheral circuit needs to use a current-type sensitive amplifier, and the area of the current-type sensitive amplifier is larger, so that the power consumption, the performance and the area (power, performance, area, PPA) of the peripheral circuit are deteriorated. Meanwhile, since two transistors are required to be arranged for each memory cell, the memory density is low and the manufacturing cost is high.

The ferroelectric memories of the 2T2C and 2T1C memory structures have lower memory density and larger occupied area, and the micro performance and the memory capacity of the ferroelectric memories are affected. Fig. 5 shows a schematic diagram of a ferroelectric memory with a 1T1C memory structure, where each memory cell MC includes an access transistor and a ferroelectric capacitor, so that the memory density is high and the memory capacity of the ferroelectric memory can be improved. The memory cell MC shown in fig. 5 includes an access transistor T and a storage capacitor C, wherein a control terminal of the access transistor T is connected to a word line WL1, a first terminal of the access transistor T is connected to a bit line BL1, a second terminal of the access transistor T is connected to a first plate of the ferroelectric capacitor C, and a second plate of the ferroelectric capacitor C is connected to a plate line PL1.

The word line WL1 is used for enabling the access transistor T of the memory cell MC, controlling the access transistor T to be turned on, the bit line BL1 and the plate line PL1 are used for charging the ferroelectric capacitor C of the memory cell MC, so that the ferroelectric capacitor C is in different polarization states (as shown in fig. 2), and further, the different polarization states of the ferroelectric capacitor C can be used to represent data "0" and "1", when the data stored in the memory cell MC are read, an excitation voltage VW (the excitation voltage VW is greater than a coercive field strength Ec of the ferroelectric material and is sufficient to invert the polarization state of the ferroelectric capacitor) is applied to the ferroelectric capacitor C in the memory cell MC through the plate line PL1, the ferroelectric capacitor C generates an inversion charge under the effect of the excitation voltage VW, the read data is determined according to the amount of the inversion charge, the inversion charge is accumulated on the bit line BL1 to form a read voltage, when the bit line BL1 is low in level, and when the bit line BL1 is high in level, the inversion charge is represented more. For example, it may be used to indicate that the data stored in the memory cell MC is "1" when more inversion charges are generated, and to indicate that the stored data is "0" when the inversion charges are less. In another case, the data stored may be indicated as "0" when the flipped charge is greater, and "1" when the flipped charge is less. When a read operation is performed, the voltage of the word line WL1 is raised to turn on the access transistor T of the memory cell MC, then the excitation voltage VW is output to the plate line PL1, after the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C, the generated flipped charge is distributed to the parasitic capacitance of the bit line BL1 to form a read voltage on the bit line BL1, and if the data stored in the ferroelectric capacitor C is "1", as shown in fig. 2, the flipped charge "Q1" forms a read voltage on the bit line BL1 during the read; if the data stored in the ferroelectric capacitor C is "0", the flipped charge "Q0" forms a read voltage on the bit line BL1 during reading, and the memory has a small size, a low capacitance value, and a small amount of flipped charge, and the read voltage is formed by accumulating the flipped charge on the bit line, so that the read voltage window is small, which may possibly cause a problem that the stored data cannot be read accurately.

In order to solve the above-mentioned problems, an embodiment of the present application provides a ferroelectric memory, referring to fig. 6, which includes one or more memory cell sub-arrays, for example, memory cell sub-arrays subarray i to subarray i+m in fig. 6, each of which includes ferroelectric memory cells MC distributed in an array, and m is a positive integer. Wherein ferroelectric memory cells MC located in the same row in each memory cell sub-array are connected to the same word line WL, such as one of word lines WL1 to WLn; ferroelectric memory cells MC located in the same row are connected to the same plate line PL, such as one of plate lines PL1 to PLn; ferroelectric memory cells MC located in the same column are connected to the same Local Bit Line (LBL), such as one of local bit lines LBL1 to LBLn. Each memory cell sub-array is further provided with a row of gain units GU (gain unit), such as gain unit GU1, gain unit GU 2-gain unit GUn, and each column of ferroelectric memory cells MC in the memory cell sub-array is correspondingly connected with one gain unit GU through a local bit line LBL.

The gain unit GU includes an amplifying transistor Tg, a control terminal of the amplifying transistor Tg is electrically connected to a local bit line LBL to which the column of ferroelectric memory cells MC is connected, a first terminal of the amplifying transistor Tg is electrically connected to a global bit line (LBL), and a second terminal of the amplifying transistor Tg is connected to a source line SL.

As shown in fig. 7, as the first column of ferroelectric memory cells MC is connected to the gain cell GU1 through the local bit line LBL1, the second column of ferroelectric memory cells MC is connected to the gain cell GU2 through the local bit line LBL2, and the nth column of ferroelectric memory cells MC is connected to the gain cell GUn through the local bit line LBLn.

Referring to fig. 6 and 7, taking a subarray of memory cells subarray i as an example, a first column of ferroelectric memory cells MC is connected to local bit line LBL1, a first row of ferroelectric memory cells MC is connected to word line WL1, and the first row of ferroelectric memory cells MC is also connected to word line PL1. The first column of ferroelectric memory cells MC is connected to the gain cell GU1 via a local bit line LBL1, wherein the gain cell GU1 comprises an amplifying transistor Tg1, the control terminal of the amplifying transistor Tg1 is connected to the local bit line LBL1, the first terminal of the amplifying transistor Tg1 is connected to the global bit line GBL1, and the second terminal of the amplifying transistor Tg1 is connected to the source line SL1.

The second column of ferroelectric memory cells MC is connected to the local bit line LBL2, the second row of ferroelectric memory cells MC is connected to the word line WL2, and the second row of ferroelectric memory cells MC is also connected to the word line PL2. The second column of ferroelectric memory cells MC is connected to the gain cell GU2 via the local bit line LBL2, wherein the gain cell GU2 comprises an amplifying transistor Tg2, the control terminal of the amplifying transistor Tg2 of the gain cell GU2 is connected to the local bit line LBL2, the first terminal of the amplifying transistor Tg2 of the gain cell GU2 is connected to the global bit line GBL2, and the second terminal of the amplifying transistor Tg1 of the gain cell GU2 is connected to the source line SL2.

The ferroelectric memory cell MC includes an access transistor T and a ferroelectric capacitor C, the control terminal of the access transistor T is connected to the word line WL, the first terminal of the access transistor T is connected to the local bit line LBL, the second terminal of the access transistor T is connected to the first plate of the ferroelectric capacitor C, and the second plate of the ferroelectric capacitor C is connected to the plate line PL. Referring to fig. 7 and 8, taking ferroelectric memory cell MC1 of fig. 8 as an example, the control terminal of access transistor T of ferroelectric memory cell MC1 is connected to bit line WL1, the first terminal of access transistor T is connected to local bit line LBL1, the second terminal of access transistor T is connected to the first plate of ferroelectric capacitor C, and the second plate of ferroelectric capacitor C is connected to plate line PL 1. The first terminal of the access transistor T is connected to the control terminal of the amplifying transistor Tg1 of the gain unit GU1 via a local bit line LBL 1.

When reading data stored in the ferroelectric memory cell MC, for example, when reading the ferroelectric memory cell MC1 shown in fig. 8, the amplifying transistor Tg1 of the gain unit GU1 can amplify a voltage window formed on the local bit line LBL1 by the flipped charge on the ferroelectric capacitor C of the ferroelectric memory cell MC1 to a read voltage window on the global bit line GBL1, and when reading data, the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on, the excitation voltage VW is applied to the ferroelectric capacitor C, and the voltage of the local bit line LBL1 is raised by the flipped charge generated by the ferroelectric capacitor C, that is, the voltage of the control terminal of the amplifying transistor Tg1 is raised. If the flipped charge is less (Q0 as shown in fig. 2), the voltage of the local bit line LBL1 is lower, the amplifying transistor Tg1 is in an off state, and if the flipped charge is more (Q1 as shown in fig. 2), the voltage of the local bit line LBL1 is higher, the amplifying transistor Tg1 is in an on state; the first end of the amplifying transistor Tg1 is connected to the global bit line GBL1, the second end of the amplifying transistor Tg1 is connected to the source line SL1, when the amplifying transistor Tg1 is in the off state and the on state, different read voltages can be read on the global bit line GBL1, that is, the line voltage of the global bit line GBL1 or the line voltage of the source line SL1, and a voltage window formed by the line voltage of the global bit line GBL1 or the line voltage of the source line SL1 is larger than a voltage window formed by the flipped charges of the ferroelectric capacitor C on the local bit line LBL1, so that the flipped charges on the ferroelectric memory cell MC are amplified to the read voltage on the global bit line GBL, thereby realizing the amplification of the read window.

For example, referring to fig. 8, when reading the data of the ferroelectric memory cell MC1, the first terminal of the amplifying transistor Tg1 is precharged to a first level, the first terminal of the amplifying transistor Tg1 is floating at the first level, and a second level is output to the source line SL1, wherein the second level is different from the first level, for example, the first level is a high level, and the second level is a low level; or the second level is a high level, the first level is a low level, and the second level may be set to a low level in order to reduce power consumption. The control terminal of the amplifying transistor Tg1 of the gain unit GU1 is pre-charged to the third level, and then the control terminal of the amplifying transistor Tg1 is suspended at the third level, wherein when the control terminal of the amplifying transistor Tg1 is at the third level, the amplifying transistor Tg1 is in an off state.

After the precharge is completed, the access transistor T of the ferroelectric memory cell MC1 is controlled to be conducted, an excitation voltage VW is applied to the plate line PL1, a flip charge is generated after the ferroelectric capacitor C of the ferroelectric memory cell MC1 is applied with the excitation voltage VW, the flip charge is accumulated on the local bit line LBL1 to form a voltage, if the flip charge is more, the voltage on the local bit line LBL1 is higher, when the turn-on threshold of the amplifying transistor Tg1 is exceeded, the amplifying transistor Tg1 is conducted, the first end and the second end of the amplifying transistor Tg1 are conducted, the global bit line GBL1 is communicated with the source line SL1, the voltage on the global bit line GBL1 is the same as the voltage of the source line SL1, and the read voltage on the global bit line GBL1 is the line voltage of the source line SL1, namely a second level; if the flipped charge is small, the voltage on the local bit line LBL1 is low enough to turn on the amplifying transistor Tg1, and the voltage on the global bit line GBL1 is the voltage at the first end (i.e., the first level) of the amplifying transistor Tg1, so that when the data stored in the ferroelectric memory cell MC1 is read, the voltage generated by the flipped charge of the ferroelectric memory cell MC1 on the local bit line LBL1 is converted and amplified into the read voltage (the first level or the second level) on the global bit line GBL1 by the amplifying transistor Tg1, and the data stored in the ferroelectric memory cell MC1 is determined according to the read voltage, thereby realizing the amplification of the read window. Illustratively, when the ferroelectric capacitor generates less flipped charge, the read data is determined to be "0" when the read voltage is at the first level, when the ferroelectric capacitor generates more flipped charge, the read data is determined to be "1" when the read voltage is at the second level, or alternatively, the read data is determined to be "1" when the read voltage is at the first level, the read data is determined to be "0" when the read voltage is at the second level,

In the ferroelectric memory provided by the embodiment of the application, when the data stored in the ferroelectric memory cell MC1 is read, the read voltage of the GBL1 on the global bit line is detected, the read voltage on the global bit line GBL1 is controlled by the amplifying transistor Tg1, when the amplifying transistor Tg1 is turned on, the global bit line GBL1 is communicated with the source line SL1, the voltage on the global bit line GBL1 is pulled down (the source line SL1 is at a low level) or pulled up (the source line SL1 is at a high level) by the source line SL1, when the amplifying transistor Tg1 is turned off, the voltage on the global bit line GBL1 is the voltage at the first end of the amplifying transistor Tg1, and the read voltage is related to the on state of the amplifying transistor Tg1, so that the influence of factors other than the inversion charge of the ferroelectric memory cell MC1 on the on state of the amplifying transistor Tg1 is eliminated, and the precharge operation is required before the read operation.

The gain cell further includes a first transistor having a control terminal coupled to a first control line (write control line, CL), a first terminal electrically coupled to a Write Bit Line (WBL), and a second terminal electrically coupled to a local bit line LBL coupled to the control terminal of the amplifying transistor.

Referring to fig. 8 and 9a, for example, the gain unit GU1 further includes a first transistor Tc1, wherein a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the write bit line WBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1 connected to a control terminal of the amplifying transistor Tg 1.

The first transistor Tc1 is used to precharge the control terminal of the amplifying transistor Tg1 to a third level before a read operation, and when the control terminal is at the third level, the amplifying transistor Tg1 is in an off state, so that a voltage formed by accumulating the flipped charge of the ferroelectric capacitor C of the ferroelectric memory cell MC1 on the local bit line LBL1 during the read operation can control the on state of the amplifying transistor Tg 1.

In one possible implementation, taking the first transistor Tc1 as an N-type transistor as an example, in the pre-charging stage, a high level is output to the first control line CL1, the first transistor Tc1 is controlled to be turned on, a third level (for example, the third level may be a voltage of 0) is output to the write bit line WBL1, the write bit line WBL1 pulls down the voltage on the local bit line LBL1 to the third level through the first transistor Tc1, the control terminal of the amplifying transistor Tg1 is set to the third level, the pre-charging of the control terminal of the amplifying transistor Tg1 is completed, when the control terminal of the amplifying transistor Tg1 is at the third level, the amplifying transistor Tg1 is in an off state, the control terminal of the amplifying transistor Tg1 is pre-charged to the third level, the first transistor Tc1 is turned off, and the control terminal of the amplifying transistor Tg1 is suspended, at this time, the control terminal of the amplifying transistor Tg1 is kept at the third level.

After the control terminal of the amplifying transistor Tg1 is precharged to the third level (the local bit line LBL1 is also the third level at this time), the voltage formed by accumulating the flipped charges of the ferroelectric capacitor C of the ferroelectric memory cell MC1 on the local bit line LBL1 can be turned on or off, so that different read voltages can be presented on the global bit line GBL 1. When the amplifying transistor Tg1 is conducted, the global bit line GBL1 is communicated with the source line SL1 through the amplifying transistor Tg1, and the voltages of the global bit line GBL1 and the source line SL1 are the same; when the amplifying transistor Tg1 is turned off, the voltage on the global bit line GBL1 is the voltage of the first end of the amplifying transistor Tg1, so that different read voltages can be detected on the global bit line GBL1 when the amplifying transistor Tg1 is in the on state and the off state, different voltage signals need to be provided on the source line SL1 and the first end of the amplifying transistor Tg1, for example, the first end of the amplifying transistor Tg1 is precharged to a first level, and a second level is output to the source line SL1, where the first level is different from the second level in voltage, for example, the first level is a high level signal, the second level is a low level signal, or the first level is a low level signal, and the second level is a high level signal.

The gain unit includes a second transistor, a control terminal of the second transistor is electrically connected to the second control line, a first terminal of the second transistor is electrically connected to the write bit line, and a second terminal of the second transistor is electrically connected to the global bit line to which the first terminal of the amplifying transistor is connected.

With continued reference to fig. 9a, for example, the gain unit GU1 further includes a second transistor Tr1, a control terminal of the second transistor Tr1 is connected to the second control line CL2, a first terminal of the second transistor Tr1 is connected to the write bit line WBL1, and a second terminal of the second transistor Tr1 is connected to the global bit line GBL1.

The second transistor Tr1 is used to precharge the first terminal of the amplifying transistor Tg1 (i.e., the global bit line GBL 1) to a first level different from the voltage of the source line SL1 before the read operation, so that a different read voltage can be read on the global bit line GBL1 when the amplifying transistor Tg1 is in an on state or an off state during the read phase.

Taking the second transistor Tr1 as an N-type transistor as an example, in conjunction with fig. 9a, in the precharge phase, a high level is output to the second control line CL2, the second transistor Tr1 is controlled to be turned on, a first level is output to the write bit line WBL1, the write bit line WBL1 is communicated with the global bit line GBL1 through the second transistor Tr1, the voltage of the global bit line GBL1 is pulled up to the first level, the first end of the amplifying transistor Tg1 is pulled up to the first level, then the second transistor Tr1 is controlled to be turned off, the first end of the amplifying transistor Tg1 is suspended, and at this time, the first end of the amplifying transistor Tg1 is kept at the first level.

After the control terminal and the first terminal of the amplifying transistor Tg1 are precharged, the ferroelectric memory cell MC1 can be read, the exciting voltage VW is applied to the ferroelectric capacitor C of the ferroelectric memory cell MC1, and then the read voltage on the global bit line GBL1 is detected or induced to read the data stored in the ferroelectric memory cell MC 1.

In the above example, the ferroelectric memory cells MC1 in the first column of ferroelectric memory cells MC are taken as an example, and the connection relationship and the operation principle of the first column of ferroelectric memory cells MC and the gain cells GU1 are described, where the memory cell sub-array subarray includes ferroelectric memory cells MC distributed in an array and a row of gain cells GU, each column of ferroelectric memory cells MC is correspondingly provided with one gain cell GU, in the memory cell sub-array subarray, the same row of gain cells GU is connected to the same first control line CL1, and the same row of gain cells GU is connected to the same second control line CL2.

For example, referring to fig. 9a, the memory cell sub-array subarray further includes a second column of ferroelectric memory cells MC and a gain cell GU2, the second column of ferroelectric memory cells MC being connected to the local bit line LBL2, the gain cell GU2 including an amplifying transistor Tg2, a first transistor Tc2 and a second transistor Tr2. The control terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the local bit line LBL2, the first terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the global bit line GBL2, and the second terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the source line SL 2.

The control terminal of the first transistor Tc2 of the gain unit GU2 is connected to the first control line CL1, the first terminal of the first transistor Tc2 of the gain unit GU2 is connected to the write bit line WBL2, and the second terminal of the first transistor Tc2 of the gain unit GU2 is connected to the local bit line LBL2.

The control end of the second transistor Tr2 of the gain unit GU2 is connected to the second control line CL2, the first end of the second transistor Tr2 of the gain unit GU2 is connected to the write bit line WBL2, and the second end of the second transistor Tr2 of the gain unit GU2 is connected to the global bit line GBL2.

As can be seen from the above, in the memory cell sub-array subarray i, the first transistor Tc1 in the gain cell GU1 and the first transistor Tc2 in the gain cell GU2 are connected to the same first control line CL1; the second transistor Tr1 in the gain unit GU1 is connected to the same second control line CL2 as the second transistor Tr2 in the gain unit GU 2.

In the same memory cell subarray, gain cells in the same row can share the same first control line and the same second control line, so that the cost can be reduced, and the area of the ferroelectric memory can be reduced.

The above embodiments describe a memory cell sub-array subarray i, and the ferroelectric memory provided in the embodiments of the present application may further include a plurality of memory cell sub-arrays, and as illustrated in fig. 9b, the ferroelectric memory further includes a memory cell sub-array subarray i+1, where the memory cell sub-array subarray i+1 and the memory cell sub-array subarray i are distributed in a column direction, and different memory cell sub-arrays distributed in the column direction may be connected to the same write bit line WBL, the same global bit line GBL, and the same source line SL.

For example, in the memory cell sub-array subarray i+1, the first column of ferroelectric memory cells MC including the first column of ferroelectric memory cells MC, the gain cell GU1 is disposed corresponding to the first column of ferroelectric memory cells MC of the memory cell sub-array subarray i+1, and the gain cell GU1 includes the amplifying transistor Tg1, the first transistor Tc1, and the second transistor Tr1.

The first end of the amplifying transistor Tg1 in the memory cell sub-array subarray i+1 is connected to the same global bit line GBL, i.e. the global bit line GBL1 shown in fig. 9b, and the second end of the amplifying transistor Tg1 in the memory cell sub-array subarray i+1 is connected to the same source line SL, i.e. the source line SL1 shown in fig. 9 b.

The first terminal of the first transistor Tc1 in the memory cell sub-array subarray i+1 is connected to the same write bit line WBL as the first terminal of the first transistor Tc1 in the memory cell sub-array subarray i, i.e. write bit line WBL1 shown in fig. 9b, the first terminal of the second transistor Tr1 in the memory cell sub-array subarray i+1 is connected to the same write bit line WBL as the first terminal of the second transistor Tr1 in the subarray i, i.e. write bit line WBL1 shown in fig. 9b, and the second terminal of the second transistor Tr1 in the memory cell sub-array subarray i+1 is connected to the same global bit line GBL as the second terminal of the second transistor Tr1 in the memory cell sub-array subarray i, e.g. global bit line GBL1 shown in fig. 9 b.

Different memory cell subarrays share the write bit line WBL, the global bit line GBL and the source line SL, so that the occupied area of the ferroelectric memory can be reduced, and the cost can be reduced.

The foregoing embodiment describes an implementation manner in which the gain unit GU includes the amplifying transistor Tg, the first transistor Tc, and the second transistor Tr, the control terminal of the amplifying transistor Tg is precharged by the first transistor Tc, the first terminal of the amplifying transistor Tg is precharged by the second transistor Tr, and in another embodiment of the present application, the structure of the gain unit GU may be simplified, and the gain unit includes the first transistor, the control terminal of the first transistor is electrically connected to the first control line, the first terminal of the first transistor is electrically connected to the global bit line connected to the first terminal of the amplifying transistor, and the second terminal of the first transistor is electrically connected to the local bit line connected to the control terminal of the amplifying transistor.

For example, referring to fig. 8 in combination with fig. 10a, the gain unit GU1 includes a first transistor Tc1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the global bit line GBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1.

Before the operation of reading the data of the ferroelectric memory cell MC1, the first transistor Tc1 is used to precharge the control terminal of the amplifying transistor Tg1 to the third level, and when the control terminal is the third level, the amplifying transistor Tg1 is in the off state, so that the voltage formed by accumulating the flipped charge of the ferroelectric capacitor C of the ferroelectric memory cell MC1 on the local bit line LBL1 during the reading can control the on state of the amplifying transistor Tg 1.

Taking the first transistor Tc1 as an N-type transistor as an example, in the precharge phase, a high level is output to the first control line CL1, the first transistor Tc1 is controlled to be turned on, a third level is output to the global bit line GBL1, the global bit line GBL1 pulls down the voltage on the local bit line LBL1 to the third level through the first transistor Tc1, the control terminal of the amplifying transistor Tg1 is set to the third level, the precharge of the control terminal of the amplifying transistor Tg1 is completed, the control terminal of the amplifying transistor Tg1 is precharged to the third level, the first transistor Tc1 is controlled to be turned off, and the control terminal of the amplifying transistor Tg1 is suspended, at this time, the control terminal of the amplifying transistor Tg1 is kept at the third level.

After the control terminal of the amplifying transistor Tg1 is precharged to the third level, the voltage formed by accumulating the flipped charges of the ferroelectric capacitor C of the ferroelectric memory cell MC1 on the local bit line LBL1 may be turned on or off, so that different read voltages may be presented on the global bit line GBL 1. When the amplifying transistor Tg1 is conducted, the global bit line GBL1 is communicated with the source line SL1 through the amplifying transistor Tg1, and the voltages of the global bit line GBL1 and the source line SL1 are the same; when the amplifying transistor Tg1 is turned off, the voltage on the global bit line GBL1 is the voltage of the first end of the amplifying transistor Tg1, so that different read voltages can be detected on the global bit line GBL1 when the amplifying transistor Tg1 is in the on state and the off state, different voltage signals need to be provided on the first end of the amplifying transistor Tg1 and the source line SL1, for example, the first end of the amplifying transistor Tg1 is precharged to a first level, and a second level is output to the source line SL1, where the first level is different from the second level in voltage, for example, the first level is a high level signal, the second level is a low level signal, or the first level is a low level signal, and the second level is a high level signal.

After the control end of the amplifying transistor Tg1 is precharged to the third level, the first transistor Tc1 is controlled to be turned off, the first level is output to the global bit line GBL1, the first end of the amplifying transistor Tg1 is precharged to the first level, then the signal output to the global bit line GBL1 is stopped, the first end of the amplifying transistor Tg1 is suspended, and at the moment, the first end of the amplifying transistor Tg1 is kept at the first level.

In the above example, the ferroelectric memory cells MC1 in the first column of ferroelectric memory cells are taken as an example, and the connection relationship and the operation principle of the first column of ferroelectric memory cells MC and the gain cells GU1 are described, where the memory cell sub-array subarray includes ferroelectric memory cells MC distributed in an array and one row of gain cells GU, each column of ferroelectric memory cells MC is correspondingly provided with one gain cell GU, and the control terminals of the first transistors Tc of the gain cells GU located in the same row are electrically connected to the same first control line CL1.

For example, with continued reference to fig. 10a, the first memory cell sub-array subarray further includes a second column of ferroelectric memory cells MC and a gain cell GU2, the second column of ferroelectric memory cells MC being connected to the local bit line LBL2, the gain cell GU2 also including an amplifying transistor Tg2 and a first transistor Tc2. The control terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the local bit line LBL2, the first terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the global bit line GBL2, and the second terminal of the amplifying transistor Tg2 of the gain unit GU2 is connected to the source line SL2.

The control terminal of the first transistor Tc2 of the gain unit GU2 is connected to the first control line CL1, the first terminal of the first transistor Tc2 of the gain unit GU2 is connected to the global bit line GBL1, and the second terminal of the first transistor Tc2 of the gain unit GU2 is connected to the local bit line LBL2.

In the same memory cell sub-array, the gain cells GU in the same row may share the same first control line CL1, which may reduce the cost and reduce the area of the ferroelectric memory.

The above embodiments describe a memory cell sub-array subarray i, and the ferroelectric memory provided in the embodiments of the present application includes one or more memory cell sub-arrays, and as illustrated in fig. 10b, the ferroelectric memory further includes a memory cell sub-array subarray i+1, where the memory cell sub-array subarray i+1 and the memory cell sub-array subarray i are distributed in a column direction, and in different memory cell sub-arrays, the first ends of the amplifying transistors Tg of the gain cells GU located in the same column are electrically connected to the same global bit line GBL; the second ends of the amplifying transistors Tg of the gain units GU located in the same column are electrically connected to the same source line SL; the first ends of the first transistors Tc of the gain cells located in the same column are electrically connected to the same global bit line GBL.

For example, as shown in fig. 10b, in the memory cell sub-array subarray i+1, the first column of ferroelectric memory cells MC including the first column of ferroelectric memory cells MC, the gain cell GU1 is provided corresponding to the first column of ferroelectric memory cells MC of the memory cell sub-array subarray i+1, and the gain cell GU1 includes the amplifying transistor Tg1 and the first transistor Tc1.

In the memory cell sub-array subarray i+1, a first end of an amplifying transistor Tg1 of a gain cell GU1 is connected to a global bit line GBL1, a second end of the amplifying transistor Tg1 of the gain cell GU1 is connected to a source line SL1, and a first end of a first transistor Tc1 of the gain cell GU1 is connected to the global bit line GBL1.

In the multiple memory cell subarrays, the gain cells in the same column can share the global bit line GBL and the source line SL, so that the occupied area of the ferroelectric memory can be reduced, and the cost is reduced.

Based on the ferroelectric memory, the embodiment of the present application further provides a data writing method for writing data into the ferroelectric memory provided in the above embodiment. Writing data includes writing "0" and writing "1". Data is written into the ferroelectric memory essentially by using an electric field to bring the ferroelectric capacitance of the ferroelectric memory cell to a predetermined polarization state, for example, the polarization state represented by position I and the polarization state represented by position II in fig. 2, and a different voltage difference is exhibited between the two plates of the ferroelectric capacitance in different polarization states, and if one of the states is used to indicate that the ferroelectric memory cell stores data "0", the other is used to indicate that the ferroelectric memory cell stores data "1".

In the following, referring to fig. 8, a data writing method will be described by taking the ferroelectric memory cell MC1 in the first column of the ferroelectric memory cells MC in the memory cell sub-array subarray i+1 as a target ferroelectric memory cell for writing data, where a row where a non-target ferroelectric memory cell is located is referred to as a selected row, a column where a target ferroelectric memory cell is located is referred to as a selected column, and a column where a non-target ferroelectric memory cell is located is referred to as a non-selected column.

Referring to fig. 11, the data writing method provided by the embodiment of the application includes steps S210-S240.

S210: the access transistor of the control target ferroelectric memory cell is turned on.

S220: the local bit line to which the target ferroelectric memory cell is connected is charged to a first voltage.

S230: and outputting a second voltage to the plate line connected to the target ferroelectric memory cell, wherein the second voltage is different from the first voltage.

S240: and charging local bit lines except the local bit lines connected with the target ferroelectric memory cells in the memory cell subarray to a second voltage.

For example, referring to fig. 8 in combination, taking the ferroelectric memory cell MC1 as the target ferroelectric memory cell, the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is connected to the local bit line LBL1 through the access transistor T, and the local bit line LBL1 is charged to the first voltage, that is, the first plate of the ferroelectric capacitor C is set to the first voltage; a second voltage is output to the plate line PL1, that is, the second plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to the second voltage, and the voltage difference between the first plate and the second plate represents the data stored in the ferroelectric memory cell MC 1.

When the access transistors T of the ferroelectric memory cell MC1 are controlled to be turned on, the access transistors T of all the ferroelectric memory cells MC connected to the word line WL1 are turned on, and when the second voltage is output to the plate line PL1, the second plate of all the ferroelectric capacitors C connected to the plate line PL1 is set to the second voltage, and in order to avoid overwriting data of non-target ferroelectric memory cells, the first plate of the ferroelectric capacitors of all the other ferroelectric memory cells in the row where the ferroelectric memory cell MC1 is located needs to be set to the second voltage, so that the voltages of the first plate and the second plate of the ferroelectric capacitors of all the other ferroelectric memory cells except the target ferroelectric memory cell in the row are both the second voltage, and the voltage difference is 0, so that the stored data of the ferroelectric memory cells cannot be overwritten.

Referring to fig. 8, the control terminal of the access transistor T of the ferroelectric memory cell MC1 is connected to the word line WL1, and the access transistor T is illustratively an N-type transistor, outputs a high signal to the word line WL1, and the access transistor T of the ferroelectric memory cell MC1 is turned on.

After the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on, the local bit line LBL1 is charged to a first voltage, that is, the first plate of the ferroelectric memory cell MC1 is set to the first voltage, for example, referring to fig. 9a, the gain unit GU1 includes an amplifying transistor Tg1, a first transistor Tc1, and a second transistor Tr1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the write bit line WBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1; the control terminal of the second transistor Tr1 is connected to the second control line CL2, the first terminal of the second transistor Tr1 is connected to the write bit line WBL1, and the second terminal of the second transistor Tr1 is connected to the global bit line GBL1, in this case, referring to fig. 11a, s220 includes:

S220a: the first transistor is controlled to be turned on, a first voltage is output to the write bit line, and the local bit line connected with the target ferroelectric memory cell is charged to the first voltage.

The first transistor Tc1 is turned on, the write bit line WBL1 is connected to the local bit line LBL1 through the first transistor Tc1, a first voltage is output to the write bit line WBL1, the local bit line LBL1 is charged to the first voltage, and at this time, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is charged to the first voltage by the local bit line LBL1.

In another possible implementation, in conjunction with fig. 10a, the gain unit GU includes an amplifying transistor Tg1 and a first transistor Tc1, wherein a control terminal of the first transistor Tc1 is connected to a first control line CL1, a first terminal of the first transistor Tc1 is connected to a global bit line GBL1, and a second terminal of the first transistor Tc1 is connected to a local bit line LBL1, in this case, referring to fig. 11b, s220 includes:

S220b: the first transistor is controlled to be turned on, a first voltage is output to the global bit line, and the local bit line connected with the target ferroelectric memory cell is charged to the first voltage.

The first transistor Tc1 is turned on, the global bit line GBL1 is connected to the local bit line LBL1 through the first transistor Tc1, the local bit line LBL1 is charged to the first voltage through the global bit line GBL1, and at this time, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is charged to the first voltage by the local bit line LBL1.

The local bit line LBL1 is charged to a first voltage, and when the access transistor T of the ferroelectric memory cell MC1 is in an on state, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is charged to the first voltage by the local bit line LBL1, and then a second voltage is output to the plate line PL1, and the second plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to a second voltage, wherein the second voltage is different from the first voltage, and a voltage difference between the first plate and the second plate is representative of data stored in the ferroelectric memory cell MC 1.

In order to avoid overwriting data in non-target ferroelectric memory cells while writing data in target ferroelectric memory cells, it is also necessary to set the first plate of the ferroelectric capacitor of all other ferroelectric memory cells in the row in which the target ferroelectric memory cells are located to the second voltage, and in one possible implementation, for example, please describe S240 in connection with fig. 9a, 11a and 12a, in connection with the first example of S220, S240 may be implemented as follows:

S240a: outputting a second voltage to other write bit lines except the write bit line corresponding to the target ferroelectric memory cell in the memory cell subarray, and charging the local bit line except the local bit line connected with the target ferroelectric memory cell to the second voltage.

In the memory cell sub-array subarray, taking the ferroelectric memory cell MC1 as an example, the gain cells GU in the same row are connected to the same first control line CL1, so when the first control line CL1 is enabled to control the first transistor Tc1 to be turned on, all the first transistors in the row gain cells GU1 to GUn are turned on, the write bit line WBL corresponding to each column of the ferroelectric memory cells MC in the memory cell sub-array subarray is turned on with the local bit line LBL corresponding to the column of the ferroelectric memory cells MC, so that the second voltage is output to the other write bit lines WBL except the write bit line WBL1 in the memory cell sub-array subarray, and the local bit line LBL except the local bit line LBL1 in the memory cell sub-array subarray i is charged to the second voltage, thereby preventing the data of other non-target ferroelectric memory cells from being rewritten.

In another possible implementation, please refer to fig. 10a, 11b and 12b in combination, S240 is described herein in connection with the second example of S220, and S240 may be further implemented as follows:

S240b: and outputting a second voltage to other global bit lines except the global bit line corresponding to the target ferroelectric memory cell in the memory cell subarray, and charging other local bit lines except the local bit line connected with the target ferroelectric memory cell to the second voltage.

In connection with fig. 10a, taking ferroelectric memory cell MC1 as the target ferroelectric memory cell as an example, in the memory cell sub-array subarray, the same row of gain cells GU is connected to the same first control line CL1, so that when the first control line CL1 is enabled to control the first transistor Tc1 to be turned on, all the first transistors in the row of gain cells GU 1-GUn are turned on, the global bit line GBL corresponding to each column of ferroelectric memory cells MC in the memory cell sub-array subarray i is conducted with the local bit line LBL corresponding to the column of ferroelectric memory cells MC, so that a second voltage is output to other global bit lines GBL except the global bit line GBL1 in the first memory cell sub-array subarray i, the local bit line LBL except the local bit line LBL1 in the memory cell sub-array subarray i is charged to the second voltage, and data of non-target ferroelectric memory cells is prevented from being rewritten.

When writing data to the ferroelectric memory cell, the voltage difference between the first plate and the second plate (the difference between the first voltage and the second voltage) represents the stored data, and illustratively, when the first voltage is at a high level (e.g., the voltage is the actuation voltage VW) and the second voltage is at a low level (e.g., the voltage 0), the data written to the ferroelectric memory cell MC1 is indicated to be a first logic value, and when the first voltage is at a low level (e.g., the voltage is 0) and the second voltage is at a high level (e.g., the voltage is the actuation voltage VW), the data written to the ferroelectric memory cell MC1 is indicated to be a second logic value.

For convenience of explanation of the embodiments of the present application, in the embodiments of the present application, an example in which the differential pressure between the first plate and the second plate of the ferroelectric capacitor is positive represents that the stored data is a first logic value, and when the differential pressure between the first plate and the second plate of the ferroelectric capacitor is negative, the stored data is a second logic value, where the first voltage is a high level, for example, the excitation voltage VW; the second voltage is at a low level, for example, a voltage of 0, and the first logic value is opposite to the second logic value, for example, the first logic value represents data "1", and the second logic value represents data "0"; if the first logical value represents a data "0", then the second logical value represents a data "1".

Referring to fig. 13a and table 1a in combination with the ferroelectric memory shown in fig. 9a, table 1a shows a voltage state table of a write operation of the ferroelectric memory shown in fig. 9a, and fig. 13a shows a waveform diagram of the write operation of the ferroelectric memory shown in fig. 9a, it should be noted that VDD is greater than a threshold voltage for turning on channels of the access transistor and the first transistor, and VW is a voltage for turning over a polarization state of the ferroelectric capacitor.

TABLE 1a

	Standby	Write a first logic value	Write a second logic value
Select line WL	0	VDD	VDD
Unselected row WL	0	0	0
Select middle column PL	0	0	VW
Non-selected column PL	0	0	0
Select WBL of middle column	0	VW	0
Non-selected column WBL	0	0	VW
GBL	0	0	0
SL	0	0	0
CL1	0	VDD	VDD
CL2	0	0	0

In the standby state, 0 is output to all signal lines to reduce power consumption in the standby state.

If the ferroelectric memory cell MC1 in the memory cell sub-array subarray is subjected to the operation of writing the first logic value, outputting VDD to the word line WL1, and controlling the access transistor T of the ferroelectric memory cell MC1 to be turned on; VDD is output to the first control line CL1, the first transistor Tc1 of the control gain unit GU1 is turned on, VW is output to the write bit line WBL1, and 0 is output to the plate line PL1, at which time the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to VW and the second plate voltage is set to 0. And outputting 0 to write bit lines WBL 2-WBLn which are write bit lines except the write bit line WBL1 in the memory cell subarray so as to avoid overwriting data of the non-target ferroelectric memory cell. The other signal lines in the memory cell sub-array subarray all output 0 so as to reduce the power consumption to the greatest extent.

If the ferroelectric memory cell MC1 of the subarray of the memory cell subarray is written with the second logic value, VDD is output to the word line WL1, and the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on; VDD is output to the first control line CL1, the first transistor Tc1 of the control gain unit GU1 is turned on, 0 is output to the write bit line WBL1, VW is output to the plate line PL1, and at this time, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to 0 and the second plate voltage is set to VW. And (3) outputting VW to write bit lines WBL 2-WBLn which are write bit lines except the write bit line WBL1 in the memory cell subarray so as to avoid overwriting data of the non-target ferroelectric memory cell. The other signal lines in the memory cell sub-array subarray all output 0 so as to reduce the power consumption to the greatest extent.

In another possible embodiment, referring to fig. 13b and table 1b in combination with the ferroelectric memory shown in fig. 10a, table 1b shows a voltage state table of a write operation of the ferroelectric memory shown in fig. 10a, and fig. 13b shows a waveform schematic diagram of the write operation of the ferroelectric memory shown in fig. 10a.

TABLE 1b

	Standby	Write a first logic value	Write a second logic value
Select line WL	0	VDD	VDD
Unselected row WL	0	0	0
Select middle column PL	0	0	VW
Non-selected column PL	0	0	0
Select GBL of middle column	0	VW	0
Non-selected column GBL	0	0	VW
SL	0	0	0
CL1	0	VDD	VDD

If the first ferroelectric memory cell MC1 in the memory cell sub-array subarray is subjected to the operation of writing the first logic value, VDD is output to the word line WL1, and the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on; VDD is output to the first control line CL1, the first transistor Tc1 of the control gain unit GU1 is turned on, VW is output to the global bit line GBL1, and 0 is output to the plate line PL1, at which time the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to VW and the second plate voltage is set to 0. Outputting 0 to the global bit lines GBL 2-GBLn which are other global bit lines except the global bit line GBL1 in the subarray of memory cells, overwriting of data of non-target ferroelectric memory cells is avoided. The other signal lines in the memory cell sub-array subarray all output 0 so as to reduce the power consumption to the greatest extent.

If the ferroelectric memory cell MC1 of the subarray of the memory cell subarray is written with the second logic value, VDD is output to the word line WL1, and the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on; VDD is output to the first control line CL1, the first transistor Tc1 of the control gain unit GU1 is turned on, 0 is output to the global bit line GBL1, VW is output to the plate line PL1, and at this time, the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to 0 and the second plate voltage is set to VW. VW is output to global bit lines other than global bit line GBL1 in the memory cell sub-array subarray GBL2 to global bit line GBLn, overwriting of data of non-target ferroelectric memory cells is avoided. The other signal lines in the memory cell sub-array subarray all output 0 so as to reduce the power consumption to the greatest extent.

The data writing method of the ferroelectric memory is described in the above embodiment, and the embodiment of the application further provides a data reading method, based on which the data stored in the ferroelectric memory provided in the embodiment of the application can be read, and the data reading method provided in the embodiment of the application is described below with reference to the accompanying drawings. In the data writing stage, the ferroelectric capacitor of the ferroelectric memory unit is set to a preset polarization state, the first polar plate and the second polar plate of the ferroelectric capacitor of the ferroelectric memory unit are set to a preset voltage difference, when the voltage difference between the first polar plate and the second polar plate of the ferroelectric capacitor is positive, the data stored in the ferroelectric memory unit is a first logic value, and when the voltage difference between the first polar plate and the second polar plate of the ferroelectric capacitor is negative, the data stored in the ferroelectric memory unit is a second logic value. In the reading stage, an electric field is applied to the ferroelectric capacitor of the ferroelectric memory cell, the quantity of ferroelectric inversion charge generated by the ferroelectric capacitor of the ferroelectric memory cell is converted into a reading voltage on the global bit line, and data stored in the ferroelectric memory cell is determined according to the reading voltage. The reading operation of the ferroelectric memory comprises a pre-charging stage and a reading stage, wherein the pre-charging stage is used for pre-charging each terminal of the amplifying transistor to a preset voltage state, and the turning charge generated by the ferroelectric memory unit in the reading stage controls the amplifying transistor to be turned on or off, and then the reading voltage is detected on the global bit line, so that the ferroelectric turning charge of the target ferroelectric memory unit can be converted to the global bit line for reading.

For convenience of explanation, the embodiment of the present application will be described taking the ferroelectric memory cell MC1 in the memory cell sub-array subarray as the target ferroelectric memory cell for reading data. The row in which the target ferroelectric memory cell is located is called a selected row, the row in which the non-target ferroelectric memory cell is located is called a non-selected row, the column in which the target ferroelectric memory cell is located is called a selected column, and the column in which the non-target ferroelectric memory cell is located is called a non-selected column. As illustrated in fig. 14, the data reading method includes:

s310: the first terminal of the amplifying transistor is precharged to a first level different from a source line voltage, which is a second level.

S320: an actuation voltage is applied to the target ferroelectric memory cell.

S330: the data stored in the read target ferroelectric memory cell is determined according to the read voltage on the global bit line.

Taking the ferroelectric memory cell MC1 as an example, in connection with the ferroelectric memory shown in fig. 8, the first terminal of the amplifying transistor Tg1 of the gain unit GU1 is connected to the global bit line GBL1, the second terminal of the amplifying transistor Tg1 is connected to the source line SL1, the source line SL1 is at a second level, the first terminal of the amplifying transistor Tg1 is precharged to a first level different from the voltage of the source line SL1, the first terminal of the amplifying transistor Tg1 is suspended, for example, the second level is at a low level (for example, the voltage is 0), and the first level is at a high level (for example, the voltage is VDD); or the second level is a high level (e.g., voltage VDD), the first level is a low level (e.g., voltage 0), and preferably, the second level is set to a low level (e.g., voltage 0) in order to reduce power consumption.

After the precharge is completed, the voltages at the first and second terminals of the amplifying transistor Tg1 are in two different states, the driving voltage VW is applied to the ferroelectric memory cell MC1, and the ferroelectric memory cell MC1 generates a flipped charge, which is distributed to the local bit line LBL1 through the access transistor T, and a voltage is accumulated on the local bit line LBL 1. For example, the access transistor T of the ferroelectric memory cell MC1 is turned on, the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1, the ferroelectric capacitor C generates a flipped charge, the flipped charge is distributed to the local bit line LBL1 through the access transistor T, a voltage is accumulated on the local bit line LBL1, if the flipped charge is large, the voltage of the local bit line LBL1 rises beyond the turn-on threshold of the amplifying transistor Tg1, the amplifying transistor Tg1 is turned on, the global bit line GBL1 is turned on with the source line SL1, and the voltage on the global bit line GBL1 becomes the second level. If the flipped charge is less, the voltage of the local bit line LBL1 is lower, the amplifying transistor Tg1 is in an off state, and the voltage on the global bit line GBL1 is the voltage at the first end of the amplifying transistor Tg1 and is a fourth level, where the fourth level is the difference between the first level and the leakage amount (Δv) of the amplifying transistor Tg1 in the off state.

Determining the data stored by the read target ferroelectric memory cell based on the read voltage on the global bit line, illustratively, determining the data stored by the read target ferroelectric memory cell based on the read voltage on the global bit line includes: when the read voltage on the global bit line is the same as the voltage of the source line to be the second level, determining that the data stored in the target ferroelectric memory cell is the first logic value; and when the read voltage on the global bit line is the fourth level, determining that the data stored in the target ferroelectric memory cell is the second logic value.

In the reading process, the first end of the amplifying transistor Tg1 is precharged to a first level, a second level is output to the source line SL1, the voltage of the first level is different from the voltage of the second level, then the conduction state of the amplifying transistor Tg1 is controlled according to the quantity of the flipped charge of the ferroelectric capacitor C1 of the ferroelectric memory cell MC1, then the read data is determined according to the read voltage on the global bit line GBL1, the conduction state of the amplifying transistor Tg1 is different, the read voltage on the global bit line GBL1 is different, and thus different data are read, in order to reduce the influence of factors other than the flipped charge on the conduction state of the amplifying transistor Tg1, in the precharge stage, the control end of the amplifying transistor Tg1 needs to be precharged, referring to fig. 15, before S310, the data reading method further includes;

s301: the control end of the amplifying transistor is pre-charged to the third level, and when the control end of the amplifying transistor is at the third level, the amplifying transistor is in an off state.

Illustratively, in one possible implementation, taking the ferroelectric memory shown in fig. 9a as an example, the ferroelectric memory cell MC1 is taken as a target ferroelectric memory cell, where the gain cell GU1 includes a first transistor Tc1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the write bit line WBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1. In this case, when the control terminal of the amplifying transistor Tg1 is precharged, referring to fig. 15a, s301 can be implemented as follows:

S301a: the first transistor is controlled to be turned on, a third level is output to the write bit line, the control end of the amplifying transistor is precharged to the third level, and when the control end of the amplifying transistor is at the third level, the amplifying transistor is in an off state.

The write bit line WBL1 is connected to the local bit line LBL1 through the first transistor Tc1, and the control terminal of the amplifying transistor Tg1 is connected to the local bit line LBL1, and when the first transistor Tc1 is turned on, a third level is output to the write bit line WBL1, and the control terminal of the amplifying transistor Tg1 is precharged to the third level, wherein when the control terminal of the amplifying transistor Tg1 is the third level, the amplifying transistor Tg1 is in an off state, for example, in the embodiment of the application, the amplifying transistor Tg1 is an N-type transistor, the third level is a low level, for example, the voltage of the third level is 0, the amplifying transistor Tg1 may also be a P-type transistor, and the third level is a high level.

After the control end of the amplifying transistor Tg1 is precharged to the third level, the first transistor Tc1 is controlled to be turned off, the control end of the amplifying transistor Tg1 is suspended, and the control end of the amplifying transistor Tg1 is kept at the third level.

In another possible implementation, in conjunction with the ferroelectric memory shown in fig. 10a, the gain unit GU1 includes a first transistor Tc1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the global bit line GBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1. In this case, referring to fig. 15b, s301 can be implemented as follows when the control terminal of the amplifying transistor Tg1 is precharged:

S301b: and controlling the first transistor to be on, outputting a third level to the global bit line, pre-charging the control end of the amplifying transistor to the third level, and when the control end of the amplifying transistor is at the third level, enabling the amplifying transistor to be in an off state.

The first transistor Tc1 is turned on, the global bit line GBL1 is communicated with the local bit line LBL1 through the first transistor Tc1, a third level is output to the global bit line GBL1, the global bit line GBL1 precharges the control terminal of the amplifying transistor Tg1 to the third level through the first transistor Tc1 and the local bit line LBL1, and when the control terminal of the amplifying transistor Tg1 is at the third level, the amplifying transistor Tg1 is in an off state.

In a possible implementation, in connection with the ferroelectric memory shown in fig. 9a, the gain unit GU includes a second transistor Tr1, the control terminal of the second transistor Tr1 is connected to the second control line CL2, the first terminal of the second transistor Tr1 is connected to the write bit line WBL1, and the second terminal of the second transistor Tr1 is connected to the global bit line GBL1, S310 is described in connection with the first embodiment of S301, in which case, as shown in fig. 16a, S310 may be implemented as follows:

s310a: the second transistor is controlled to be turned on, a first level different from a source line voltage is output to the write bit line, and the first end of the amplifying transistor is precharged to the first level, wherein the source line voltage is a second level.

The voltage of the source line SL1 is different from the voltage of the second level. The write bit line WBL1 is connected to the global bit line GBL1 through the second transistor Tr1, the first terminal of the amplifying transistor Tg1 is connected to the global bit line GBL1, the first level is output to the write bit line WBL1, the global bit line GBL1 is pulled up to the first level, and the first terminal voltage of the amplifying transistor Tg1 is precharged to the first level.

After the voltage at the first end of the amplifying transistor Tg1 is pre-charged to the first level, the second transistor Tr1 is controlled to be turned off, and the first end of the amplifying transistor Tg1 is suspended to maintain the state of the first level.

In another possible implementation, S310 is described in connection with the second embodiment of S301 above in connection with the ferroelectric memory shown in fig. 10a, where the first terminal of the amplifying transistor Tg1 is connected to the global bit line GBL1, as in fig. 16b, in which case S310 may be implemented as follows:

S310b: the first level is output to the global bit line, and the first end of the amplifying transistor is precharged to a first level different from the source line voltage, which is a second level.

After the first end of the amplifying transistor Tg1 is precharged to the first level, the output of the signal to the global bit line GBL1 is stopped, the first end of the amplifying transistor Tg1 is suspended, and the state of the first level is maintained.

After the control end and the first end of the amplifying transistor Tg1 are precharged, the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on, the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1, and then the data stored in the ferroelectric memory cell MC1 is determined according to the read voltage on the global bit line GBL1.

Since the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C during the reading process, if the voltage of the second plate of the ferroelectric capacitor C is different from the excitation voltage, the difference refers to that the voltage state of the second plate is different from the excitation voltage VW, for example, the excitation voltage is high, and the second plate of the ferroelectric capacitor C is low, as in the foregoing embodiment, for example, the data stored in the ferroelectric memory cell MC is a first logic value, the first plate of the ferroelectric capacitor C is a first voltage (high level), and the second plate of the ferroelectric capacitor C is a second voltage (low level), in which case, the application of the excitation voltage to the second plate of the ferroelectric capacitor C rewrites the voltage of the second plate to a high level, resulting in that the data stored in the ferroelectric memory cell is rewritten to a second logic value from the first logic value, therefore, during the reading process, if the data read to be the first logic value, the data stored in the ferroelectric memory cell is rewritten to the second logic value, and therefore the data read back in the ferroelectric memory cell is rewritten to the first logic value, and the data read back, and the data read method further includes the following fig. 17:

and S340, when the data stored in the read target ferroelectric memory cell is determined to be the first logic value, writing back the first logic value to the target ferroelectric memory cell.

In the embodiment of the present application, the first logic value represents that the voltage difference between the first plate and the second plate of the ferroelectric capacitor is positive, that is, the first voltage is high level, and the second voltage is low level, so that after the exciting voltage VW is applied to the second plate of the ferroelectric capacitor of the ferroelectric memory cell MC1, the data stored in the ferroelectric memory cell MC1 is rewritten into the second logic value, and the first logic value is rewritten into the ferroelectric memory cell MC1, that is, the ferroelectric memory cell MC1 is rewritten, so that the ferroelectric capacitor reaches the state that the first plate is high level, and the second plate is low level. The method of writing to the ferroelectric memory cell has been described in detail in the foregoing embodiments, and will not be described in detail herein, but reference is made to the details of the data writing portion of the ferroelectric memory cell in the foregoing embodiments.

By way of example, in one possible implementation, referring to fig. 17a in combination with the ferroelectric memory shown in fig. 9a, S340 includes the following sub-steps:

S341: the access transistor of the control target ferroelectric memory cell is turned on.

S342a: the first transistor is controlled to be conducted, and a high-level signal is output to a write bit line corresponding to the target ferroelectric memory cell.

S343: a low level signal is output to the plate line to which the target ferroelectric memory cell is connected.

S344a: and outputting a low-level signal to a write bit line except the write bit line corresponding to the target ferroelectric memory cell in the memory cell subarray.

In another possible implementation, referring to fig. 17b in conjunction with the ferroelectric memory shown in fig. 10a, s340 includes the following sub-steps:

S342b: the first transistor is controlled to be conducted, and a high-level signal is output to the global bit line corresponding to the target ferroelectric memory cell.

S344b: and outputting a low-level signal to a global bit line except the global bit line corresponding to the target ferroelectric memory cell in the memory cell subarray.

Note that, since the access transistors T of the ferroelectric memory cell MC1 are controlled to be turned on by the word line WL1 during the read process, the access transistors of all the ferroelectric memory cells in the row where the ferroelectric memory cell MC1 is located are controlled to be turned on; when the excitation voltage VW is applied to the ferroelectric capacitors C of the ferroelectric memory cells MC1 through the plate line PL1, the excitation voltage VW is applied to the ferroelectric capacitors of all the ferroelectric memory cells of the row in which the ferroelectric memory cells MC1 are located, and thus, when reading the ferroelectric memory provided in the embodiment of the present application, reading is performed in units of rows, and data stored in one row of ferroelectric memory cells can be read in one reading operation.

Referring to fig. 9a, 16a, 18a and table 2a, fig. 18a shows a schematic waveform diagram of a read operation of the ferroelectric memory shown in fig. 9a, and table 2a shows a voltage state table of a read operation of the ferroelectric memory shown in fig. 9a, taking reading of the ferroelectric memory cell MC1 in fig. 9a as an example, the data reading method provided in the embodiment of the present application is illustrated. Wherein VDD is greater than a threshold voltage for turning on channels of the access transistor, the first transistor, and the second transistor, and VW represents a voltage that can invert a polarization state of the ferroelectric capacitor.

TABLE 2a

When the ferroelectric memory cell MC1 is read, the precharge is performed first, and the precharge is performed in two stages, the first stage precharges the control terminal of the amplifying transistor Tg1 and the second stage precharges the first terminal of the amplifying transistor Tg 1. First, VDD is output to the word line WL1 and the first control line CL1, the access transistor T and the first transistor Tc1 are turned on, and a third level (as shown in fig. 18a and table 2a, the third level voltage may be 0) is output to the write bit line WBL1, and to ensure that the information stored in the ferroelectric capacitor is unchanged, 0 is output to the plate line PL 1. In order to reduce power consumption, a signal with a voltage of 0 is output to each of the other lines, then a signal with a voltage of 0 is output to the first control line CL1 and the word line WL1, the control terminal of the amplifying transistor Tg1 is suspended, and at this time, the voltage of the control terminal of the amplifying transistor Tg1 is 0. Then, VDD is output to the second control line CL2, the second transistor Tr1 is controlled to be turned on, a first level (as shown in fig. 18a and table 2a, the first level may be VDD) is output to the write bit line WBL1, the first terminal of the amplifying transistor Tg1 is precharged to VDD, then the first control line CL1 is set to 0, the second terminal of the amplifying transistor Tg1 is suspended, and at this time, the second terminal of the amplifying transistor Tg1 is VDD, and the precharge phase is completed.

After the precharge phase is completed, reading is performed, the word line WL1 is set to VDD, the source line SL1 is set to a second level (as shown in fig. 17 and table 2, the voltage of the second level may be 0), the excitation voltage VW is output to the plate line PL1 to generate the inversion charge on the ferroelectric capacitor C, the other word lines, such as the word lines WL2 to WLn, are set to 0, and the other plate lines, such as the plate lines PL2 to PLn, are set to 0. Detecting a read voltage on the global bit line GBL1, if the read voltage on the global bit line GBL1 is at a second level (the voltage is 0), which indicates that the amplifying transistor Tg1 is in a conductive state, and more flipped charges are generated by the ferroelectric capacitor C, the read data is at a first logic value. If the read voltage on the global bit line GBL1 is at a fourth level, for example, VDD- Δv, that is, the difference between the first level and the amount of leakage, which indicates that the amplifying transistor Tg1 is in an off state, and the ferroelectric capacitor C generates less flipped charges, the read voltage is at the second logic value.

After reading the first logic value, the ferroelectric memory cell MC1 read to the first logic value needs to be written back, where the writing back step is the same as the writing method in the foregoing embodiment, for example, if the data read by the ferroelectric memory cell MC1 is the first logic value, the first logic value is written back to the ferroelectric memory cell MC1, VDD is output to the word line WL1, the access transistor T of the ferroelectric memory cell MC1 is controlled to be turned on, VDD is output to the first control line CL1, the first transistor Tc1 is controlled to be turned on, then VW is output to the global bit line GBL, and the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to VW; the first logic value is written back to the ferroelectric memory cell MC1 by outputting 0 to the plate line PL1 and setting the second plate of the ferroelectric capacitor C to 0, and outputting 0 to other global bit lines such as the global bit line GBL2 to the global bit line GBLn, thereby preventing the data of other ferroelectric memory cells from being rewritten.

In another possible implementation manner, in conjunction with fig. 10a, 16b, 18b and table 2b, fig. 18b shows a schematic waveform diagram of a read operation of the ferroelectric memory shown in fig. 10a, and table 2b shows a voltage state table of a read operation of the ferroelectric memory shown in fig. 10a, taking as an example the reading of the ferroelectric memory cell MC1 in fig. 10a, the data reading method provided by the embodiment of the present application is illustrated.

TABLE 2b

When the ferroelectric memory cell MC1 is read, the precharge is performed first, and the precharge is performed in two stages, the first stage precharges the control terminal of the amplifying transistor Tg1 and the second stage precharges the first terminal of the amplifying transistor Tg 1.

First, VDD is output to the first control line CL1, the first transistor Tc1 is controlled to be turned on, a third level (for example, the third level voltage may be 0 as shown in fig. 18b and table 2 b) is output to the global bit line GBL1, and in order to ensure that the information stored in the ferroelectric capacitor is unchanged, VDD may be output to the word line WL1, and 0 may be output to the plate line PL1, so that the voltages of the ferroelectric memory cell MC1 and the first and second plates of all the ferroelectric memory cells in the row are all 0, and there is no voltage difference between the first and second plates, so that the data stored in the ferroelectric memory cell will not be rewritten. In order to reduce power consumption, 0 is output to other lines, after the control end of the amplifying transistor Tg1 is precharged to a third level, 0 is output to the first control line CL1 and the word line WL1, the control end of the amplifying transistor Tg1 is suspended, and at this time, the voltage of the control end of the amplifying transistor Tg1 is at the third level, and the amplifying transistor Tg1 is in an off state.

Then, a first level (for example, the first level may be VDD as shown in fig. 18b and table 2 b) is output to the global bit line GBL1, the first terminal of the amplifying transistor Tg1 is precharged to VDD, then, the output of the signal to the global bit line GBL1 is stopped, the first terminal of the amplifying transistor Tg1 is suspended, and at this time, the first terminal of the amplifying transistor Tg1 is VDD, and the precharge phase is completed.

After the precharge phase is completed, the read is performed, the word line WL1 is set to VDD, the source line SL1 is set to a second level (for example, the second level voltage may be 0 as shown in fig. 18b and table 2 b), the driving voltage VW is output to the plate line PL1 to generate the inversion charge on the ferroelectric capacitor C, the other word lines, for example, the word lines WL2 to WLn are set to 0, and the other plate lines, for example, the plate lines PL2 to PLn are set to 0.

Detecting the read voltage on the global bit line GBL1, if the read voltage on the global bit line GBL1 is at a second level (for example, the second level voltage may be 0 as shown in fig. 18b and table 2 b), which indicates that the amplifying transistor Tg1 is in a conductive state, and the ferroelectric capacitor C generates more flipped charges, the read data is at the first logic value. If the read voltage on the global bit line GBL1 is at a fourth level, for example, VDD- Δv, that is, the difference between the first level and the amount of leakage, which indicates that the amplifying transistor Tg1 is in an off state, and the ferroelectric capacitor C generates less flipped charges, the read voltage is at the second logic value. After reading the first logic value, the ferroelectric memory cell MC1 read to the first logic value needs to be written back, where the writing back step is the same as the writing method in the foregoing embodiment, for example, if the data read by the ferroelectric memory cell MC1 is the first logic value, the first logic value is written back to the ferroelectric memory cell MC1, VDD is output to the word line WL1, the access transistor of the ferroelectric memory cell MC1 is controlled to be turned on, VDD is output to the first control line CL1, the first transistor Tc1 is controlled to be turned on, then VW is output to the global bit line GBL, and the first plate of the ferroelectric capacitor C of the ferroelectric memory cell MC1 is set to VW; the first logic value is rewritten to the ferroelectric memory cell MC1 by outputting 0 to the plate line PL1 and setting the second plate of the ferroelectric capacitor C to 0, and the 0 is outputted to the other global bit lines such as the global bit lines GBL2 to GBLn, thereby preventing the data of the other ferroelectric memory cells from being rewritten.

The foregoing description of the solution provided by the embodiments of the present application has been presented mainly in terms of method steps. It is understood that the computer, in order to implement the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as a combination of hardware and computer software. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can also divide the functional modules of the data reading device according to the method example, for example, each functional module can be divided corresponding to each function, or two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation. In the case of dividing the respective functional modules with the respective functions, fig. 19 shows a data read/write apparatus 400, which may be a chip, for performing the above data read method and data write method. The data read/write apparatus 400 includes:

The pre-charging unit 401 is configured to pre-charge a first end of the amplifying transistor to a first level different from a source line voltage, wherein the source line voltage is a second level. For example, in connection with fig. 14, a precharge unit may be used to perform S310.

A read control unit 402 for applying an actuation voltage VW to the target ferroelectric memory cell, e.g. in connection with fig. 14, the read control unit may be used to perform S320.

The read control unit 402 is further configured to determine data stored in the read target ferroelectric memory cell according to the read voltage on the global bit line, for example, when the read voltage is at the second level, the read control unit 402 is configured to determine that the logic value stored in the read target ferroelectric memory cell is the first logic value; the read control unit 402 is further configured to determine that the logic value stored in the read target ferroelectric memory cell is the second logic value when the read voltage is at a fourth level, where the fourth level is a difference between the first level and the leakage amount of the amplifying transistor in the off state. For example, in connection with fig. 14, the read control unit may be used to perform S330.

Optionally, the pre-charging unit 401 is further configured to pre-charge the control terminal of the amplifying transistor to a third level, and when the control terminal of the amplifying transistor is at the third level, the amplifying transistor is in an off state. For example, in connection with fig. 15, a read control unit may be used to perform S301.

Optionally, referring to fig. 9a, the gain unit GU1 includes a first transistor Tc1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the write bit line WBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1.

The pre-charge unit 401 is further configured to control the first transistor to be turned on, output a third level to the write bit line, pre-charge the control terminal of the amplifying transistor to the third level, and when the control terminal of the amplifying transistor is at the third level, the amplifying transistor is in an off state, for example, in conjunction with fig. 15a, the pre-charge unit 401 may be configured to perform S301a.

Alternatively, in another possible implementation manner, in connection with fig. 10a, the gain unit GU1 includes a first transistor Tc1, a control terminal of the first transistor Tc1 is connected to the first control line CL1, a first terminal of the first transistor Tc1 is connected to the global bit line GBL1, and a second terminal of the first transistor Tc1 is connected to the local bit line LBL1.

The pre-charging unit 401 is further configured to control the first transistor to be turned on, output a third level to the global bit line, pre-charge the control terminal of the amplifying transistor to the third level, and when the control terminal of the amplifying transistor is at the third level, the amplifying transistor is in an off state, for example, in conjunction with fig. 15b, the pre-charging unit 401 may be configured to perform S301b.

Optionally, with continued reference to fig. 9a, the gain unit GU1 includes a second transistor Tr1, a control terminal of the second transistor Tr1 is connected to the second control line CL2, a first terminal of the second transistor Tr1 is connected to the write bit line WBL1, and a second terminal of the second transistor Tr1 is connected to the global bit line GBL1.

Optionally, the pre-charging unit 401 is further configured to control the second transistor to be turned on, output a first level different from the source line voltage to the write bit line, and pre-charge the first terminal of the amplifying transistor to the first level, wherein the source line voltage is the second level. For example, in connection with fig. 16a, the pre-charge unit 401 may be used to perform S310a.

Alternatively, in another possible implementation, in conjunction with fig. 10a, the first terminal of the amplifying transistor Tg1 is connected to the global bit line GBL 1.

The precharge unit 401 is further configured to output a first level to the global bit line, precharge the first terminal of the amplifying transistor to a first level different from a source line voltage, wherein the source line voltage is a second level. For example, in connection with fig. 16b, the pre-charge unit 401 may be used to perform S310b.

Optionally, the data read/write apparatus 400 further includes a write control unit 403, where the write control unit 403 is configured to write back the first logic value to the target ferroelectric memory cell when it is determined that the data stored in the read target ferroelectric memory cell is the first logic value, for example, in conjunction with fig. 16, the read control unit may be configured to execute S340.

Optionally, in combination with fig. 9a, the write control unit 403 is configured to control the access transistor of the target ferroelectric memory cell to be turned on, control the first transistor corresponding to the target ferroelectric memory cell to be turned on, output a high level signal to the write bit line corresponding to the target ferroelectric memory cell, output a low level signal to the plate line connected to the target ferroelectric memory cell, and output a low level signal to the write bit line other than the write bit line corresponding to the target ferroelectric memory cell in the memory cell sub-array, so as to write back the first logic value to the target ferroelectric memory cell, for example, in combination with fig. 17a, the write control unit 403 is configured to perform S341, S342a, S343, and S344a.

Optionally, in combination with fig. 10a, the write control unit 403 is further configured to control the access transistor of the target ferroelectric memory cell to be turned on, control the first transistor corresponding to the target ferroelectric memory cell to be turned on, output a high level signal to the global bit line corresponding to the target ferroelectric memory cell, output a low level signal to the plate line connected to the target ferroelectric memory cell, and output a low level signal to the global bit line other than the global bit line corresponding to the target ferroelectric memory cell in the memory cell sub-array to write back the first logic value to the target ferroelectric memory cell, for example, in combination with fig. 17b, the write control unit 403 is further configured to perform S341, S342b, S343, S344b.

Optionally, the write control unit 403 is further configured to control the access transistor of the target ferroelectric memory cell to be turned on, charge the local bit line connected to the target ferroelectric memory cell to a first voltage, and output a second voltage to the plate line connected to the target ferroelectric memory cell, where the second voltage is different from the first voltage, and charge the local bit line other than the local bit line connected to the target ferroelectric memory cell in the memory cell sub-array to the second voltage to write data into the ferroelectric memory cell. When the first voltage is at a high level and the second voltage is at a low level, writing a first logic value; when the first voltage is at a low level and the second voltage is at a high level, a second logic value is written, for example, in conjunction with fig. 11, the writing control unit 403 is further configured to execute S210 to S240.

Based on this, the embodiment of the application also provides an electronic device, which comprises a printed circuit board (print circuit board, PCB) and the ferroelectric memory provided in the above embodiment, wherein the ferroelectric memory is connected with the circuit board. Optionally, the electronic device is a user device or a terminal device of different types such as a computer system, a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device and the like; the electronic device may also be a network device such as a base station. It should be noted that, for the description of the ferroelectric memory in the electronic device, reference may be specifically made to the description of the memory in the above embodiment, and the embodiments of the present application are not repeated herein.

The steps of a method or algorithm described in connection with the present disclosure may be embodied in hardware, or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, erasable programmable read-only memory (erasable programmable ROM, EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Finally, it should be noted that: the foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A ferroelectric memory comprising one or more subarrays of memory cells, each subarray of memory cells comprising a row of gain cells and an array of distributed ferroelectric memory cells;

the ferroelectric memory cells in the same column are electrically connected with the same local bit line, the ferroelectric memory cells in the same row are electrically connected with the same word line, and the ferroelectric memory cells in the same row are also electrically connected with the same plate line; the ferroelectric memory cells in the same column are correspondingly provided with a gain unit, the gain unit comprises an amplifying transistor, the control end of the amplifying transistor is electrically connected with the local bit line connected with the ferroelectric memory cells in the column, the first end of the amplifying transistor is electrically connected with a global bit line, and the second end of the amplifying transistor is connected with a source line.
The ferroelectric memory according to claim 1, wherein the gain cell further comprises a first transistor, a control terminal of the first transistor being connected to a first control line, a first terminal of the first transistor being electrically connected to a write bit line, a second terminal of the first transistor being electrically connected to the local bit line to which a control terminal of the amplifying transistor is connected.
The ferroelectric memory according to claim 2, wherein the gain cell further comprises a second transistor, a control terminal of the second transistor being electrically connected to a second control line, a first terminal of the second transistor being electrically connected to the write bit line, a second terminal of the second transistor being electrically connected to the global bit line to which the first terminal of the amplifying transistor is connected.
The ferroelectric memory of claim 3, wherein in said memory cell sub-array; the control ends of the first transistors of the gain units positioned in the same row are connected with the same first control line; the control ends of the second transistors of the gain units positioned in the same row are connected with the same second control line.
The ferroelectric memory of claim 3, wherein said ferroelectric memory comprises a plurality of memory cell sub-arrays, among which; the first ends of the amplifying transistors of the gain units positioned in the same column are electrically connected with the same global bit line; the second ends of the amplifying transistors of the gain units positioned in the same column are electrically connected with the same source line; a first end of the first transistor of the gain unit positioned in the same column is connected with the same writing bit line; the first ends of the second transistors of the gain units positioned in the same column are connected with the same writing bit line; the second ends of the second transistors of the gain units located in the same column are connected with the same global bit line.
The ferroelectric memory according to claim 1, wherein the gain cell further comprises a first transistor, a control terminal of the first transistor being electrically connected to a first control line, a first terminal of the first transistor being electrically connected to the global bit line to which the first terminal of the amplifying transistor is connected, a second terminal of the first transistor being electrically connected to the local bit line to which the control terminal of the amplifying transistor is connected.
The ferroelectric memory according to claim 6, wherein control terminals of the first transistors of the gain cells located in the same row are electrically connected to the same first control line in the memory cell sub-array.
The ferroelectric memory according to claim 7, wherein the ferroelectric memory comprises a plurality of memory cell sub-arrays in which first ends of the amplifying transistors of the gain cells located in the same column are electrically connected to the same global bit line; the second ends of the amplifying transistors of the gain units positioned in the same column are electrically connected with the same source line; the first ends of the first transistors of the gain cells located in the same column are electrically connected to the same global bit line.
The ferroelectric memory according to any one of claims 1 to 8, wherein the ferroelectric memory cell comprises an access transistor and a ferroelectric capacitor, a control terminal of the access transistor being electrically connected to the word line; the first end of the access transistor is electrically connected with the local bit line, the second end of the access transistor is electrically connected with the first polar plate of the ferroelectric capacitor, and the second polar plate of the ferroelectric capacitor is electrically connected with the plate line.
A data reading method applied to the ferroelectric memory according to any one of claims 1 to 9, characterized in that the method comprises:

Pre-charging a first end of the amplifying transistor to a first level different from the source line voltage, wherein the source line voltage is a second level;

applying an actuation voltage to the target ferroelectric memory cell;

And determining the data stored in the read target ferroelectric memory cell according to the read voltage on the global bit line.
The data reading method of claim 10, wherein prior to determining the data stored by the read target ferroelectric memory cell according to the read voltage on the global bit line, the method further comprises:

and pre-charging the control end of the amplifying transistor to a third level, and when the control end of the amplifying transistor is at the third level, the amplifying transistor is in an off state.
The data reading method of claim 11, wherein the gain cell further comprises a first transistor, a control terminal of the first transistor is connected to a first control line, a first terminal of the first transistor is connected to a write bit line, a second terminal of the first transistor is connected to the local bit line to which a control terminal of the amplifying transistor is connected, and precharging the control terminal of the amplifying transistor to a third level comprises:

And controlling the first transistor to be conducted, outputting a third level to the write bit line, and precharging the control end of the amplifying transistor to the third level.
The data reading method of claim 12, wherein the gain cell further comprises a second transistor, a control terminal of the second transistor is connected to a first control line, a first terminal of the second transistor is connected to a write bit line, a second terminal of the second transistor is connected to the global bit line to which the first terminal of the amplifying transistor is connected, and the precharging the first terminal of the amplifying transistor to a first level different from the source line voltage comprises:

and controlling the second transistor to be conducted, and outputting a first level different from the source line voltage to the write bit line.
The data reading method of claim 11, wherein the gain cell comprises a first transistor, a control terminal of the first transistor is connected to the first control line, a first terminal of the first transistor is connected to the global bit line to which a first terminal of the amplifying transistor is connected, a second terminal of the first transistor is connected to the local bit line to which a control terminal of the amplifying transistor is connected, and the precharging the control terminal of the amplifying transistor to the third level comprises:

And controlling the first transistor to be conducted, and outputting a third level to the global bit line.
The method of claim 14, wherein precharging the first terminal of the amplifying transistor to a first level different from the source line voltage comprises:

a first level is output to the global bit line, and a first terminal of the amplifying transistor is precharged to a first level different from the source line voltage.
The method according to any one of claims 10 to 15, wherein the determining the data stored in the target ferroelectric memory cell to be read according to the read voltage on the global bit line includes:

When the read voltage is at the second level, determining that the data stored in the read target ferroelectric memory cell is at a first logic value;

And when the read voltage is a fourth level, determining that the data stored in the read target ferroelectric memory cell is a second logic value, wherein the fourth level is a difference value between the first level and the drain quantity of the amplifying transistor in an off state.
The method of claim 16, wherein if it is determined that the read target ferroelectric memory cell stores a logic value that is a first logic value, the method further comprises:

And writing back a first logic value to the target ferroelectric memory cell.
An electronic device, characterized in that the electronic device comprises a circuit board and a ferroelectric memory electrically connected to the circuit board, wherein the ferroelectric memory is a ferroelectric memory according to any one of claims 1 to 9.