CN117915030A - Video stream processing method, device and storage medium based on CML video interface - Google Patents

Abstract

The invention discloses a video stream processing method and device based on a CML video interface and a storage medium, and belongs to the technical field of video storage. The method comprises the following steps: initializing a system; starting a CML video stream data processing module, controlling the input and output of video stream data of a CML encoding and decoding chip according to a working mode, performing frame decoding structure processing and image frame integrity processing on the input video stream data, performing frame adding structure processing and output frame rate control on the output video stream data, and controlling the read-write operation of the video stream data in the DDR cache module; and respectively establishing a CML video stream data storage thread and a CML video stream data export thread, wherein the CML video stream data export thread is used for realizing two functions of downloading and simulation output according to the instruction. Fills the blank of the integration of the storage, downloading and simulation output functions in the existing CML video stream application field, and realizes the function of performing CML video stream simulation output by using stored video stream data under the condition of no CML video stream source.

Description

Video stream processing method, device and storage medium based on CML video interface

Technical Field

The present invention relates to the field of video storage technologies, and in particular, to a video stream processing method and apparatus based on a CML video interface, and a storage medium.

Background

With the development of electronic technology, video streams based on CML interfaces are widely used, so that the demands on devices such as storage and output of CML video streams are increasing. In the existing CML video stream application field, the functions of the related devices of the CML video stream are single, and an integrated method and an integrated device for the storage, downloading and simulation output functions of the CML video stream do not exist yet.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a video stream processing method, a device and a storage medium based on a CML video interface.

The aim of the invention is realized by the following technical scheme: the first aspect of the present invention provides: a video stream processing method based on a CML video interface is characterized in that: the method comprises the following steps:

S1: the initialization hardware module comprises a main control module, a CML video stream interface module, a SATA disk storage module and a key indicator module;

S2: initializing each on-board chip and interfaces, wherein the chips comprise DDR chips, USB3.0 chips and CML encoding and decoding chips, and the interfaces comprise BRAM interfaces, CML parallel digital interfaces, SATA disk read-write interfaces, USB3.0 interfaces and I/O interfaces;

s3: starting a DDR cache module, and carrying out partition cache processing on SATA storage data and SATA export data;

S4: starting a CML video stream data processing module, controlling the input and output of video stream data of a CML encoding and decoding chip according to a working mode, performing frame decoding structure processing and image frame integrity processing on the input video stream data, performing frame adding structure processing and output frame rate control on the output video stream data, and controlling the read-write operation of the video stream data in the DDR cache module;

S5: starting a SATA read-write management module, according to a command issued by a PS end of a main control module, reading and writing data on the SATA disk, formatting the data, and returning to SATA disk state operation;

S6: starting a USB3.0 read-write management module, and dividing USB3.0 data read-write into an instruction frame data channel and a video stream data channel according to the difference of data magnitudes;

S7: based on S3-S6, respectively establishing a CML video stream data storage thread and a CML video stream data export thread, wherein the CML video stream data export thread is used for realizing two functions of downloading and simulation output according to instructions;

s8: a cyclic scanning key input instruction and an upper computer input instruction, and triggering a CML video stream data storage thread in S7 if a storage instruction is received; and if a downloading or simulation instruction is received, triggering the CML video stream data export thread in S7.

Preferably, the step S3 further includes the following steps: distributing a write buffer area FIFO and three data buffer areas in the DDR buffer module for circular buffer storage, and providing a SATA storage buffer storage function and a SATA export buffer storage function; the SATA storage and caching function is as follows: triggering write DDR operation when the data quantity of the write cache area FIFO exceeds 32KB data; when the read DDR data is sent into the SATA write data buffer interval, the data quantity of one packet of SATA write is 512KB each time, the corresponding operation is performed on the read DDR buffer module for 16 times, the read DDR operation is started when the number of read and write packets is unequal, and the write DDR operation is performed simultaneously;

the SATA exports the cache function and is: when receiving SATA read data, triggering write DDR operation when the data quantity of the write buffer area FIFO exceeds 32KB data; and simultaneously counting DDR read-write data packets, when the total number of the write-in packets is larger than the total number of the read-in packets, judging that the DDR cache module has data to be exported, and when the data export interface module is idle, reading 32KB data to the DDR cache module each time and sending the 32KB data to the data receiving end.

Preferably, the step S4 further includes the following steps:

When video stream data is input, a CML encoding and decoding chip decodes a CML video stream input signal of the input video stream data into parallel video stream data, a PL end sequentially carries out frame analysis on the input video stream data according to a general CML protocol, resolution size and line number information in the input video stream data are obtained and are used for detecting the image frame integrity of the input video stream data, if line loss or incomplete image frame data of a data frame exist, the lost part of the image frame data is supplemented with 0, and the image frame data is written into a DDR buffer module;

When video stream data is output, the PL end of the main control module derives the cached output video stream data from the DDR cache module, reads the video stream data frame by taking the resolution of an image frame as an index, carries out a frame adding structure on single-frame image data according to a general CML protocol, outputs the image data to an output interface of a CML encoding and decoding chip at the rate of 30 frames per second, and the CML encoding and decoding chip encodes the image data into a CML video stream output signal to finish simulation output of the output video stream data in a circulating way.

Preferably, the step S5 further includes the following steps:

the SATA read-write management module defines a BLOCK size of 512KB and a PAGE size of 32KB;

when SATA is written, if the data volume of the PL end data of the main control module written to the DDR cache module exceeds BLOCK, data movement is carried out to a write address of the SATA read-write management module;

when SATA is read, the PL end of the main control module reads one address data each time and moves one BLOCK data to the DDR cache module;

The operation instruction and the operation address of the SATA read-write management module are issued by the PS end of the main control module through a BRAM register, the single operation of the SATA read-write management module is carried out by taking BLOCK as a unit, and the data quantity transmission between the SATA read-write port and the DDR cache module is carried out in a BLOCK mode;

When the main control module PL end completes the SATA operation instruction issued by the main control module PS end at a time, the main control module PL end feeds back operation result state information to the main control module PS end through the BRAM register.

Preferably, the step S6 further includes the following steps: the parallel transmission bit number of the USB3.0 chip is configured to be 32 bits, and the FIFO sizes of the input and output endpoints of the USB3.0 chip are both configured to be 32KB;

The command frame data channel is used for transmitting and storing, downloading, simulating, stopping, inquiring equipment state and formatting command data of the SATA disk, the command frame data is issued by the upper computer through an input FIFO of the USB3.0 read-write management module, and the main control module PL receives the command frame data and de-frames the command frame data to obtain a command frame and directly stores the command frame into a 32KB data buffer area pointed by the BRAM register;

the video stream data channel works in a data high-speed downloading mode and a simulated image preview mode; in a data high-speed downloading mode, the PL end of the main control module directly writes data of the DDR cache module into an output FIFO of the USB3.0 read-write management module according to the size of 32KB of each packet; in the simulation image preview mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of image data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 read-write management module at the rate of 30 frames per second.

Preferably, the working steps of the CML video stream data storage thread in S7 include:

S711: the main control module PS receives the data storage instruction, the data storage instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the data storage instruction, the data storage function is started;

s712: the PS end of the main control module issues a storage instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S713: the method comprises the steps that a PS end of a main control module issues a storage address queue to a PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as unused SATA in an address list management space, packages a plurality of SATA addresses into an address queue form, issues the address queue form to the PL end of the main control module through the BRAM register, and is used for providing an address space of the SATA to-be-stored data in advance;

S714: in the CML video stream data processing module, a main control module PL end writes decoded CML video stream data into a write buffer area FIFO of the DDR buffer module according to frames;

S715: in the DDR cache module, data are written into the SATA storage cache in a subpackage mode, each packet of data is 32KB, three data cache areas of the DDR cache module are filled in a circulating mode, and a data cache space is provided for SATA storage operation to achieve circulating storage;

S716: in the SATA read-write management module, a data storage flow is started, data of the DDR cache module is read, unused SATA storage addresses provided by the step S713 are sequentially written, the storage control module reads the data of the DDR cache module according to 512KB, the 512KB data is moved to a SATA storage space corresponding to one SATA storage address provided by the PS end of the main control module, and a single data storage flow is completed;

S717: after finishing the single 512K size CML video stream data storage flow, S714-S716 are repeated until an exit command is received.

Preferably, the working steps of the CML video stream data export thread in S7 include:

S721: the main control module PS receives the downloading or simulation output instruction, the downloading or simulation output instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the downloading or simulation output instruction, the data export function is started;

S722: the PS end of the main control module issues a export instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S723: the PS end of the main control module issues an export address queue to the PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as SATA used in an address list management space, all the used SATA addresses are packed into an address queue form, and the address queue form is issued to the PL end of the main control module through the BRAM register and used for providing an addressing space of the SATA to-be-exported data in advance;

s724: the SATA read-write management module starts a data export flow to export SATA data, and caches the SATA data in the DDR cache module, releases a SATA export address, reads 512KB data corresponding to the current SATA export address, and moves the read 512KB data to a data cache area of the DDR cache module;

S725: in the DDR cache module, data are written into a data cache area of the DDR cache module in a subpackage mode, each packet of data is 32KB, and three data cache areas of the DDR cache module are filled in a circulating mode so as to be exported;

S726: if the PS end of the main control module receives the downloading instruction, the USB3.0 read-write management module works in a data high-speed downloading mode, and the PL end of the main control module directly writes the data in the data buffer area of the DDR buffer module into the output FIFO of the USB3.0 chip according to the size of 32KB of each packet; if the PS end of the main control module receives the simulation output instruction, the USB3.0 read-write management module works in a simulation playing mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of video data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 chip at the rate of 30 frames per second;

S727: if the PS end of the main control module receives the downloading instruction, the video stream processing module based on the CML video interface does not output the downloading instruction; if the PS end of the main control module receives the simulation output instruction, the video stream processing module based on the CML video interface works in an output mode, the PL end of the main control module reads out the data in the data buffer area of the DDR buffer module according to each video frame according to the resolution, adds a CML protocol frame structure to the video frame data, and finally converts the digital signal into a CML signal to be output through a CML encoding and decoding chip, wherein the video stream output frame rate is 30 frames per second;

S728: and repeatedly executing S724-S727 after each 512KB of data is exported until the video stream data corresponding to the SATA address queues of all the stored data is exported.

A second aspect of the invention provides: a video stream processing device based on a CML video interface, configured to implement any one of the video stream processing methods based on the CML video interface, including: the system comprises a CML video stream interface module, a SATA disk storage module, a key indicator module and a ZYNQ embedded main control module; the CML video stream interface module, the SATA disk storage module and the key indicator module are all connected with the ZYNQ embedded main control module;

The control core of the ZYNQ embedded main control module is a ZYNQ chip, which comprises a PL end and a PS end; the PL end of the ZYNQ chip runs an FPGA logic program to realize high-speed processing of video stream data, DDR data read-write cache, high-speed parallel read-write of a SATA disk storage module and high-speed parallel read-write of a USB3.0 chip; the PS end of the ZYNQ chip runs an embedded program to realize SATA disk address list management, key detection and indicator lamp control; the PL end and the PS end of the ZYNQ chip are communicated with each other through a BRAM register to perform data interaction; the USB3.0 interface is communicated with the PC upper computer;

The core of the CML video stream interface module is a CML encoding and decoding chip; the CML encoding and decoding chip has two working modes of encoding and decoding, when the CML encoding and decoding chip works in the decoding mode, video stream of the CML input interface is decoded into parallel video stream data and is transmitted to the ZYNQ chip PL end, and when the CML encoding and decoding chip works in the encoding mode, parallel video stream data transmitted from the ZYNQ chip PL end is encoded into CML video stream and is output from the CML output interface;

the SATA disk storage module is controlled by parallel reading and writing of logic programs at the PL end of the ZYNQ chip;

The key indicator lamp module is characterized in that keys 1-4 of the key indicator lamp module are respectively used for function control of storage, downloading, simulation output and stopping, and LED 1-4 indicator lamps are respectively used for state indication of storage, downloading, simulation output and stopping.

A third aspect of the invention provides: a computer readable storage medium having stored therein computer executable instructions that when loaded and executed by a processor implement any of the above-described CML video interface based video stream processing methods.

The beneficial effects of the invention are as follows:

1) Fills the blank of the integration of the storage, downloading and simulation output functions in the existing CML video stream application field, and realizes the function of performing CML video stream simulation output by using stored video stream data under the condition of no CML video stream source.

2) And supplementing 0 to the lost part of the image frame data and writing the lost part of the image frame data into the DDR buffer module to ensure the integrity and the alignment of the image frames of the stored CML video stream data, thereby realizing the integrity of the image frames when the video stream is simulated and output.

Drawings

FIG. 1 is a flow chart of a video stream processing method based on a CML video interface;

FIG. 2 is a system block diagram of a video stream processing device based on a CML video interface;

FIG. 3 is a memory partition diagram of a DDR cache module;

FIG. 4 is a schematic diagram of a CML video stream data processing module;

FIG. 5 is a schematic diagram of a SATA read-write management module;

FIG. 6 is a schematic diagram of a USB3.0 read/write management module;

FIG. 7 is a flow chart of a CML video stream data storage thread;

Fig. 8 is a flow chart of a CML video stream data export thread.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.

Referring to fig. 1-8, a first aspect of the present invention provides: a video stream processing method based on a CML video interface is characterized in that: the method comprises the following steps:

S1: the initialization hardware module comprises a main control module, a CML video stream interface module, a SATA disk storage module and a key indicator module;

S2: initializing each on-board chip and interfaces, wherein the chips comprise DDR chips, USB3.0 chips and CML encoding and decoding chips, and the interfaces comprise BRAM interfaces, CML parallel digital interfaces, SATA disk read-write interfaces, USB3.0 interfaces and I/O interfaces;

s3: starting a DDR cache module, and carrying out partition cache processing on SATA storage data and SATA export data;

S4: starting a CML video stream data processing module, controlling the input and output of video stream data of a CML encoding and decoding chip according to a working mode, performing frame decoding structure processing and image frame integrity processing on the input video stream data, performing frame adding structure processing and output frame rate control on the output video stream data, and controlling the read-write operation of the video stream data in the DDR cache module;

S5: starting a SATA read-write management module, according to a command issued by a PS end of a main control module, reading and writing data on the SATA disk, formatting the data, and returning to SATA disk state operation;

S6: starting a USB3.0 read-write management module, and dividing USB3.0 data read-write into an instruction frame data channel and a video stream data channel according to the difference of data magnitudes;

S7: based on S3-S6, respectively establishing a CML video stream data storage thread and a CML video stream data export thread, wherein the CML video stream data export thread is used for realizing two functions of downloading and simulation output according to instructions;

s8: a cyclic scanning key input instruction and an upper computer input instruction, and triggering a CML video stream data storage thread in S7 if a storage instruction is received; and if a downloading or simulation instruction is received, triggering the CML video stream data export thread in S7.

In some embodiments, the step S3 further comprises the steps of: distributing a write buffer area FIFO and three data buffer areas in the DDR buffer module for circular buffer storage, and providing a SATA storage buffer storage function and a SATA export buffer storage function; the SATA storage and caching function is as follows: triggering write DDR operation when the data quantity of the write cache area FIFO exceeds 32KB data; when the read DDR data is sent into the SATA write data buffer interval, the data quantity of one packet of SATA is 512KB, the DDR buffer module is correspondingly operated to read 16 times, the DDR reading operation is started when the number of the read and write packets is unequal, and the DDR writing operation is performed simultaneously because the bandwidth of the DDR buffer module is larger than that of the SATA disk storage module, so that the front-end input data can be prevented from being lost;

the SATA exports the cache function and is: when receiving SATA read data, triggering write DDR operation when the data quantity of the write buffer area FIFO exceeds 32KB data; and simultaneously counting DDR read-write data packets, when the total number of the write-in packets is larger than the total number of the read-in packets, judging that the DDR cache module has data to be exported, and when the data export interface module is idle, reading 32KB data to the DDR cache module each time and sending the 32KB data to the data receiving end.

In some embodiments, the step S4 further comprises the steps of:

When video stream data is input, a CML encoding and decoding chip decodes a CML video stream input signal of the input video stream data into parallel video stream data, a PL end sequentially carries out frame analysis on the input video stream data according to a general CML protocol, resolution size and line number information in the input video stream data are obtained and are used for detecting the image frame integrity of the input video stream data, if line loss or incomplete image frame data of a data frame exist, the lost part of the image frame data is supplemented with 0, and the image frame data is written into a DDR buffer module;

When video stream data is output, the PL end of the main control module derives the cached output video stream data from the DDR cache module, reads the video stream data frame by taking the resolution of an image frame as an index, carries out a frame adding structure on single-frame image data according to a general CML protocol, outputs the image data to an output interface of a CML encoding and decoding chip at the rate of 30 frames per second, and the CML encoding and decoding chip encodes the image data into a CML video stream output signal to finish simulation output of the output video stream data in a circulating way.

In some embodiments, the step S5 further comprises the steps of:

the SATA read-write management module defines a BLOCK size of 512KB and a PAGE size of 32KB;

when SATA is written, if the data volume of the PL end data of the main control module written to the DDR cache module exceeds BLOCK, data movement is carried out to a write address of the SATA read-write management module;

when SATA is read, the PL end of the main control module reads one address data each time and moves one BLOCK data to the DDR cache module;

The operation instruction and the operation address of the SATA read-write management module are issued by the PS end of the main control module through a BRAM register, the single operation of the SATA read-write management module is carried out by taking BLOCK as a unit, and the data quantity transmission between the SATA read-write port and the DDR cache module is carried out in a BLOCK mode;

When the main control module PL end completes the SATA operation instruction issued by the main control module PS end at a time, the main control module PL end feeds back operation result state information to the main control module PS end through the BRAM register.

In some embodiments, the step S6 further comprises the steps of: the parallel transmission bit number of the USB3.0 chip is configured to be 32 bits, and the FIFO sizes of the input and output endpoints of the USB3.0 chip are both configured to be 32KB;

The command frame data channel is used for transmitting and storing, downloading, simulating, stopping, inquiring equipment state and formatting command data of the SATA disk, the command frame data is issued by the upper computer through an input FIFO of the USB3.0 read-write management module, and the main control module PL receives the command frame data and de-frames the command frame data to obtain a command frame and directly stores the command frame into a 32KB data buffer area pointed by the BRAM register;

The video stream data channel works in a data high-speed downloading mode and a simulated image preview mode; in a data high-speed downloading mode, the PL end of the main control module directly writes data of the DDR cache module into an output FIFO of the USB3.0 read-write management module according to the size of 32KB of each packet; in the simulation image preview mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of image data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 read-write management module at the rate of 30 frames per second. And the preview images of the output video streams are synchronously displayed on the upper computer when the CML video streams are simulated and output.

In some embodiments, the working steps of the CML video stream data storage thread in S7 include:

S711: the main control module PS receives the data storage instruction, the data storage instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the data storage instruction, the data storage function is started;

s712: the PS end of the main control module issues a storage instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S713: the method comprises the steps that a PS end of a main control module issues a storage address queue to a PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as unused SATA in an address list management space, packages a plurality of SATA addresses into an address queue form, issues the address queue form to the PL end of the main control module through the BRAM register, and is used for providing an address space of the SATA to-be-stored data in advance;

S714: in the CML video stream data processing module, a main control module PL end writes decoded CML video stream data into a write buffer area FIFO of the DDR buffer module according to frames;

S715: in the DDR cache module, data are written into the SATA storage cache in a subpackage mode, each packet of data is 32KB, three data cache areas of the DDR cache module are filled in a circulating mode, and a data cache space is provided for SATA storage operation to achieve circulating storage;

S716: in the SATA read-write management module, a data storage flow is started, data of the DDR cache module is read, unused SATA storage addresses provided by the step S713 are sequentially written, the storage control module reads the data of the DDR cache module according to 512KB, the 512KB data is moved to a SATA storage space corresponding to one SATA storage address provided by the PS end of the main control module, and a single data storage flow is completed;

S717: after finishing the single 512K size CML video stream data storage flow, S714-S716 are repeated until an exit command is received.

In some embodiments, the working steps of the CML video stream data export thread in S7 include:

S721: the main control module PS receives the downloading or simulation output instruction, the downloading or simulation output instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the downloading or simulation output instruction, the data export function is started;

S722: the PS end of the main control module issues a export instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S723: the PS end of the main control module issues an export address queue to the PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as SATA used in an address list management space, all the used SATA addresses are packed into an address queue form, and the address queue form is issued to the PL end of the main control module through the BRAM register and used for providing an addressing space of the SATA to-be-exported data in advance;

s724: the SATA read-write management module starts a data export flow to export SATA data, and caches the SATA data in the DDR cache module, releases a SATA export address, reads 512KB data corresponding to the current SATA export address, and moves the read 512KB data to a data cache area of the DDR cache module;

S725: in the DDR cache module, data are written into a data cache area of the DDR cache module in a subpackage mode, each packet of data is 32KB, and three data cache areas of the DDR cache module are filled in a circulating mode so as to be exported;

S726: if the PS end of the main control module receives the downloading instruction, the USB3.0 read-write management module works in a data high-speed downloading mode, and the PL end of the main control module directly writes the data in the data buffer area of the DDR buffer module into the output FIFO of the USB3.0 chip according to the size of 32KB of each packet; if the PS end of the main control module receives the simulation output instruction, the USB3.0 read-write management module works in a simulation playing mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of video data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 chip at the rate of 30 frames per second;

S727: if the PS end of the main control module receives the downloading instruction, the video stream processing module based on the CML video interface does not output the downloading instruction; if the PS end of the main control module receives the simulation output instruction, the video stream processing module based on the CML video interface works in an output mode, the PL end of the main control module reads out the data in the data buffer area of the DDR buffer module according to each video frame according to the resolution, adds a CML protocol frame structure to the video frame data, and finally converts the digital signal into a CML signal to be output through a CML encoding and decoding chip, wherein the video stream output frame rate is 30 frames per second;

S728: and repeatedly executing S724-S727 after each 512KB of data is exported until the video stream data corresponding to the SATA address queues of all the stored data is exported.

A second aspect of the invention provides: a video stream processing device based on a CML video interface, configured to implement any one of the video stream processing methods based on the CML video interface, including: the system comprises a CML video stream interface module, a SATA disk storage module, a key indicator module and a ZYNQ embedded main control module; the CML video stream interface module, the SATA disk storage module and the key indicator module are all connected with the ZYNQ embedded main control module;

The control core of the ZYNQ embedded main control module is a ZYNQ chip, which comprises a PL end and a PS end; the PL end of the ZYNQ chip runs an FPGA logic program to realize high-speed processing of video stream data, DDR data read-write cache, high-speed parallel read-write of a SATA disk storage module and high-speed parallel read-write of a USB3.0 chip; the PS end of the ZYNQ chip runs an embedded program to realize SATA disk address list management, key detection and indicator lamp control; the PL end and the PS end of the ZYNQ chip are communicated with each other through a BRAM register to perform data interaction; the USB3.0 interface is communicated with the PC upper computer;

The core of the CML video stream interface module is a CML encoding and decoding chip; the CML encoding and decoding chip has two working modes of encoding and decoding, when the CML encoding and decoding chip works in the decoding mode, video stream of the CML input interface is decoded into parallel video stream data and is transmitted to the ZYNQ chip PL end, and when the CML encoding and decoding chip works in the encoding mode, parallel video stream data transmitted from the ZYNQ chip PL end is encoded into CML video stream and is output from the CML output interface;

the SATA disk storage module is controlled by parallel reading and writing of logic programs at the PL end of the ZYNQ chip;

The key indicator lamp module is characterized in that keys 1-4 of the key indicator lamp module are respectively used for function control of storage, downloading, simulation output and stopping, and LED 1-4 indicator lamps are respectively used for state indication of storage, downloading, simulation output and stopping.

ZYNQ embedded master control module: the system mainly comprises a ZYNQ chip, a DDR chip, a USB3.0 interface, a parallel data interface, a SATA disk read-write interface and an I/O interface, and is used for system function management and logic realization of a video stream processing device based on a CML video interface. CML video stream interface module: the system mainly comprises a CML encoding and decoding chip, a CML input interface, a CML output interface and a parallel digital interface, and is mainly used for interconversion of CML video stream and parallel video stream data. SATA disk storage module: the system mainly comprises 4 SATA solid state disks, SATA disk read-write interfaces and related peripheral circuits. The SATA solid state hard disk with the size of 4 SATA is adopted, the storage capacity is 4TB in total, and the SATA solid state hard disk has the characteristics of high-speed reading and writing, large capacity, small volume and replaceability, and can be replaced with a SATA solid state hard disk with larger capacity according to use requirements. Key indicator module: the device mainly comprises 4 self-recovery mechanical keys, 4 LED indicator lamps and a driving circuit thereof, and is mainly used for manual control and state monitoring of related functions of a video stream processing device based on a CML video interface.

A third aspect of the invention provides: a computer readable storage medium having stored therein computer executable instructions that when loaded and executed by a processor implement any of the above-described CML video interface based video stream processing methods.

The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (9)

1. A video stream processing method based on a CML video interface is characterized in that: the method comprises the following steps:

S1: the initialization hardware module comprises a main control module, a CML video stream interface module, a SATA disk storage module and a key indicator module;

S2: initializing each on-board chip and interfaces, wherein the chips comprise DDR chips, USB3.0 chips and CML encoding and decoding chips, and the interfaces comprise BRAM interfaces, CML parallel digital interfaces, SATA disk read-write interfaces, USB3.0 interfaces and I/O interfaces;

s3: starting a DDR cache module, and carrying out partition cache processing on SATA storage data and SATA export data;

S4: starting a CML video stream data processing module, controlling the input and output of video stream data of a CML encoding and decoding chip according to a working mode, performing frame decoding structure processing and image frame integrity processing on the input video stream data, performing frame adding structure processing and output frame rate control on the output video stream data, and controlling the read-write operation of the video stream data in the DDR cache module;

S5: starting a SATA read-write management module, according to a command issued by a PS end of a main control module, reading and writing data on the SATA disk, formatting the data, and returning to SATA disk state operation;

S6: starting a USB3.0 read-write management module, and dividing USB3.0 data read-write into an instruction frame data channel and a video stream data channel according to the difference of data magnitudes;

S7: based on S3-S6, respectively establishing a CML video stream data storage thread and a CML video stream data export thread, wherein the CML video stream data export thread is used for realizing two functions of downloading and simulation output according to instructions;

s8: a cyclic scanning key input instruction and an upper computer input instruction, and triggering a CML video stream data storage thread in S7 if a storage instruction is received; and if a downloading or simulation instruction is received, triggering the CML video stream data export thread in S7.

2. The CML video interface-based video stream processing method of claim 1, wherein: the step S3 also comprises the following steps: distributing a write buffer area FIFO and three data buffer areas in the DDR buffer module for circular buffer storage, and providing a SATA storage buffer storage function and a SATA export buffer storage function; the SATA storage and caching function is as follows: triggering write DDR operation when the data quantity of the write cache area FIFO exceeds 32KB data; when the read DDR data is sent into the SATA write data buffer interval, the data quantity of one packet of SATA write is 512KB each time, the corresponding operation is performed on the read DDR buffer module for 16 times, the read DDR operation is started when the number of read and write packets is unequal, and the write DDR operation is performed simultaneously;

the SATA exports the cache function and is: when receiving SATA read data, triggering write DDR operation when the data quantity of the write buffer area FIFO exceeds 32KB data; and simultaneously counting DDR read-write data packets, when the total number of the write-in packets is larger than the total number of the read-in packets, judging that the DDR cache module has data to be exported, and when the data export interface module is idle, reading 32KB data to the DDR cache module each time and sending the 32KB data to the data receiving end.

3. The CML video interface-based video stream processing method of claim 1, wherein: the step S4 also comprises the following steps:

When video stream data is input, a CML encoding and decoding chip decodes a CML video stream input signal of the input video stream data into parallel video stream data, a PL end sequentially carries out frame analysis on the input video stream data according to a general CML protocol, resolution size and line number information in the input video stream data are obtained and are used for detecting the image frame integrity of the input video stream data, if line loss or incomplete image frame data of a data frame exist, the lost part of the image frame data is supplemented with 0, and the image frame data is written into a DDR buffer module;

When video stream data is output, the PL end of the main control module derives the cached output video stream data from the DDR cache module, reads the video stream data frame by taking the resolution of an image frame as an index, carries out a frame adding structure on single-frame image data according to a general CML protocol, outputs the image data to an output interface of a CML encoding and decoding chip at the rate of 30 frames per second, and the CML encoding and decoding chip encodes the image data into a CML video stream output signal to finish simulation output of the output video stream data in a circulating way.

4. The CML video interface-based video stream processing method of claim 1, wherein: the step S5 also comprises the following steps:

the SATA read-write management module defines a BLOCK size of 512KB and a PAGE size of 32KB;

when SATA is written, if the data volume of the PL end data of the main control module written to the DDR cache module exceeds BLOCK, data movement is carried out to a write address of the SATA read-write management module;

when SATA is read, the PL end of the main control module reads one address data each time and moves one BLOCK data to the DDR cache module;

The operation instruction and the operation address of the SATA read-write management module are issued by the PS end of the main control module through a BRAM register, the single operation of the SATA read-write management module is carried out by taking BLOCK as a unit, and the data quantity transmission between the SATA read-write port and the DDR cache module is carried out in a BLOCK mode;

When the main control module PL end completes the SATA operation instruction issued by the main control module PS end at a time, the main control module PL end feeds back operation result state information to the main control module PS end through the BRAM register.

5. The CML video interface-based video stream processing method of claim 1, wherein: the step S6 also comprises the following steps: the parallel transmission bit number of the USB3.0 chip is configured to be 32 bits, and the FIFO sizes of the input and output endpoints of the USB3.0 chip are both configured to be 32KB;

The command frame data channel is used for transmitting and storing, downloading, simulating, stopping, inquiring equipment state and formatting command data of the SATA disk, the command frame data is issued by the upper computer through an input FIFO of the USB3.0 read-write management module, and the main control module PL receives the command frame data and de-frames the command frame data to obtain a command frame and directly stores the command frame into a 32KB data buffer area pointed by the BRAM register;

the video stream data channel works in a data high-speed downloading mode and a simulated image preview mode; in a data high-speed downloading mode, the PL end of the main control module directly writes data of the DDR cache module into an output FIFO of the USB3.0 read-write management module according to the size of 32KB of each packet; in the simulation image preview mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of image data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 read-write management module at the rate of 30 frames per second.

6. The CML video interface-based video stream processing method of claim 1, wherein: the working steps of the CML video stream data storage thread in the S7 include:

S711: the main control module PS receives the data storage instruction, the data storage instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the data storage instruction, the data storage function is started;

s712: the PS end of the main control module issues a storage instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S713: the method comprises the steps that a PS end of a main control module issues a storage address queue to a PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as unused SATA in an address list management space, packages a plurality of SATA addresses into an address queue form, issues the address queue form to the PL end of the main control module through the BRAM register, and is used for providing an address space of the SATA to-be-stored data in advance;

S714: in the CML video stream data processing module, a main control module PL end writes decoded CML video stream data into a write buffer area FIFO of the DDR buffer module according to frames;

S715: in the DDR cache module, data are written into the SATA storage cache in a subpackage mode, each packet of data is 32KB, three data cache areas of the DDR cache module are filled in a circulating mode, and a data cache space is provided for SATA storage operation to achieve circulating storage;

S716: in the SATA read-write management module, a data storage flow is started, data of the DDR cache module is read, unused SATA storage addresses provided by the step S713 are sequentially written, the storage control module reads the data of the DDR cache module according to 512KB, the 512KB data is moved to a SATA storage space corresponding to one SATA storage address provided by the PS end of the main control module, and a single data storage flow is completed;

S717: after finishing the single 512K size CML video stream data storage flow, S714-S716 are repeated until an exit command is received.

7. The CML video interface-based video stream processing method of claim 1, wherein: the working steps of the CML video stream data export thread in S7 include:

S721: the main control module PS receives the downloading or simulation output instruction, the downloading or simulation output instruction of the main control module PS is sourced from a key or an upper computer, and when the main control module PS receives the downloading or simulation output instruction, the data export function is started;

S722: the PS end of the main control module issues a export instruction to the PL end of the main control module through a BRAM register to the SATA read-write management module;

S723: the PS end of the main control module issues an export address queue to the PL end of the main control module through a BRAM register, the PS end of the main control module retrieves storage addresses marked as SATA used in an address list management space, all the used SATA addresses are packed into an address queue form, and the address queue form is issued to the PL end of the main control module through the BRAM register and used for providing an addressing space of the SATA to-be-exported data in advance;

s724: the SATA read-write management module starts a data export flow to export SATA data, and caches the SATA data in the DDR cache module, releases a SATA export address, reads 512KB data corresponding to the current SATA export address, and moves the read 512KB data to a data cache area of the DDR cache module;

S725: in the DDR cache module, data are written into a data cache area of the DDR cache module in a subpackage mode, each packet of data is 32KB, and three data cache areas of the DDR cache module are filled in a circulating mode so as to be exported;

S726: if the PS end of the main control module receives the downloading instruction, the USB3.0 read-write management module works in a data high-speed downloading mode, and the PL end of the main control module directly writes the data in the data buffer area of the DDR buffer module into the output FIFO of the USB3.0 chip according to the size of 32KB of each packet; if the PS end of the main control module receives the simulation output instruction, the USB3.0 read-write management module works in a simulation playing mode, the PL end of the main control module extracts partial data according to the resolution of 640x480 from each frame of video data frame read in the video stream processing module based on the CML video interface, and writes the partial data into the output FIFO of the USB3.0 chip at the rate of 30 frames per second;

S727: if the PS end of the main control module receives the downloading instruction, the video stream processing module based on the CML video interface does not output the downloading instruction; if the PS end of the main control module receives the simulation output instruction, the video stream processing module based on the CML video interface works in an output mode, the PL end of the main control module reads out the data in the data buffer area of the DDR buffer module according to each video frame according to the resolution, adds a CML protocol frame structure to the video frame data, and finally converts the digital signal into a CML signal to be output through a CML encoding and decoding chip, wherein the video stream output frame rate is 30 frames per second;

S728: and repeatedly executing S724-S727 after each 512KB of data is exported until the video stream data corresponding to the SATA address queues of all the stored data is exported.

8. A video stream processing device based on a CML video interface, characterized in that: a video stream processing method for implementing a CML-based video interface as claimed in any one of claims 1-7, comprising: the system comprises a CML video stream interface module, a SATA disk storage module, a key indicator module and a ZYNQ embedded main control module; the CML video stream interface module, the SATA disk storage module and the key indicator module are all connected with the ZYNQ embedded main control module;

The control core of the ZYNQ embedded main control module is a ZYNQ chip, which comprises a PL end and a PS end; the PL end of the ZYNQ chip runs an FPGA logic program to realize high-speed processing of video stream data, DDR data read-write cache, high-speed parallel read-write of a SATA disk storage module and high-speed parallel read-write of a USB3.0 chip; the PS end of the ZYNQ chip runs an embedded program to realize SATA disk address list management, key detection and indicator lamp control; the PL end and the PS end of the ZYNQ chip are communicated with each other through a BRAM register to perform data interaction; the USB3.0 interface is communicated with the PC upper computer;

The core of the CML video stream interface module is a CML encoding and decoding chip; the CML encoding and decoding chip has two working modes of encoding and decoding, when the CML encoding and decoding chip works in the decoding mode, video stream of the CML input interface is decoded into parallel video stream data and is transmitted to the ZYNQ chip PL end, and when the CML encoding and decoding chip works in the encoding mode, parallel video stream data transmitted from the ZYNQ chip PL end is encoded into CML video stream and is output from the CML output interface;

the SATA disk storage module is controlled by parallel reading and writing of logic programs at the PL end of the ZYNQ chip;

The key indicator lamp module is characterized in that keys 1-4 of the key indicator lamp module are respectively used for function control of storage, downloading, simulation output and stopping, and LED 1-4 indicator lamps are respectively used for state indication of storage, downloading, simulation output and stopping.

9. A computer-readable storage medium, characterized by: the computer readable storage medium stores computer executable instructions that, when loaded and executed by a processor, implement the CML video interface-based video stream processing method of any one of claims 1-7.