CN107301868B - Audio decoding system and audio decoding method - Google Patents
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Abstract
The invention provides an audio decoding system and an audio decoding method.A first processor transmits audio data to be decoded to a second processor for processing through a data buffer area, controls audio decoding of the second processor through an interaction unit, and realizes audio decoding by two processors together to improve decoding efficiency and system real-time; the interaction between the two processors is realized through the interaction unit, the transmission of the audio data to be decoded is realized through the data buffer area, and the reliability of the audio decoding realized by the two processors together is ensured.
Description
Technical Field
The present invention relates to the field of audio processing technologies, and in particular, to an audio decoding system and an audio decoding method.
Background
With the rapid development of microelectronic technology and multimedia technology, embedded products are widely applied in many fields such as homes, workplaces, entertainment venues, etc., and the demand for audio playing and decoding on embedded systems is also continuously increasing. However, due to the characteristics of small embedded system kernel, limited system resources and the like, a performance bottleneck always exists in high-quality audio decoding, and the problem that other tasks of the system cannot be processed in time due to decoding time consumption or decoding cannot be completed in time due to processing of other tasks may occur in the system operation, so that the real-time performance and user experience of the system are greatly influenced.
Disclosure of Invention
The invention aims to provide an audio decoding system and an audio decoding method, and aims to solve the problems that other tasks of the system cannot be processed in time due to decoding time consumption possibly occurring in system operation or decoding cannot be completed in time due to processing of other tasks in the prior art.
In view of the above object, the present invention provides an audio decoding system, including: the system comprises a first processor, a second processor, an interaction unit and a data buffer area; wherein the content of the first and second substances,
the first processor transfers the audio data to be decoded to the second processor through the data buffer for processing, and the first processor controls the audio decoding of the second processor through the interaction unit.
Optionally, in the audio decoding system, the interactive unit includes a first interactive unit and a second interactive unit; the first interaction unit is used for realizing interaction between the first processor and the second processor; the second interaction unit is used for storing the memory address mapping operated by the second processor.
Optionally, in the audio decoding system, the first processor starts the second processor through the memory address mapping stored in the second interactive unit.
Optionally, in the audio decoding system, the first processor is further configured to reset the second processor.
Optionally, in the audio decoding system, the first interaction unit includes an interrupt control register, the interrupt control register is used for transmitting an interrupt signal, and the first processor and the second processor interact with each other through the interrupt signal.
Optionally, in the audio decoding system, the interrupt control register includes a first interrupt control register and a second interrupt control register, where the first interrupt control register is used to transmit an interrupt signal sent by the first processor to the second processor, and the second interrupt control register is used to transmit an interrupt signal sent by the second processor to the first processor.
Optionally, in the audio decoding system, the first interrupt control register and the second interrupt control register are both thirty-two bit interrupt control registers.
Optionally, in the audio decoding system, the first interaction unit further includes a mailbox register, where the mailbox register includes a data register and a mutual exclusion lock, the data register is used to store an interaction command of the first processor and the second processor, and the mutual exclusion lock is used to latch the data register.
Optionally, in the audio decoding system, the mutually exclusive lock is configured to latch the data register, and includes: when the first processor sends a control command, the first processor inquires a mutual exclusion lock; the first processor acquires an idle mutual exclusion lock and marks the idle mutual exclusion lock as non-idle; the first processor writes a control command into a data register corresponding to the acquired mutex; the first processor generates an interrupt signal according to the acquired mutex; and the first processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding system, the mutex lock is configured to latch the data register, and further includes: when the second processor receives a control command, the second processor receives an interrupt signal; the second processor acquires a mutual exclusion lock according to the interrupt signal; the second processor reads a control command in the corresponding data register according to the acquired mutual exclusion lock; the second processor writes a reply command into the data register; the second processor sets an interrupt signal; and the second processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding system, the mutex lock is configured to latch the data register, and further includes: when the first processor receives a reply command, the first processor receives an interrupt signal; the first processor acquires a mutual exclusion lock according to the interrupt signal; the first processor reads a reply command in the corresponding data box according to the acquired mutual exclusion lock; and the first processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding system, the number of the data registers is thirty two groups, and the number of the mutex locks is thirty two groups, where thirty two groups of the data registers and thirty two groups of the mutex locks are in one-to-one correspondence.
Optionally, in the audio decoding system, the command sent by the first processor to the second processor includes a DMA interrupt.
Optionally, in the audio decoding system, the first processor controls the audio decoding of the second processor by sending a control command, where the control command includes play, exit, pause, fast forward, or fast rewind.
Optionally, in the audio decoding system, the data buffer is used for storing audio data to be decoded and decoded audio data.
Optionally, in the audio decoding system, the data buffer includes an input data buffer and an output data buffer, where the input data buffer is used to store audio data to be decoded, and the output data buffer is used to store decoded audio data and audio information of the decoded audio data.
Optionally, in the audio decoding system, the input data buffer performs data writing through a first write pointer, and performs data reading through a first read pointer; and the output data buffer zone writes data through a second write pointer and reads data through a second read pointer.
Optionally, in the audio decoding system, the second processor performs input of audio data to be decoded and output of decoded audio data in a chain DMA manner.
Optionally, in the audio decoding system, the first processor and/or the second processor are further configured to perform sound effect post-processing, audio transcoding processing, recording processing, and/or playing processing on the decoded audio data.
Optionally, in the audio decoding system, the first processor is further configured to write the decoded audio data into an external storage medium.
Optionally, in the audio decoding system, the first processor is a RISC, and the second processor is a DSP.
The present invention also provides an audio decoding method, including: the first processor transmits the audio data to be decoded to the second processor through the data buffer area for processing; and the first processor controls the audio decoding of the second processor through the interaction unit.
Optionally, in the audio decoding method, the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing, and the first processor controls the audio decoding of the second processor through the interaction unit to be performed simultaneously; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing before the first processor controls the audio decoding of the second processor through the interaction unit; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing after the first processor controls the audio decoding of the second processor through the interaction unit.
Optionally, in the audio decoding method, the controlling, by the first processor, the audio decoding by the second processor through the interaction unit includes:
the first processor sends a control command to the interaction unit, and the first processor controls audio decoding by sending the control command;
the second processor receives a control command from the interactive unit and processes audio data to be decoded according to the control command.
Optionally, in the audio decoding method, the sending, by the first processor, the control command to the interactive unit includes:
the first processor inquires a mutual exclusion lock;
the first processor acquires an idle mutual exclusion lock and marks the idle mutual exclusion lock as non-idle;
the first processor writes a control command into a data register corresponding to the acquired mutex;
the first processor generates an interrupt signal according to the acquired mutex;
and the first processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding method, the receiving, by the second processor, a control command from the interaction unit, and processing the audio data to be decoded according to the control command includes:
the second processor receives an interrupt signal;
the second processor acquires a mutual exclusion lock according to the interrupt signal;
the second processor reads a control command in the corresponding data register according to the acquired mutual exclusion lock;
the second processor writes a reply command into the data register;
the second processor sets an interrupt signal;
and the second processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding method, after the second processor reads the control command in the corresponding data register according to the acquired mutex lock, the second processor receives the control command from the interaction unit, and processes the audio data to be decoded according to the control command further includes:
the second processor reads audio data to be decoded of an input data buffer;
the second processor decodes the read audio data to be decoded;
the second processor writes the decoded audio data and audio information of the decoded audio data to the output data buffer.
Optionally, in the audio decoding method, after the second processor reads the control command in the corresponding data register according to the acquired mutex lock, the second processor receives the control command from the interaction unit, and processes the audio data to be decoded according to the control command further includes:
the second processor inputs audio data to be decoded by using a chain DMA mode;
the second processor decodes the input audio data to be decoded;
the second processor performs output of the decoded audio data using a chained DMA manner.
Optionally, in the audio decoding method, after the second processor receives the control command from the interaction unit and processes the audio data to be decoded according to the control command, the controlling, by the first processor, audio decoding by the second processor through the interaction unit further includes:
the first processor receives a reply command from the interaction unit.
Optionally, in the audio decoding method, the receiving, by the first processor, a reply command from the interaction unit includes:
the first processor receives an interrupt signal;
the first processor acquires a mutual exclusion lock according to the interrupt signal;
the first processor reads a reply command in the corresponding data register according to the acquired mutual exclusion lock;
and the first processor releases the acquired mutual exclusion lock.
Optionally, in the audio decoding method, after the first processor receives a reply command from the interaction unit, the audio decoding method further includes:
the first processor reads decoded audio data of an output data buffer.
Optionally, in the audio decoding method, after the first processor reads the decoded audio data of the output data buffer, the audio decoding method further includes:
and the first processor and/or the second processor perform sound effect post-processing, audio transcoding processing, recording processing and/or playing processing on the decoded audio data.
Optionally, in the audio decoding method, after the first processor reads the decoded audio data of the output data buffer, the audio decoding method further includes:
the first processor writes the decoded audio data to a peripheral storage medium.
Optionally, in the audio decoding method, before the first processor controls audio decoding of the second processor through the interaction unit, the audio decoding method further includes:
and the first processor starts the second processor through the memory address mapping stored in the second interaction unit.
In the audio decoding system and the audio decoding method provided by the invention, a first processor transmits audio data to be decoded to a second processor for processing through a data buffer area, the first processor controls audio decoding of the second processor through an interaction unit, and the two processors jointly realize audio decoding to improve decoding efficiency and system real-time performance; the interaction between the two processors is realized through the interaction unit, the transmission of the audio data to be decoded is realized through the data buffer area, and the reliability of the audio decoding realized by the two processors together is ensured.
Drawings
FIG. 1 is a block diagram of an audio decoding system according to an embodiment of the present invention;
FIG. 2 is a flow chart of an audio decoding method according to an embodiment of the invention;
fig. 3 is a flow chart illustrating the interaction of control commands in the audio decoding method according to the embodiment of the invention.
Detailed Description
The following describes the audio decoding system and the audio decoding method according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In particular, the drawings are intended to show different emphasis points and are often in different proportions.
Please refer to fig. 1, which is a block diagram of an audio decoding system according to an embodiment of the present invention. As shown in fig. 1, the audio decoding system 1 includes: a first processor 10, a second processor 11, an interaction unit 12 and a data buffer 13; wherein the first processor 10 transfers the audio data to be decoded to the second processor 11 through the data buffer 13 for processing, and the first processor 10 controls the audio decoding of the second processor 11 through the interaction unit 12. In the embodiment of the present application, the audio decoding process is mainly controlled by the first processor 10; the second processor 11 processes the audio data to be decoded, so that the two processors jointly realize audio decoding to improve decoding efficiency and system real-time performance. Further, the first processor 10 controls the audio decoding process by sending control commands including commands for controlling audio decoding operations such as play, exit, pause, fast forward or fast reverse audio. In the embodiment of the present application, the first processor 10 is a Reduced Instruction Set Computer (RISC), and the second processor 11 is a Digital Signal Processing (DSP).
Specifically, the interaction unit 12 includes a first interaction unit 120 and a second interaction unit 121; wherein, the first interaction unit 120 is configured to implement interaction between the first processor 10 and the second processor 11; the second interaction unit 121 is configured to store a memory address map executed by the second processor 11.
In the embodiment of the present application, the first processor 10 is further configured to control the operation of the second processor 11. Specifically, the first processor 10 starts the second processor 11 according to the memory address mapping. The method mainly comprises the following steps: the first processor 10 copies the firmware program of the second processor 11 to the corresponding memory address according to the memory address mapping; the first processor 10 sets the state of the second processor 11 to start, and the second processor 11 starts normal operation. In the embodiment of the present application, the operation of the second processor 11 is controlled by the first processor 10, so that the system operation with different complexity can be better adapted.
Furthermore, the first processor 10 is also configured to reset the second processor 11. Specifically, when a fatal error occurs during the operation of the second processor 11, the first processor 10 may reset the second processor 11 according to the memory address mapping, that is, the first processor 10 restarts the second processor 11 according to the memory address mapping, thereby avoiding a system downtime problem and ensuring the reliability of system operation.
In the embodiment of the present application, the communication between the first processor 10 and the second processor 11 is controlled by an interrupt signal. Specifically, the first interaction unit 120 includes an interrupt control register, and the interrupt control register is used for transmitting an interrupt signal, and the first processor 10 and the second processor 11 interact with each other through the interrupt signal. Further, the interrupt control register includes a first interrupt control register for transmitting the interrupt signal sent by the first processor 10 to the second processor 11 (i.e. transmitting the interrupt signal generated by the first processor 10), and a second interrupt control register for transmitting the interrupt signal sent by the second processor 11 to the first processor 10 (i.e. transmitting the interrupt signal generated by the second processor 11). Preferably, the first interrupt control register and the second interrupt control register are both thirty-two bit interrupt control registers.
Further, the first interaction unit 120 further includes a mailbox register, where the mailbox register includes a data register and a mutual exclusion lock, the data register is used to store a command for interaction between the first processor 10 and the second processor 11, and the mutual exclusion lock is used to latch the data register. Preferably, the number of the data registers is thirty two groups, and the number of the exclusive locks is thirty two groups, wherein thirty two groups of the data registers correspond to thirty two groups of the exclusive locks one to one. In the embodiment of the present application, the data register is latched by the exclusive lock, so that the first processor 10 and the second processor 11 are prevented from accessing the same data register at the same time, and a conflict of data access is avoided.
Specifically, when the first processor 10 sends a control command, the first processor 10 queries a mutex; the first processor 10 acquires an idle mutual exclusion lock, and marks the idle mutual exclusion lock as non-idle; the first processor 10 writes a control command into a data register corresponding to the acquired mutex; the first processor 10 generates an interrupt signal according to the acquired mutex; the first processor 10 releases the acquired mutex.
When the second processor 11 receives a control command, the second processor 11 receives an interrupt signal; the second processor 11 acquires a mutex lock according to the interrupt signal; the second processor 11 reads the control command in the corresponding data register according to the acquired mutex; the second processor 11 writes a reply command into the data register; the second processor 11 sets an interrupt signal; the second processor 11 releases the acquired mutex.
When the first processor 10 receives a reply command, the first processor 10 receives an interrupt signal; the first processor 10 acquires a mutex lock according to the interrupt signal; the first processor 10 reads a reply command in the corresponding data box according to the acquired mutex; the first processor 10 releases the acquired mutex.
Further, the command sent by the first processor 10 to the second processor 11 includes a DMA interrupt. In this embodiment of the present application, the second processor 11 is a DSP, and a conventional DSP cannot receive a DMA interrupt, where the first processor 10 sends the DMA interrupt to the second processor 11 in a manner of a command after detecting the DMA interrupt, so as to solve a problem that the conventional DSP cannot receive the DMA interrupt.
Further, the first processor 10 controls audio decoding of the second processor 11 by transmitting a control command to the first interactive unit 120, and the second processor 11 receives the control command from the first interactive unit 120, wherein the control command includes play, exit, pause, fast forward or fast reverse.
In the embodiment of the present application, the data buffer 13 is used for storing audio data to be decoded and decoded audio data. Specifically, the data buffer includes an input data buffer 130 and an output data buffer 131, where the input data buffer 130 is used for storing audio data to be decoded, and the output data buffer 131 is used for storing decoded audio data. Further, the output data buffer 131 is also used for storing audio information of the decoded audio data. The audio information may specifically comprise information such as channel, sampling rate or audio format, for use by the first processor 10 in further processing the decoded audio data.
In the embodiment of the application, the input data buffer area performs data writing through a first writing pointer and performs data reading through a first reading pointer; and the output data buffer zone writes data through a second write pointer and reads data through a second read pointer. That is, the writing of data and the reading of data are realized by different pointers, so that the reliability of the writing and reading of data can be ensured, and the data amount stored in the input data buffer area and the output data buffer area can be conveniently seen.
Further, the second processor 11 may also perform input of audio data to be decoded and output of decoded audio data using a chained DMA scheme. Thereby enabling the second processor 11 to have more channels to input audio data to be decoded and output decoded audio data; meanwhile, the device has higher data input and output speed.
In the embodiment of the present application, the first processor 10 and/or the second processor 11 may also be used for post-audio processing of the decoded audio data. Wherein the sound effect post-processing comprises performing some post-processing for improving sound effect quality on the decoded audio data, such as noise reduction, equalization, and the like. Further, the first processor 10 and/or the second processor 11 may be further configured to perform audio transcoding, recording, and/or playing on the decoded audio data; the first processor 10 is further configured to write the decoded audio data into an external storage medium or a sound box device for subsequent storage, playing, and the like.
Correspondingly, the embodiment also provides an audio decoding method. Specifically, please refer to fig. 2 and fig. 3, wherein fig. 2 is a schematic flowchart of an audio decoding method according to an embodiment of the present invention, and fig. 3 is a schematic flowchart of a control command interaction in the audio decoding method according to the embodiment of the present invention. As shown in fig. 2 and 3, the audio decoding method includes:
the method comprises the following steps: the first processor 10 transfers the audio data to be decoded to the second processor 11 through the data buffer 13 for processing; and
step two: the first processor 10 controls the audio decoding of the second processor 11 via an interaction unit 12.
In the embodiment of the present application, the order between the first step and the second step is not limited, that is, the first processor 10 transfers the audio data to be decoded to the second processor 11 through the data buffer 13 for processing, and the first processor 10 controls the audio decoding of the second processor 11 through the interaction unit 12 to be performed simultaneously; or the first processor 10 transfers the audio data to be decoded to the second processor 11 through the data buffer 13 for processing before the first processor 10 controls the audio decoding of the second processor 11 through the interaction unit 12; or the first processor 10 transfers the audio data to be decoded to the second processor 11 through the data buffer 13 for processing after the first processor 10 controls the audio decoding of the second processor 11 through the interaction unit 12.
Specifically, the controlling, by the first processor 10 through the interaction unit 12, the audio decoding by the second processor 11 includes: the first processor 10 sends a control command to the interaction unit 12, and the first processor 10 controls audio decoding by sending the control command; the second processor 11 receives a control command from the interactive unit 12 and processes audio data to be decoded according to the control command. In this embodiment of the present application, before the first processor 10 and the second processor 11 implement interaction through the interaction unit 12 and jointly implement audio decoding, that is, before the above step two is performed, the audio decoding method further includes: the first processor 10 starts the second processor 11 according to the memory address mapping stored by the interaction unit 12 (here, the second interaction unit 121) and operated by the second processor 11.
Wherein the sending of the control command to the interaction unit 12 by the first processor 10 comprises:
the first processor 10 queries a mutual exclusion lock (of the interaction unit 12);
the first processor 10 acquires an idle mutex lock (of the interaction unit 12) and marks the idle mutex lock as non-idle (the mutex lock may be marked as 1 herein);
the first processor 10 writes a control command into a data register corresponding to the acquired mutex;
the first processor 10 generates an interrupt signal (which may be referred to as a first interrupt signal herein) according to the acquired mutex;
the first processor 10 releases the acquired mutex (the mutex may be marked as 0 here).
Further, the second processor 11 receives a control command from the interaction unit 12, and processes the audio data to be decoded according to the control command, including:
the second processor 11 receives an interrupt signal (here, receives a first interrupt signal);
the second processor 11 acquires a mutex (which may be marked as 1 herein) according to the interrupt signal (i.e., the first interrupt signal);
the second processor 11 reads the control command in the corresponding data register according to the acquired mutex;
the second processor 11 writes a reply command into the data register;
the second processor 11 sets an interrupt signal (which may be referred to herein as a second interrupt signal);
the second processor 11 releases the acquired mutex (the mutex may be marked as 0 here).
Correspondingly, after the second processor 11 reads the control command in the corresponding data register according to the acquired mutex, the second processor 11 receives the control command from the interaction unit 12, and processes the audio data to be decoded according to the control command further includes: the second processor 11 reads the audio data to be decoded of the input data buffer; the second processor 11 decodes the read audio data to be decoded; the second processor 11 writes the decoded audio data to the output data buffer. Further, the second processor 11 also writes the audio information of the decoded audio data to the output data buffer. Wherein the second processor 11 updates the first read pointer aud _ rdptr after reading the audio data to be decoded, and the second processor 11 updates the second write pointer pcm _ wrptr after writing the decoded audio data to the output data buffer.
In other embodiments of the present application, after the second processor 11 reads the control command in the corresponding data register according to the acquired mutex, the receiving, by the second processor 11, the control command from the interaction unit 12, and processing the audio data to be decoded according to the control command may further include: the second processor 11 uses a chain DMA mode to input audio data to be decoded; the second processor 11 decodes the input audio data to be decoded; the second processor 11 performs output of the decoded audio data using a chain DMA method. That is, the second processor 11 may also perform input of audio data to be decoded and output of decoded audio data by other means.
Further, after the second processor 11 receives the control command from the interaction unit 12 and processes the audio data to be decoded according to the control command, the first processor 10 controls the audio decoding of the second processor 11 through the interaction unit 12 further includes: the first processor 10 receives a reply command from the interaction unit 12. The first processor 10 receiving a reply command from the interaction unit 12 comprises:
the first processor 10 receives an interrupt signal (i.e., a second interrupt signal);
the first processor 10 acquires a mutex lock according to the interrupt signal;
the first processor 10 reads a reply command in the corresponding data register according to the acquired mutex;
the first processor 10 releases the acquired mutex.
After the first processor 10 receives the reply command from the interaction unit 12, the audio decoding method further includes: the first processor 10 reads the decoded audio data of the output data buffer. Wherein the first processor 10 updates the second read pointer pcm rdptr upon reading decoded audio data of the output data buffer.
In an embodiment of the present application, after the first processor 10 reads the decoded audio data of the output data buffer, the audio decoding method may further include: the first processor 10 and/or the second processor 11 perform sound effect post-processing, audio transcoding processing, recording processing and/or playing processing on the decoded audio data; or the first processor 10 writes the decoded audio data to an external storage medium or the like.
In summary, in the audio decoding system and the audio decoding method provided in the embodiments of the present invention, the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing, and the first processor controls the audio decoding of the second processor through the interaction unit, and the two processors jointly implement the audio decoding to improve the decoding efficiency and the system real-time performance; the interaction between the two processors is realized through the interaction unit, the transmission of the audio data to be decoded is realized through the data buffer area, and the reliability of the audio decoding realized by the two processors together is ensured.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (32)
1. An audio decoding system, characterized in that the audio decoding system comprises: the system comprises a first processor, a second processor, an interaction unit and a data buffer area; wherein the content of the first and second substances,
the first processor transmits audio data to be decoded to the second processor through the data buffer for processing, and the first processor controls audio decoding of the second processor through the interaction unit;
the first processor transmits audio data to be decoded to the second processor through the data buffer area for processing, and controls the audio decoding of the second processor to be performed through the interaction unit; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing before the first processor controls the audio decoding of the second processor through the interaction unit; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing after the first processor controls the audio decoding of the second processor through the interaction unit;
the first processor controlling audio decoding of the second processor through the interaction unit includes: the first processor sends a control command to the interaction unit, and the first processor controls audio decoding by sending the control command; the second processor receives a control command from the interactive unit and processes audio data to be decoded according to the control command.
2. The audio decoding system of claim 1, wherein the interactive unit comprises a first interactive unit and a second interactive unit; the first interaction unit is used for realizing interaction between the first processor and the second processor; the second interaction unit is used for storing the memory address mapping operated by the second processor.
3. The audio decoding system of claim 2, wherein said first processor launches said second processor through said memory address map stored by said second interactive unit.
4. The audio decoding system of claim 2, wherein the first processor is further configured to reset the second processor.
5. The audio decoding system of claim 2, wherein the first interaction unit includes an interrupt control register for transmitting an interrupt signal by which the first processor and the second processor interact.
6. The audio decoding system of claim 5, wherein the interrupt control register comprises a first interrupt control register for transmitting the interrupt signal sent by the first processor to the second processor and a second interrupt control register for transmitting the interrupt signal sent by the second processor to the first processor.
7. The audio decoding system of claim 6, wherein the first interrupt control register and the second interrupt control register are each thirty-two bit interrupt control registers.
8. The audio decoding system of claim 5, wherein the first interactive unit further comprises a mailbox register, the mailbox register comprising a data register for storing commands for the first processor and the second processor to interact with and a mutual exclusion lock for latching the data register.
9. The audio decoding system of claim 8, wherein the mutex lock is configured to latch the data register comprises: when the first processor sends a control command, the first processor inquires a mutual exclusion lock; the first processor acquires an idle mutual exclusion lock and marks the idle mutual exclusion lock as non-idle; the first processor writes a control command into a data register corresponding to the acquired mutex; the first processor generates an interrupt signal according to the acquired mutex; and the first processor releases the acquired mutual exclusion lock.
10. The audio decoding system of claim 9, wherein the mutex lock is configured to latch the data register further comprising: when the second processor receives a control command, the second processor receives an interrupt signal; the second processor acquires a mutual exclusion lock according to the interrupt signal; the second processor reads a control command in the corresponding data register according to the acquired mutual exclusion lock; the second processor writes a reply command into the data register; the second processor sets an interrupt signal; and the second processor releases the acquired mutual exclusion lock.
11. The audio decoding system of claim 10, wherein the mutex lock is configured to latch the data register further comprising: when the first processor receives a reply command, the first processor receives an interrupt signal; the first processor acquires a mutual exclusion lock according to the interrupt signal; the first processor reads a reply command in the corresponding data box according to the acquired mutual exclusion lock; and the first processor releases the acquired mutual exclusion lock.
12. The audio decoding system of claim 8, wherein the number of said data registers is thirty-two groups and the number of said mutually exclusive locks is thirty-two groups, wherein thirty-two groups of said data registers and thirty-two groups of said mutually exclusive locks correspond one-to-one.
13. The audio decoding system of claim 8, wherein the command sent by the first processor to the second processor comprises a DMA interrupt.
14. The audio decoding system of claim 8, wherein the first processor controls audio decoding by the second processor by sending control commands including play, exit, pause, fast forward, or fast reverse.
15. The audio decoding system of claim 1, wherein the data buffer is for storing audio data to be decoded and decoded audio data.
16. The audio decoding system of claim 15, wherein the data buffer comprises an input data buffer for storing audio data to be decoded and an output data buffer for storing decoded audio data and audio information of the decoded audio data.
17. The audio decoding system of claim 16, wherein the input data buffer is written with data by a first write pointer and read with data by a first read pointer; and the output data buffer zone writes data through a second write pointer and reads data through a second read pointer.
18. The audio decoding system of claim 1, wherein the second processor performs input of audio data to be decoded and output of decoded audio data using a chained DMA manner.
19. The audio decoding system of claim 1, wherein the first processor and/or the second processor are further configured to perform post-sound processing, audio transcoding processing, recording processing, and/or playback processing on the decoded audio data.
20. The audio decoding system of claim 1, wherein the first processor is further configured to write the decoded audio data to a peripheral storage medium.
21. The audio decoding system of any of claims 1-20, wherein the first processor is a RISC and the second processor is a DSP.
22. An audio decoding method, characterized in that the audio decoding method comprises: the first processor transmits the audio data to be decoded to the second processor through the data buffer area for processing; the first processor controls the audio decoding of the second processor through an interaction unit;
the first processor transmits audio data to be decoded to the second processor through the data buffer area for processing, and controls the audio decoding of the second processor to be performed through the interaction unit; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing before the first processor controls the audio decoding of the second processor through the interaction unit; or the first processor transmits the audio data to be decoded to the second processor through the data buffer for processing after the first processor controls the audio decoding of the second processor through the interaction unit;
the first processor controlling audio decoding of the second processor through the interaction unit includes: the first processor sends a control command to the interaction unit, and the first processor controls audio decoding by sending the control command; the second processor receives a control command from the interactive unit and processes audio data to be decoded according to the control command.
23. The audio decoding method of claim 22, wherein the first processor sending a control command to the interactive unit comprises:
the first processor inquires a mutual exclusion lock;
the first processor acquires an idle mutual exclusion lock and marks the idle mutual exclusion lock as non-idle;
the first processor writes a control command into a data register corresponding to the acquired mutex;
the first processor generates an interrupt signal according to the acquired mutex;
and the first processor releases the acquired mutual exclusion lock.
24. The audio decoding method of claim 23, wherein the second processor receives a control command from the interactive unit and processes the audio data to be decoded according to the control command comprises:
the second processor receives an interrupt signal;
the second processor acquires a mutual exclusion lock according to the interrupt signal;
the second processor reads a control command in the corresponding data register according to the acquired mutual exclusion lock;
the second processor writes a reply command into the data register;
the second processor sets an interrupt signal;
and the second processor releases the acquired mutual exclusion lock.
25. The audio decoding method of claim 24, wherein after the second processor reads the control command in the corresponding data register according to the acquired mutex, the second processor receives the control command from the interactive unit, and processes the audio data to be decoded according to the control command further comprises:
the second processor reads audio data to be decoded of an input data buffer;
the second processor decodes the read audio data to be decoded;
the second processor writes the decoded audio data and audio information of the decoded audio data to the output data buffer.
26. The audio decoding method of claim 24, wherein after the second processor reads the control command in the corresponding data register according to the acquired mutex, the second processor receives the control command from the interactive unit, and processes the audio data to be decoded according to the control command further comprises:
the second processor inputs audio data to be decoded by using a chain DMA mode;
the second processor decodes the input audio data to be decoded;
the second processor performs output of the decoded audio data using a chained DMA manner.
27. The audio decoding method of claim 25, wherein after the second processor receives a control command from the interactive unit and processes audio data to be decoded according to the control command, the first processor controls audio decoding of the second processor through the interactive unit further comprises:
the first processor receives a reply command from the interaction unit.
28. The audio decoding method of claim 27, wherein the first processor receiving a reply command from the interactive unit comprises:
the first processor receives an interrupt signal;
the first processor acquires a mutual exclusion lock according to the interrupt signal;
the first processor reads a reply command in the corresponding data register according to the acquired mutual exclusion lock;
and the first processor releases the acquired mutual exclusion lock.
29. The audio decoding method of claim 28, wherein after the first processor receives a reply command from the interactive unit, the audio decoding method further comprises:
the first processor reads decoded audio data of an output data buffer.
30. The audio decoding method of claim 29, wherein after the first processor reads the decoded audio data of the output data buffer, the audio decoding method further comprises:
and the first processor and/or the second processor perform sound effect post-processing, audio transcoding processing, recording processing and/or playing processing on the decoded audio data.
31. The audio decoding method of claim 29, wherein after the first processor reads the decoded audio data of the output data buffer, the audio decoding method further comprises:
the first processor writes the decoded audio data to a peripheral storage medium.
32. The audio decoding method of any one of claims 22-31, wherein before the first processor controls audio decoding by the second processor through an interaction unit, the audio decoding method further comprises:
and the first processor starts the second processor through the memory address mapping stored in the second interaction unit.
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