CN117826125A - Detection circuit, driving method thereof and single-photon laser radar - Google Patents

Abstract

The disclosure provides a detection circuit, a driving method thereof and a single-photon laser radar. The detection circuit includes N input sub-circuits and an output sub-circuit. N input sub-circuits, N being an integer greater than 1; the N input sub-circuits are connected in parallel and have the same structure; the input sub-circuit of the N input sub-circuits, which receives the optical signal for the first time, is a setting input sub-circuit, and the setting input sub-circuit is configured to output a first electric signal in response to the optical signal. The output sub-circuit is electrically connected with the output ends of the N input sub-circuits; the output sub-circuit is configured to receive the first electrical signal and output a time window signal. In the case where different input sub-circuits are used as the setting input sub-circuits, the time periods between the time point at which the setting input sub-circuits receive the optical signal and the time point at which the output sub-circuits output the time window signal are equal. The distance measurement performance of the single-photon laser radar can be improved.

Description

Detection circuit, driving method thereof and single-photon laser radar

Technical Field

The invention relates to the field of laser radars, in particular to a detection circuit, a driving method thereof and a single-photon laser radar.

Background

Lidar is a commonly used system for detecting distance. The laser radar works on the principle that information such as detection distance is obtained by transmitting an optical signal to a target object and then processing the received optical signal reflected from the target object and the transmitted optical signal.

Currently, in the case that different receivers in the lidar receive the optical signal reflected from the target object, the starting time of the time window signal has different delay times relative to the time of receiving the reflected optical signal, so that the finally obtained detection distance has an error.

Disclosure of Invention

The application provides a detection circuit, a driving method thereof and a single-photon laser radar, which can improve the ranging performance of the single-photon laser radar.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, a detection circuit is provided. The detection circuit includes N input sub-circuits and an output sub-circuit. N input sub-circuits, N being an integer greater than 1; the N input sub-circuits are connected in parallel and have the same structure; the input sub-circuit of the N input sub-circuits, which receives the optical signal for the first time, is a setting input sub-circuit, and the setting input sub-circuit is configured to output a first electric signal in response to the optical signal. The output sub-circuit is electrically connected with the output ends of the N input sub-circuits; the output sub-circuit is configured to receive the first electrical signal and output a time window signal. In the case that different input sub-circuits are used as the setting input sub-circuits, the time periods between the time point when the setting input sub-circuits receive the optical signal and the time point when the output sub-circuits output the time window signal are equal.

In a possible implementation manner, the input sub-circuit includes a first transistor, a control terminal of the first transistor receives the optical signal, an input terminal of the first transistor receives a reference signal, and an output terminal of the first transistor is electrically connected with the output sub-circuit.

In a possible implementation, the output sub-circuit includes a nor gate, which includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input end of the nor gate receives a reset signal, the second input end of the nor gate receives an inverted signal of an enable signal, and the third input end of the nor gate is electrically connected with the output ends of the N input sub-circuits.

In a possible implementation manner, the nor gate includes: three second transistors and three third transistors. The control ends of the three second transistors are respectively used for receiving the reset signal, the enable signal and the output ends of the N input sub-circuits and are electrically connected with each other, the input ends of the three second transistors are respectively used for receiving the reference signals, and the output ends of the three second transistors are respectively electrically connected with the output ends of the NOR gate. The control ends of the three third transistors are respectively used for receiving the reset signal, the enabling signal and the N input subcircuits and are electrically connected with the output ends of the N input subcircuits; the three third transistors are sequentially connected in series, the input end of one third transistor of the two third transistors positioned at two ends receives a power supply signal, and the output end of the other third transistor is electrically connected with the output end of the NOR gate.

In a possible implementation, the channel types of the three second transistors are opposite to the channel types of the three third transistors.

In a possible implementation, the detection circuit further includes an inverter. An input end of the inverter receives an enabling signal, and an output end of the inverter is electrically connected with a second input end of the NOR gate.

In a possible implementation, the detection circuit further includes a reset sub-circuit. The reset sub-circuit is electrically connected with the N input sub-circuits and the output sub-circuit; the reset sub-circuit is configured to receive a reset signal, a reference signal and a power signal, and transmit the power signal to the output ends of the N input sub-circuits under the control of the reset signal and the reference signal so as to reset the N input sub-circuits and the output sub-circuits.

In a possible implementation, the reset sub-circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The control end of the fourth transistor receives the reset signal, and the input end of the fourth transistor receives the reference signal. The control end of the fifth transistor is electrically connected with the output end of the fourth transistor, the input end of the fifth transistor receives the power supply signal, and the output end of the fifth transistor is electrically connected with the output ends of the N input sub-circuits. The control end of the sixth transistor is electrically connected with the output ends of the N input subcircuits, the input end of the sixth transistor receives the power supply signal, and the output end of the sixth transistor is electrically connected with the output end of the fourth transistor.

In a possible implementation manner, the channel type of the fifth transistor is the same as the channel type of the sixth transistor, and the channel type of the fourth transistor is opposite to the channel types of the fifth transistor and the sixth transistor. The channel type of the first transistor is the same as the channel type of the fourth transistor.

In a second aspect, a driving method of a detection circuit is provided, which is applied to the detection circuit. The driving method includes a setting input sub-circuit in the detection circuit outputting a first electrical signal in response to an optical signal. The setting input sub-circuit is an input sub-circuit which receives an optical signal for the first time in N input sub-circuits of the detection circuit. An output sub-circuit of the detection circuit receives the first electric signal and outputs a time window signal.

In a possible implementation, the start time of the time window signal is delayed by a set time relative to the first occurrence time of the optical signal. When each input sub-circuit is used as the setting input sub-circuit, one setting time is corresponding to each input sub-circuit, and the setting times corresponding to the N input sub-circuits are equal.

In a possible implementation manner, in a case that the detection circuit includes a reset sub-circuit, the driving method further includes, before the optical signal is received for the first time, transmitting a power signal to the output terminals of the N input sub-circuits by the reset sub-circuit under the control of the reset signal and the reference signal, and resetting the N input sub-circuits and the output sub-circuit.

In a third aspect, a single photon lidar is provided. The single photon lidar includes a transmitter, a receiver and a processor. The transmitter and the receiver are respectively connected with the processor; the transmitter is used for transmitting optical signals; the receiver comprises the detection circuit, and is used for receiving the reflected optical signal and outputting the time window signal; the processor determines a detection distance based on the emitted light signal, the reflected light signal, and the time window signal.

Drawings

FIG. 1 is a timing diagram of a detection circuit in some embodiments generating different time windows in the event that different input subcircuits receive optical signals;

fig. 2 is a schematic structural diagram of a single-photon lidar according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a detection circuit according to some embodiments of the present disclosure;

FIG. 4 is a timing diagram of a detection circuit provided by some embodiments of the present disclosure generating different time windows in the event that different input subcircuits receive optical signals;

fig. 5 is a schematic diagram of a nor gate in a detection circuit according to some embodiments of the present disclosure;

fig. 6 is a schematic diagram of a nor gate in a detection circuit according to some embodiments of the present disclosure;

FIG. 7 is a flow chart of a method of driving a detection circuit provided in some embodiments of the present disclosure;

fig. 8 is a flowchart of a driving method of a detection circuit according to some embodiments of the present disclosure.

Detailed Description

For ease of understanding, related terms and concepts related to embodiments of the present application are described first below.

A laser radar (Light Detection And Ranging, liDAR), is an acronym for laser detection and ranging system. Is a radar using a laser as a radiation source. Lidar is a product of a combination of laser technology and radar technology. The working principle is as follows: the transmitter transmits the optical signal, the optical signal is reflected by the target object and then is received by the receiver, and the distance between the laser radar and the target object is obtained by measuring the time difference between the sending time and the receiving time of the optical signal.

The mainstream lidar systems typically employ APDs as core detectors. When the bias voltage of the APD is lower than the avalanche voltage of the APD, the APD works in a linear mode which has a linear amplification effect on incident photoelectrons, and at the moment, the APD performs equal gain amplification on the input photoelectrons to form continuous current, so that a laser continuous optical signal with time information is obtained. When the bias voltage of the APD is higher than the avalanche voltage of the APD, the gain of the APD increases rapidly, and at the moment, the output current of the detector can be saturated by single photon absorption, which is called a geiger mode, and the APD working in the geiger mode is called a single photon avalanche diode (Single Photon Avalanche, SPAD) which can detect single photons and output pulse signals.

Based on the characteristics of SPAD (space imaging detector) for detecting single photons and outputting pulse signals, the received photons can be counted by recording the pulse number output by the SPAD detector, and the size of the optical signals can be represented by the photon count per unit time, so that the extraction of the intensity and time information of the optical signals is completed. Therefore, the SPAD detector has the remarkable advantages of high gain, high sensitivity and quick response in laser radar application, and the photon counting laser radar technology based on SPAD can accurately detect objects with low reflectivity (such as tires or pedestrians wearing black clothes) in a long distance so as to remarkably improve the detection rate and the accuracy of target detection.

The input sub-circuit 211 may receive many noise light signals while receiving the reflected light signals, and we often set a threshold decision for all the light signals, i.e. the total number of light signals exceeds a certain threshold, which is considered to be the light signal caused by the reflection of the light signal, and perform optical path measurement, whereas it is considered to be the noise light signal, and not perform optical path measurement. The threshold decision needs to be made within a time Window (Window) whose time Window width (twin) needs to be relatively stable.

The time window width may be understood as a duration for which the active level is sustained in the case where the threshold detection signal is switched from an inactive level signal (e.g., a low level signal) to an active level signal (e.g., a high level signal).

In the case of stable time window width, the received photons can be counted by recording the number of pulses output by the SPAD detector. And counting the received photons under the time window, and when the count reaches a threshold value, considering the optical signal to be detected which is being judged as the reflected optical signal. When the count does not reach the threshold value, the optical signal to be detected which is being judged is considered to be optical noise.

As shown in fig. 1, in some embodiments, the input sub-circuit may receive the reflected back optical signal, and when the reflected back optical signal received by the input sub-circuit 1 is received as the first one of all the input sub-circuits, the time window, after the first delay time td1 of the circuit has elapsed, presents a start time of the time window at time t1, and presents an end time of the time window at time t 3. When the reflected optical signal received by the input sub-circuit 2 is received as the first of all the input sub-circuits, the time window, after the circuit delay second delay time td2 has elapsed, presents a start time of the time window at time t2 and presents an end time of the time window at time t 4. It can be found that when different input sub-circuits are used as the setting input sub-circuits, the delay time is not the same (i.e. the jitter of the window time), so that the time window for performing the threshold value determination is greatly deviated due to the difference of the setting input sub-circuits, as shown in the two cases, the finally obtained detection distance has at least random jitter of td1-td2, which is difficult to calibrate in the later stage, will become a random error of the laser radar system, and seriously affect the ranging performance of the system.

Based on the detection circuit, a driving method thereof and a single-photon laser radar are provided. When different input subcircuits in the receiver of the single-photon laser radar receive the optical signals, the time difference between the time of receiving the optical signals and the starting time of the time window is stable, so that the ranging performance of the single-photon laser radar can be improved.

Single-photon lidar 100 may be understood as a lidar using SPAD as a detector. As shown in fig. 2, the single photon lidar 100 includes a transmitter 10, a receiver 20, and a processor 30. The transmitter 10 and the receiver 20 are connected to a processor 30, respectively. The transmitter 10, the receiver 20 and the processor 30 may be connected by a cable or may be connected by communication. The communication connection may include, but is not limited to, any of optical communication, wireless communication, bluetooth communication, infrared communication.

The transmitter 10 may be configured to transmit an optical signal of a first polarization state under control of the processor 30. The optical signal is used for single photon lidar 100 detection.

The receiver 20 may be configured to detect and photon count the return optical signal, which is a reflected optical signal of the optical signal transmitted by the transmitter 10, using a first polarization state that is the same as the polarization state of the optical signal transmitted by the transmitter 10, under control of the processor 30.

The processor 30 may be comprised of a micro control unit (micro controller unit, MCU), advanced reduced instruction set machine (advanced reduced instruction set computing machine, ARM) or the like, or complex programmable logic devices (complex programmable logic device, CPLAD), field programmable gate array (field programmable gate array, FPGA) or the like.

The processor 30 may apply different amounts of force to the transmitter 10 or the receiver 20 by a motor to adjust the polarization state of the transmitter 10 or the receiver 20. Alternatively, the processor 30 may send instructions (code) to the transmitter 10 or the receiver 20 by way of software to adjust the polarization state of the transmitter 10 or the receiver 20.

As shown in fig. 3 and 4, in some embodiments. The receiver 20 comprises a detection circuit 21, the detection circuit 21 comprising N input sub-circuits 211 and an output sub-circuit 212. The N input sub-circuits 211 are connected in parallel and have the same structure, N being an integer greater than 1. Each input subcircuit 211 is configured to output an electrical signal in response to an optical signal. Since each input sub-circuit 211 has the same structure, the time period from the receiving of the optical signal to the outputting of the electrical signal by the different input sub-circuits 211 is equal.

The time sequence of receiving the optical signals by the different input sub-circuits 211 is different, the input sub-circuit 211 that receives the optical signals for the first time in the N input sub-circuits 211 is a set input sub-circuit, and the set input sub-circuit 211 is configured to output the first electrical signal in response to the optical signals. The output sub-circuit 212 is electrically connected to the N input sub-circuits 211. The output subcircuit 212 is configured to receive the first electrical signal and output a time window signal.

Since only one output sub-circuit 212 receives the first electrical signal and outputs the time window signal, the time taken for each process of receiving the first electrical signal to outputting the time window signal is also equal.

In this way, in the case where the different input sub-circuits 211 are set input sub-circuits, the time periods between the time point at which the set input sub-circuits receive the optical signal and the time point at which the output sub-circuits output the time window signal are equal. It will be appreciated that the time duration (i.e. the delay time duration) taken by each input sub-circuit to output the time window signal from the received optical signal to the output sub-circuit is equal, which can overcome the problem of time window jitter.

Illustratively, an input sub-circuit 211 of the N input sub-circuits 211 that receives an optical signal for the first time refers to an input sub-circuit 211 of all input sub-circuits 211 that receives an optical signal for the first time. At this time, the input sub-circuit 211 receiving the optical signal is the set input sub-circuit 211.

Each input subcircuit 211 is identical in structure and may include an equal number of transistors. Illustratively, when each input subcircuit 211 includes a transistor. The control terminal of each input sub-circuit 211 may be configured to receive an optical signal, and the input terminal of each input sub-circuit 211 may be configured to receive a ground signal GND. The output of each input subcircuit 211 may be connected to the same input of the output subcircuit 212.

In the case where the detection circuit of the receiver 20 is capable of providing a time window without a time window jitter problem, the processor 30 can accurately determine the detection distance of the object to be detected based on the optical signal emitted by the emitter 10, and the optical signal reflected back by the receiver 20 and the output time window signal.

The principle of the detection circuit 21 will be described below in connection with an embodiment in which the detection circuit 21 comprises eight input sub-circuits 211.

Illustratively, in operation of the single-photon lidar 100, assuming that the single-photon lidar 100 receives an optical signal, a first input sub-circuit 211 of the eight input sub-circuits 211 (shown as input sub-circuit 3 in fig. 4) is the input sub-circuit 211 that receives the optical signal first of all the input sub-circuits 211. That is, the first input sub-circuit 211 is a set input sub-circuit. While the remaining input sub-circuits 211 may receive the optical signal after the first input sub-circuit 211 receives the optical signal.

Since the first input sub-circuit 211 is electrically connected to the output sub-circuit 212, the first input sub-circuit 211 receives the optical signal, then outputs a first electrical signal, and transmits the first electrical signal to the output sub-circuit 212, and then the output sub-circuit 212 outputs a time window signal. The time difference between the time when the input of the first input sub-circuit 211 receives the optical signal and the start time of the time window signal output by the output sub-circuit 212 is td3 (hereinafter referred to as delay time difference).

When the single photon lidar 100 does not receive the optical signal, all of the input sub-circuits 211 do not output, and the output sub-circuit 212 outputs an invalid signal.

Illustratively, when the single-photon lidar 100 is operating, it is assumed that when the single-photon lidar 100 receives an optical signal, a third input sub-circuit 211 (which is input sub-circuit 4 in fig. 4) of the eight input sub-circuits 211 is the input sub-circuit 211 that receives the optical signal first of all the input sub-circuits 211. That is, the third input sub-circuit 211 is a set input sub-circuit. The remaining input sub-circuits 211 may receive the optical signal after the third input sub-circuit 211 receives the optical signal.

Since the third input sub-circuit 211 is electrically connected to the output sub-circuit 212, the third input sub-circuit 211 receives the optical signal, and then outputs the first electrical signal, and the first electrical signal is transmitted to the output sub-circuit 212, and then the output sub-circuit 212 outputs the time window signal. Wherein the delay difference between the time when the detection circuit detects the optical signal and the start time of the output sub-circuit 212 outputting the time window signal is td3.

Similarly, when the single-photon lidar 100 does not receive an optical signal, all of the input sub-circuits 211 do not output, and the output sub-circuit 212 outputs an invalid signal.

Because the respective input sub-circuits 211 in the detection circuit 21 are identical in structure, and the respective input sub-circuits 211 are arranged in parallel. Therefore, when the different input sub-circuits 211 of the single-photon lidar 100 receive the optical signals, the delay amounts generated by the first electrical signals transmitted to the output sub-circuits through the different input sub-circuits 211 are equal, so that the delay difference between the time when the optical signals are received and the starting time of the time window signals output by the output sub-circuits 212 is td3. In this way, when any one of the input sub-circuits 211 of the detection circuit 21 receives an optical signal, the delay difference between the time at which the optical signal is received and the start time of the time window signal output by the output sub-circuit 212 is equal.

The above arrangement reduces or even eliminates the phenomenon that the delay difference between the time when the optical signal is received and the starting time of the time window signal output by the output sub-circuit 212 is unequal due to different structures, and improves the accuracy of measuring the distance of the target object by the single photon laser radar 100.

Note that, in the case where one of the input sub-circuits 211 is used as the setting input sub-circuit, the other input sub-circuits 211 may still continue to receive the optical signal and output the electrical signal to the output sub-circuit 212 according to the reflection of the actual optical signal, which is not limited herein.

In some embodiments, the input subcircuit 211 includes a first transistor having a control terminal receiving the optical signal, an input terminal receiving the reference signal, and an output terminal electrically coupled to the output subcircuit 212.

Illustratively, the reference signal may be a common voltage signal, a ground signal GND, or the like. In the embodiment shown in fig. 3, the input of the first transistor receives a ground signal.

When the setting input sub-circuit 211 operates normally, the control terminal of the first transistor receives the optical signal, and the first transistor is in a conductive state. Since the input terminal of the first transistor receives the ground signal, the output terminal of the first transistor inputs a low level signal. The output based on the first transistor is electrically connected to the output subcircuit 212, and thus the input of the output subcircuit 212 receives a low level signal.

When the control terminal of the first transistor does not receive the optical signal, the first transistor is in an off state, and the output terminal of the first transistor does not output the signal, so the output terminal of the output sub-circuit 212 does not receive the signal of the output terminal of the first transistor.

Thus, the signal received at the input of the output sub-circuit 212 may be controlled by controlling the signal received at the control terminal of the first transistor, thereby controlling the output signal of the output sub-circuit 212.

Note that, since the respective input sub-circuits 211 in the detection circuit 21 have the same structure, the first transistor is included in each of the input sub-circuits 211.

In the related art, each input sub-circuit in the detection circuit includes a plurality of transistors, resulting in a large number of transistors inside the detection circuit and the single-photon lidar. In the present embodiment, the number of transistors of each input sub-circuit 211 in the detection circuit can be reduced, thereby reducing the cost of the detection circuit and the single-photon lidar 100, and facilitating the miniaturization design of the single-photon lidar 100.

In some embodiments, as shown in fig. 3, output subcircuit 212 includes a nor gate. The nor gate includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input of the nor gate receives the reset signal, the second input of the nor gate receives the inverted signal of the enable signal, and the third input of the nor gate is electrically connected to the N input sub-circuits 211.

Illustratively, the detection circuit 21 includes eight input subcircuits 211. In operation of the single-photon lidar 100, the first input sub-circuit 211 outputs a valid signal (for example, a low level) assuming that the first input sub-circuit 211 receives an optical signal, and at this time, a third input terminal electrically connected to the first input sub-circuit 211 receives the low level signal. Because the second input terminal receives the inverted signal of the enable signal, for example, when the enable signal is a high level signal, the inverted signal of the enable signal appears as a low level signal. That is to say the second input receives a low signal. At this time, the first input terminal may receive a reset signal of a low potential, that is, the first input terminal receives a low level signal. According to the operation principle of the nor gate, the output sub-circuit 212 outputs a high level, and the starting time of the time window signal occurs.

When the first input end continuously receives the optical signal, the continuously received photons can be counted under the time window, and the count is judged. When the count reaches the threshold value, the optical signal to be measured being determined can be considered as the reflected optical signal. When the count does not reach the threshold value, the optical signal to be measured being determined can be considered as optical noise.

The nor gate outputs a high level signal and an inactive signal, respectively. After the nor gate outputs the high level signal each time, and before the next high level signal is output, the first input terminal receives a reset signal once, and resets the third input terminal.

When the nor gate is in the reset phase, the first input terminal receives a reset signal and outputs a high level signal. The second input terminal still receives the inverted signal of the enable signal and outputs a low level signal. The third input terminal cannot receive the optical signal at this time because of the influence of the reset signal, and at this time, the third input terminal does not output the signal.

By analogy, the output sub-circuit 212 enters a reset phase after receiving the signal output from the input sub-circuit 211, and then receives the signal output from the input sub-circuit 211.

As shown in fig. 5, in some embodiments, the nor gate includes three second transistors and three third transistors. The control ends of the three second transistors respectively receive the reset signal, the enable signal and the output ends of the N input subcircuits, the input ends of the three second transistors can receive the reference signal, and the output ends of the three second transistors are electrically connected with the output ends of the NOR gate. The control ends of the three third transistors are respectively and correspondingly electrically connected with the first input end, the second input end and the third input end. The three third transistors are sequentially connected in series, the input end of one third transistor of the two third transistors positioned at two ends receives a power supply signal, and the output end of the other third transistor is electrically connected with the output end of the NOR gate.

For ease of illustration, the description is provided herein in connection with the particular embodiment shown in FIG. 4.

The effective level for turning on the second transistor is different from the effective level for turning on the third transistor, so that the third transistor is in an off state when the second transistor is in an on state. Conversely, when the third transistor is in an on state, the second transistor is in an off state.

As shown in fig. 5, the nor gate includes three first second transistors, second transistors, and third second transistors connected in parallel in order. The paths of the first second transistor, the second transistor and the third second transistor for transmitting signals to the output end are equal. Because the three second transistors are arranged in parallel, when the types of signals received by the input ends of each second transistor are the same, the types of signals output by the output ends of the corresponding second transistors are the same.

When the control terminal of any one of the three second transistors receives an optical signal, for example, the second transistor is turned on, since the input terminal of the second transistor receives a reference signal (ground signal), the output terminal of the second transistor outputs a low level signal, that is, the third input terminal of the nor gate receives a low level signal.

The nor gate further comprises three third transistors connected in series in sequence, wherein the control ends of the three third transistors are respectively used for receiving a reset signal, an enable signal and are electrically connected with the output ends of the N input sub-circuits. The input end of one third transistor of the two third transistors positioned at two ends receives a power supply signal, and the output end of the other third transistor is electrically connected with the output end of the NOR gate. Illustratively, the three third transistors include a first third transistor, a second third transistor, and a third transistor. The input end of the first third transistor can receive an enabling signal, the control end of the first third transistor can receive a reset signal, and the output end of the first third transistor can be electrically connected with the input end of the second third transistor. The control terminal of the second third transistor may be configured to receive a reset signal, and the output terminal of the second third transistor may be electrically connected to the input terminal of the third transistor. The control end of the third transistor can be electrically connected with the output ends of the N input subcircuits, and the output end of the third transistor can be electrically connected with the output end of the NOR gate.

When the three third transistors are in an on state, one third transistor receiving a power signal (e.g., a high level signal) can input the high level signal to the next third transistor, and then the high level signal is sequentially transmitted to the output terminal of the nor gate through the three third transistors, so that the output terminal of the nor gate can output the high level signal.

In this way, the output of the output sub-circuit 212 may be controlled to output the time window signal by controlling the optical signal received from the first input terminal, the ground signal received from the second input terminal, and the reset signal received from the third input terminal.

In some embodiments, the channel types of the three second transistors are opposite to the channel types of the three third transistors. One of the second transistor and the third transistor may be a PMOS transistor, and the other may be an NMOS transistor, so that the selection range of the second transistor and the third transistor may be enlarged. Illustratively, in the example shown in fig. 4, the second transistor may be an NMOS transistor and the third transistor may be a PMOS transistor.

In some embodiments, as shown in fig. 6, the detection circuit 21 further includes an inverter. An input of the inverter receives the enable signal and an output of the inverter is electrically connected to a second input of the nor gate.

When the enable signal is a high level signal, the input end of the inverter receives the high level signal, and the output end of the inverter outputs a low level signal, because the second input end of the nor gate is electrically connected with the output end of the inverter, the second input end of the nor gate outputs a low level signal.

Similarly, when the enable signal is a low level signal, the input terminal of the inverter receives the low level signal, and the output terminal of the inverter outputs a high level signal, because the second input terminal of the nor gate is electrically connected to the output terminal of the inverter, the second input terminal of the nor gate outputs a high level signal.

As shown in fig. 3, in some embodiments, the detection circuit 21 further includes a reset sub-circuit 213. The reset sub-circuit 213 is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212. The reset subcircuit 213 is configured to receive a reset signal, a reference signal, and a power signal. Under control of the reset signal and the reference signal, a power signal is transmitted to the N input sub-circuits 211 and the output sub-circuits 212 to reset the N input sub-circuits 211 and the output sub-circuits 212.

When the reset subcircuit 213 receives a reset signal, a first component within the reset subcircuit 213 can be in an on state. The reference signal (low level signal) can be received based on one end of the component, and thus the other end of the component can output the low level signal, so that the reset sub-circuit 213 can receive the power signal and transmit the power signal to the output ends of the N input sub-circuits 211, thereby realizing the reset.

In some embodiments, the reset subcircuit 213 includes a fourth transistor, a fifth transistor, and a sixth transistor. The control end of the fourth transistor receives the reset signal, and the input end of the fourth transistor receives the reference signal. The control terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, the input terminal of the fifth transistor receives the power signal, and the output terminal of the fifth transistor is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212. The control terminal of the sixth transistor is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212, the input terminal of the sixth transistor receives the power signal, and the output terminal of the sixth transistor is electrically connected to the output terminal of the fourth transistor.

When the control end of the fourth transistor receives the reset signal, the fourth transistor is in a conducting state, the input end of the fourth transistor can receive the reference signal, and the output end of the fourth transistor can output the reference signal. Since the control terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, the fifth transistor can be in an on state at this time. The input terminal of the fifth transistor can receive the power supply signal, so that the output terminal of the fifth transistor can output the power supply signal at the moment. Since the output terminal of the fifth transistor is electrically connected to the N input sub-circuits 211, the first input terminal of the N input sub-circuits 211 can receive the power signal at this time, so that the N input sub-circuits 211 cannot receive the optical signal, thereby realizing the reset.

When the control terminal of the fourth transistor does not receive the reset signal, the input terminal of the fourth transistor receives the disable signal, and at this time, the fourth transistor is in an off state, so that the output terminal of the fourth transistor cannot output the reference signal. At this time, the N input sub-circuits 211 can receive optical signals. The control terminal of the sixth transistor is electrically connected to the N input sub-circuits 211, and thus the sixth transistor is in an on state at this time. Since the input terminal of the sixth transistor receives the power signal, the output terminal of the sixth transistor may output the power signal. Since the output terminal of the fourth transistor is electrically connected to the output terminal of the sixth transistor, and the output terminal of the fourth transistor is in an off state, the output terminal of the fourth transistor cannot output the reference signal, so that the control terminal of the fifth transistor cannot receive the reference signal, and further, the turn-on of the fifth transistor is realized, and then, the output terminal of the fifth transistor cannot naturally output the power signal.

In some embodiments, the channel type of the fifth transistor is the same as the channel type of the sixth transistor, and the channel type of the fourth transistor is opposite to the channel types of the fifth transistor and the sixth transistor. The channel type of the first transistor is the same as the channel type of the fourth transistor.

One of the fourth transistor and the fifth transistor may be a PMOS transistor, and the other may be an NMOS transistor. Illustratively, in the example shown in fig. 3, the first transistor and the fourth transistor may be NMOS transistors, and the fifth transistor and the sixth transistor may be PMOS transistors, thereby expanding the selection range of components such as the fourth transistor.

Some embodiments of the present disclosure provide a driving method of the detection circuit 21, which is applied to the detection circuit 21. As shown in fig. 7, the driving method includes the steps of:

step S210: the setting input sub-circuit 211 in the detection circuit 21 outputs a first electric signal in response to the optical signal; the input sub-circuit 211 is set as the input sub-circuit 211 that receives the optical signal for the first time among the N input sub-circuits 211 of the detection circuit 21.

Step S220: the output sub-circuit 212 of the detection circuit 21 receives the first electrical signal and outputs a time window signal.

The input sub-circuit 211 that receives the optical signal for the first time among the N input sub-circuits 211 in the detection circuit 21 is a set input sub-circuit. The setting input sub-circuit is capable of outputting a first electrical signal when receiving an optical signal, and is further capable of transmitting the first electrical signal to the output sub-circuit 212 through an output terminal of the setting input sub-circuit, so that the output sub-circuit 212 outputs a time window signal based on the first electrical signal.

Since the respective input sub-circuits 211 are connected in parallel with each other and are equal in structure, the time at which the input of any one of the input sub-circuits 211 receives the optical signal is equal to the time difference (i.e., delay time difference) between the start times of outputting the time window signal based on the first electric signal by the output sub-circuit 212. Thus, the problem of different delay differences caused by different input sub-circuits 211 receiving the optical signal for the first time can be overcome, so that no matter which input sub-circuit 211 receives the optical signal during each ranging, the delay differences are stable, and the accuracy of measuring the distance of the target object by the single photon laser radar 100 is improved.

In some embodiments, the first input sub-circuit 211 that detects an optical signal may be the set input sub-circuit among all the input sub-circuits 211. The output sub-circuit outputs the time window signal with a delay difference td3.

Because the respective input sub-circuits 211 in the detection circuit 21 are identical in structure, and the respective input sub-circuits 211 are arranged in parallel. When each input sub-circuit 211 is used as a setting input sub-circuit 211, a setting time is corresponding to each input sub-circuit 211, and setting times corresponding to the N input sub-circuits 211 are equal. That is, the delay amounts generated by the transmission of the first electric signal to the output sub-circuit through the different input sub-circuits 211 are equal, so that the delay differences of the starting moments in the time window signals output by the output sub-circuit 212 are td3.

In this way, when any of the input sub-circuits 211 of the detection circuit 21 receives the optical signal, the delay difference of the occurrence start time in the time window signal output by the output sub-circuit 212 may be td3. That is, when any one of the input sub-circuits 211 of the detection circuit 21 receives the optical signal, the delay difference at the occurrence start time in the time window signal output by the output sub-circuit 212 is equal.

In some embodiments, as shown in fig. 8, in the case where the detection circuit 21 includes the reset sub-circuit 213, the driving method further includes step S230 before step S210.

Step S230: the reset sub-circuit 213 transmits a power signal to the N input sub-circuits 211 and the output sub-circuits 212 under control of the reset signal and the reference signal, and resets the N input sub-circuits 211 and the output sub-circuits 212.

As shown in fig. 3, in some embodiments, the detection circuit 21 further includes a reset sub-circuit 213. The reset sub-circuit 213 is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212. The reset subcircuit 213 is configured to receive a reset signal, a reference signal, and a power signal. Under control of the reset signal and the reference signal, a power signal is transmitted to the N input sub-circuits 211 and the output sub-circuits 212 to reset the N input sub-circuits 211 and the output sub-circuits 212.

When the reset subcircuit 213 receives a reset signal, a first component within the reset subcircuit 213 can be in an on state. The reference signal (low level signal) can be received based on one end of the component, and thus the other end of the component can output the low level signal, so that the reset sub-circuit 213 can receive the power signal and transmit the power signal to the output ends of the N input sub-circuits 211, thereby realizing the reset.

In some embodiments, the reset subcircuit 213 includes a fourth transistor, a fifth transistor, and a sixth transistor. The control end of the fourth transistor receives the reset signal, and the input end of the fourth transistor receives the reference signal. The control terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, the input terminal of the fifth transistor receives the power signal, and the output terminal of the fifth transistor is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212. The control terminal of the sixth transistor is electrically connected to the N input sub-circuits 211 and the output sub-circuit 212, the input terminal of the sixth transistor receives the power signal, and the output terminal of the sixth transistor is electrically connected to the output terminal of the fourth transistor.

When the control end of the fourth transistor receives the reset signal, the fourth transistor is in a conducting state, the input end of the fourth transistor can receive the reference signal, and the output end of the fourth transistor can output the reference signal. Since the control terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, the fifth transistor can be in an on state at this time. The input terminal of the fifth transistor can receive the power supply signal, so that the output terminal of the fifth transistor can output the power supply signal at the moment. Since the output terminal of the fifth transistor is electrically connected to the N input sub-circuits 211, the first input terminal of the N input sub-circuits 211 can receive the power signal at this time, so that the N input sub-circuits 211 cannot receive the optical signal, thereby realizing the reset.

When the control terminal of the fourth transistor does not receive the reset signal, the input terminal of the fourth transistor receives the disable signal, and at this time, the fourth transistor is in an off state, so that the output terminal of the fourth transistor cannot output the reference signal. At this time, the N input sub-circuits 211 can receive optical signals. The control terminal of the sixth transistor is electrically connected to the N input sub-circuits 211, and thus the sixth transistor is in an on state at this time. Since the input terminal of the sixth transistor receives the power signal, the output terminal of the sixth transistor may output the power signal. Since the output terminal of the fourth transistor is electrically connected to the output terminal of the sixth transistor, and the output terminal of the fourth transistor is in an off state, the output terminal of the fourth transistor cannot output the reference signal, so that the control terminal of the fifth transistor cannot receive the reference signal, and further, the turn-on of the fifth transistor is realized, and then, the output terminal of the fifth transistor cannot naturally output the power signal.

Before the input sub-circuits 211 receive the optical signals, they are reset by the reset circuit, so as to prepare for the detection circuit 21 to receive the optical signals next time, so that each input sub-circuit 211 can output the first electrical signal to the output sub-circuit based on the detected optical signals in time.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (13)

1. A detection circuit, comprising:

n input sub-circuits, N being an integer greater than 1; the N input sub-circuits are connected in parallel and have the same structure; the input sub-circuit which receives the optical signal for the first time in the N input sub-circuits is a setting input sub-circuit, and the setting input sub-circuit is configured to respond to the optical signal and output a first electric signal;

the output sub-circuit is electrically connected with the output ends of the N input sub-circuits; the output sub-circuit is configured to receive the first electrical signal and output a time window signal;

in the case that different input sub-circuits are used as the setting input sub-circuits, the time periods between the time point when the setting input sub-circuits receive the optical signal and the time point when the output sub-circuits output the time window signal are equal.

2. The detection circuit of claim 1, wherein the input sub-circuit comprises a first transistor, a control terminal of the first transistor receiving the optical signal, an input terminal of the first transistor receiving a reference signal, an output terminal of the first transistor being electrically connected to the output sub-circuit.

3. The detection circuit of claim 1, wherein the output sub-circuit comprises a nor gate comprising a first input, a second input, a third input, and an output;

the first input end of the nor gate receives a reset signal, the second input end of the nor gate receives an inverted signal of an enable signal, and the third input end of the nor gate is electrically connected with the output ends of the N input sub-circuits.

4. A detection circuit according to claim 3, wherein the nor gate comprises:

the control ends of the three second transistors are respectively and correspondingly electrically connected with the first input end, the second input end and the third input end, the input ends of the three second transistors all receive reference signals, and the output ends of the three second transistors are all electrically connected with the output end of the NOR gate;

Three third transistors, wherein the control ends of the three third transistors are respectively and correspondingly electrically connected with the first input end, the second input end and the third input end; the three third transistors are sequentially connected in series, the input end of one third transistor of the two third transistors positioned at two ends receives a power supply signal, and the output end of the other third transistor is electrically connected with the output end of the NOR gate.

5. The detection circuit of claim 4, wherein the channel types of the three second transistors are opposite to the channel types of the three third transistors.

6. The detection circuit of claim 3, wherein the detection circuit further comprises:

and the input end of the inverter receives an enabling signal, and the output end of the inverter is electrically connected with the second input end of the NOR gate.

7. The detection circuit according to any one of claims 1 to 6, characterized in that the detection circuit further comprises:

a reset sub-circuit electrically connected to the N input sub-circuits and the output sub-circuit; the reset sub-circuit is configured to receive a reset signal, a reference signal and a power signal, and transmit the power signal to the output ends of the N input sub-circuits under the control of the reset signal and the reference signal so as to reset the N input sub-circuits and the output sub-circuits.

8. The detection circuit of claim 7, wherein the reset sub-circuit comprises:

a fourth transistor, wherein a control end of the fourth transistor receives the reset signal, and an input end of the fourth transistor receives the reference signal;

a fifth transistor, wherein a control end of the fifth transistor is electrically connected with an output end of the fourth transistor, an input end of the fifth transistor receives the power supply signal, and an output end of the fifth transistor is electrically connected with output ends of the N input subcircuits;

and the control end of the sixth transistor is electrically connected with the output ends of the N input subcircuits, the input end of the sixth transistor receives the power supply signal, and the output end of the sixth transistor is electrically connected with the output end of the fourth transistor.

9. The detection circuit according to claim 8, wherein a channel type of the fifth transistor is the same as a channel type of the sixth transistor, and wherein a channel type of the fourth transistor is opposite to channel types of the fifth transistor and the sixth transistor;

the channel type of the first transistor is the same as the channel type of the fourth transistor.

10. A driving method of a detection circuit, characterized by being applied to the detection circuit according to any one of claims 1 to 9; the driving method includes:

a setting input sub-circuit in the detection circuit responds to the optical signal and outputs a first electric signal; the setting input sub-circuit is an input sub-circuit which receives an optical signal for the first time in N input sub-circuits of the detection circuit;

an output sub-circuit of the detection circuit receives the first electric signal and outputs a time window signal.

11. The driving method according to claim 10, wherein a start timing of the time window signal is delayed by a set time with respect to a first occurrence timing of the optical signal;

when each input sub-circuit is used as the setting input sub-circuit, one setting time is corresponding to each input sub-circuit, and the setting times corresponding to the N input sub-circuits are equal.

12. The driving method according to claim 10 or 11, wherein in the case where the detection circuit includes a reset sub-circuit, the driving method further includes: before the first time an optical signal is received,

the reset sub-circuit transmits a power signal to the output ends of the N input sub-circuits under the control of a reset signal and a reference signal, and resets the N input sub-circuits and the output sub-circuits.

13. The single-photon laser radar is characterized by comprising a transmitter, a receiver and a processor, wherein the transmitter and the receiver are respectively connected with the processor; the transmitter is used for transmitting optical signals; the receiver comprising a detection circuit according to any one of claims 1 to 9, the receiver being arranged to receive the reflected light signal and to output the time window signal; the processor determines a detection distance based on the emitted light signal, the reflected light signal, and the time window signal.