CN114624724A

CN114624724A - Adjusting circuit, photoelectric detector, photoelectric detection array and optical system

Info

Publication number: CN114624724A
Application number: CN202011466514.8A
Authority: CN
Inventors: 姚廷宇; 王陈銮; 向少卿
Original assignee: Hesai Technology Co Ltd
Current assignee: Hesai Technology Co Ltd
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2022-06-14

Abstract

A conditioning circuit, photodetector array, and optical system, the conditioning circuit adapted to cooperate with the photodetector, the photodetector adapted to receive a laser pulse to produce a first pulse combination, the conditioning circuit comprising: a regulating unit adapted to receive said first pulse combination and to sample only the arrival time, Wt, of a first one of said first pulse combination for a predetermined time_pulseThe preset time is less than or equal to 5W_pulseIn the formula W_pulseIs the pulse width of the laser pulse.

Description

Adjusting circuit, photoelectric detector, photoelectric detection array and optical system

Technical Field

The invention relates to the field of electricity, in particular to a regulating circuit, a photoelectric detector, a photoelectric detection array and an optical system.

Background

The Time-of-Flight (ToF) is the mainstream laser ranging technology at present, and the principle is that a laser is used to actively project a light beam, the light beam is reflected by the surface of a target and then received by a detector, and the distance from the target to a ranging device can be obtained by calculating the back-and-forth Time-of-Flight t in the process based on the speed of light c: and z is ct/2. Among them, d-ToF (direct time-of-flight) is a commonly used ToF technique, that is, a time difference between transmission and reception of an optical pulse is directly measured. Due to laser safety limitations and product power consumption limitations, lasers emit pulses of limited energy but need to cover the entire field of view. The energy density of the light pulse decreases by more than a trillion-fold upon reflection back to the detector. At the same time, ambient light acts as noise, interfering with the detection and recovery of the signal by the detector. In this case, the signal-to-noise ratio obtained by the detector is not sufficient to directly recover the analog signal of the pulse, which in turn leads to a large error in directly measuring the time of flight. Therefore, the d-ToF method requires a photodetector with extremely high sensitivity to detect weak optical signals.

A Single Photon Avalanche Diode (SPAD) is an Avalanche photodiode that operates in geiger mode. When the reverse bias voltage at the two ends of the SPAD is larger than the avalanche breakdown voltage, the field intensity of the internal electric field is extremely high, the kinetic energy obtained by the photon-generated carriers is very large, and the avalanche multiplication effect can continuously occur in collision ionization. Therefore, a single photon can saturate the avalanche photodiode with photocurrent. The SPAD has extremely high gain and sensitivity, is often used for single photon detection, and has great advantages in the field of laser ranging.

The core technology of d-ToF ranging by SPAD is Time-correlated single photon counting (TCSPC), which is based on the basic idea that photons are regarded as a random event, and are counted after repeated measurement for multiple periods. When the optical signal is very weak and the detection frequency is very high, photons may not be detected in some periods, a photon can be detected in some periods, the detection time of the photon is corresponding to a certain time period, thus after a large number of repeated measurements are carried out, the frequency distribution histogram of the photon changing along with the time can be obtained by counting the number of the photons in each time period, and the intensity change of the optical signal can be obtained by fitting the histogram. And the highest position of the optical signal intensity is taken as a pulse peak value, the corresponding time at the position is taken as pulse return time, and the pulse return time is subtracted by the emission time to obtain the ToF time.

However, the existing SPAD is made by using a CMOS process, and there is a large deviation under different temperatures and process angles, which causes the SPAD parameters to deviate from the set values. Especially, when an SPAD is triggered twice possibly caused by a received laser pulse, two avalanche signals are output, and the operation amount of a signal reading circuit and the system power consumption are greatly increased. Moreover, if the number of SPADs that are triggered again at the falling edge of the laser pulse is large, the photon frequency corresponding to the falling edge of the pulse on the histogram may be high, and double peaks may occur during fitting, which may cause misjudgment of the peak position and distance.

Disclosure of Invention

The invention solves the problem that the existing photoelectric detector is easy to generate performance parameter deviation.

To solve the above problem, the present invention provides a regulating circuit, which is suitable for cooperating with a photodetector. The photodetector is adapted to receive the laser pulses to produce a first pulse combination, comprising: a regulating unit adapted to receive said first pulse combination and to sample only the arrival time, Wt, of a first one of said first pulse combination for a predetermined time_pulseThe preset time is less than or equal to 5W_pulseIn the formula W_pulseIs the pulse width of the laser pulse.

The invention also provides a data processing chip, comprising: the above-described conditioning circuit adapted to cooperate with one or more photodetectors.

The invention also provides a photoelectric detector which is suitable for being matched with the regulating circuit. The photodetector includes: a photoelectric conversion unit adapted to generate the first pulse combination in response to the one laser pulse.

The present invention also provides a photodetection array comprising: a plurality of rows and a plurality of columns; each row and each column are respectively provided with a plurality of photoelectric detection units, and each photoelectric detection unit comprises at least one photoelectric detector; the adjusting circuit is coupled with one or more photodetectors in one photodetector unit.

The present invention also provides an optical system comprising: a light emitting module comprising: a light emitting array including a plurality of rows and a plurality of columns; wherein, each row and each column are respectively provided with a plurality of light emitting units, and each light emitting unit comprises at least one light emitter; the light emitting array further comprises a light emitting array driving circuit coupled to each of the light emitters for emitting a detection laser beam; and the optical detection module comprises the photoelectric detection array and is used for receiving detection echoes.

Compared with the prior art, the technical scheme of the invention has the following advantages:

when one photodetector is triggered multiple times in response to a received laser pulse, multiple first pulses are generated, and if subsequent distance determination is performed based on the multiple first pulses, the amount of calculation of a subsequent signal reading circuit is increased, and distance misdetermination may occur. The regulating unit provided by the invention generates a second pulse corresponding to the first pulses for subsequent processing based on the first pulses, so that the shortest time interval of the output signals can be accurately controlled, the misjudgment of the pulses in the subsequent processing is avoided, the operation amount and the power consumption of a subsequent signal reading circuit are reduced, and the accuracy of distance judgment is improved.

Drawings

FIG. 1 is a schematic diagram of a SPAD quench and reset circuit;

FIG. 2 is a schematic diagram of detection effects of different dead times

FIG. 3 is a schematic diagram of a SPAD area array chip;

FIG. 4 is a schematic diagram of a conditioning circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the waveform of the correlation signal of the present invention;

FIG. 6 is a block diagram of the configuration of the conditioning circuit of the present invention in cooperation with a photodetector; FIG. 7 is a schematic diagram of a conditioning circuit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a conditioning circuit according to yet another embodiment of the present invention;

FIG. 9 is a schematic diagram of a current-output type analog-to-digital converter according to the present invention;

FIG. 10 is a schematic diagram of the connection between the photodetecting unit and the data processing chip according to the present invention;

fig. 11 is a schematic structural view of the optical system of the present invention.

Detailed Description

In order to find the cause of the intensity compensation or the distance judgment error, the inventor has further studied the photodetector:

photons enter the SPAD to excite avalanche, and in order to ensure the normal operation of the SPAD, a special circuit is arranged to control the reverse bias voltage of the SPAD to be reduced below avalanche breakdown voltage so as to quench the avalanche; the SPAD is then controlled to reset such that its reverse bias returns to an initial state above the avalanche breakdown voltage to detect the following photon. The SPAD cannot sense other photons during the time from the onset of avalanche quenching to the end of reset, called dead time (dead time).

For example, as shown in fig. 1, the SPAD quench and reset circuit may include a passive quench circuit, SPAD, and a resistor Rs. The passive quenching circuit is a quenching resistor RL. Before the photons arrive, the SPAD is reverse biased to Vp, which is now in the state to be detected. Once photons reach the SPAD, photon-generated carriers are excited, the carriers are guided to the avalanche multiplication region under the action of an internal electric field, avalanche can be triggered, the instantly increased avalanche current causes great voltage drop on the quenching resistance RL, the voltage at two ends of the SPAD is reduced to be lower than breakdown voltage, and avalanche is quenched. And then, the voltage Vp charges the two ends of the SPAD, so that the SPAD is restored to a state to be detected, and the next photon is continuously detected.

In the application of laser ranging, the scheme that a single SPAD device is used as a pixel brings obvious noise interference, noise factors such as dark counts and ambient light are difficult to distinguish from effective signals, and the relative application effect is poor. Therefore, a plurality of SPAD devices are usually used as one pixel, that is, a plurality of SPADs are connected in parallel to one readout circuit to read distance information, and through certain condition judgment, noise filtering can be realized, and effective signals can be obtained more accurately. Meanwhile, a plurality of pixels are arranged in a certain array to form an area array SPAD detector, so that the photosensitive surface of the detector can be enlarged to increase the range of a detectable field of view.

Referring to fig. 1 and 2, a is a laser pulse received by a photodetector (e.g., an echo laser pulse received by the photodetector after a transmitted pulse is reflected by a target), and a typical full width at half maximum is several nanometers, and a difference between a rising edge start time and a falling edge end time of the laser pulse is defined as a pulse width of the laser pulse. After the emission pulse is reflected by the target object, the echo laser pulse shown in fig. 2a is emitted to the SPAD photosurface to trigger SPAD avalanche, and the output end Vout outputs an avalanche signal shown in fig. 2 b. The time difference between the echo pulse and the transmit pulse is determined as the time of flight (TOF) from the SPAD trigger time. By measuring the time of flight, the distance to the target object can be calculated. After the output of the detection signal b, the SPAD cannot be triggered again because of the effect of the dead time. SPAD can avalanche again after avalanche, recovery. In a detection window, namely the total time of carrying out repeated measurement on a certain field range for multiple times, counting the number of SPAD avalanches in each time period of each measurement, then superposing the results of repeated measurement for multiple times to obtain a histogram of the number of photons changing along with time, and fitting the histogram to obtain the echo pulse waveform. Wherein, the time at the peak is taken as the arrival time of the echo signal.

The dead time of the SPAD is determined by a quenching and resetting circuit integrated on an SPAD detector area array, and large deviation exists under different temperatures and processes. The area array SPAD has a large area, and the circuit lengths between the SPAD units at different positions and circuit elements such as a voltage source are greatly different, so that the dead times of the SPADs at different positions are not uniform. In particular, if the dead time of the SPAD is smaller than the pulse width of the received laser pulse, the reset is completed before the laser pulse is ended, and the SPAD is recovered to the detection state, then the SPAD may be triggered once by the rising edge of the laser pulse, and then triggered again by the falling edge of the pulse, and the output terminal Vout outputs two avalanche signals as shown in fig. 2 c. That is, a laser pulse received by the detector causes the SPAD to be triggered twice, which easily causes the photon frequency of the corresponding pulse falling edge in the histogram to be too high, and the echo signal is wrongly judged as the double peak shown in fig. 2d in the subsequent fitting process, thereby causing errors in ToF judgment and distance calculation.

In addition, if the dead time is too small, when the ambient light is strong, the SPAD may generate very high frequency triggering, the noise signal is too strong, the system computation amount and power consumption are increased, and even the system response speed may be exceeded, resulting in data loss.

In the front-illuminated SPAD array, front-end circuits such as quenching and resetting are arranged around the SPAD photosensitive surface on the surface of the chip (the direction perpendicular to the paper surface is inward the light incidence direction) as shown in fig. 3, so that a certain chip area is occupied. In order to improve the fill factor (SPAD photosensitive surface area/total chip area) and ensure the detection efficiency, too much area can not be reserved for preparing a circuit, so that the difficulty degree of adding a circuit for adjusting or controlling the dead time function on the SPAD detector area array is very high.

Based on the above studies, the inventors propose a regulating circuit that can be fitted with a photodetector. The photodetector is adapted to receive the laser pulses to produce a first pulse combination.

The regulation circuit includes: a regulating unit adapted to receive said first pulse combination and to sample only the arrival time, Wt, of a first one of said first pulse combination for a predetermined time_pulseThe preset time is less than or equal to 5W_pulseIn the formula W_pulseIs the pulse width of the laser pulse.

In particular, the adjusting unit is adapted to output a second pulse corresponding to an arrival time of a first pulse of the first pulse combination, a first abrupt change edge of the second pulse corresponding to a first abrupt change edge of the first pulse.

When the photodetector is triggered multiple times due to one laser pulse, multiple first pulses are generated, and if subsequent data accumulation, histogram formation, and distance determination are performed based on the multiple first pulses, an erroneous result will be generated. The adjusting unit provided by the invention only records and outputs the first pulse arrival time within the preset time, and the preset time is not less than W_pulseNamely the pulse width of the laser pulse, so that the misjudgment of the pulse in the subsequent processing can be avoided, the power consumption of the system is reduced, and the accuracy of distance judgment is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The present embodiment also provides a photodetector that cooperates with the conditioning circuit. The photodetector includes a photoelectric conversion unit. The photoelectric conversion unit may generate a first Pulse combination Pulse-1 in response to one laser Pulse. The photoelectric conversion unit may be an avalanche diode. More specifically, the photoelectric conversion unit may be spad(s).

The following description will be made with reference to fig. 4 and 5, taking an example in which the photoelectric conversion unit is a SPAD (not shown) and the first Pulse combination Pulse-1 includes two first pulses. Namely, the first Pulse combination Pulse-1 includes: a first pulse p11 and a second first pulse p 12. The first and second first pulses are generated before and after the relative timing, and the first pulse p11 is generated more ahead of the second first pulse p 12. Both p11 and p12 are named first pulses because both pulse signals are signals generated by the laser pulses reflected by the target and received by the photodetector.

The regulation circuit includes: an output signal supply unit 1 and a reset unit 2. The output signal providing unit 1 generates the second Pulse-2 based on the reset Pulse-r and the first Pulse p 11. The reset unit 2 may generate the reset Pulse-r according to the second Pulse-2.

Wherein the output signal providing unit 1 generates a first burst edge of the second Pulse-2 according to the first burst edge of the first Pulse p11, and generates a second burst edge of the second Pulse signal Pulse-2 based on the first burst edge of the reset Pulse-r. The first abrupt edge of the first pulse p11 corresponds to the trigger time of the SPAD. The output signal providing unit 1 generates the first sharp edge of the second Pulse-2 according to the first sharp edge of the first Pulse p11, and the first sharp edge of the second Pulse-2 also corresponds to the triggering time of the SPAD.

The first Pulse and the second Pulse-2 may both be positive pulses, and the reset Pulse-r may be negative pulses. The first abrupt change edge of the first pulse is a rising edge, and the second abrupt change edge of the first pulse is a falling edge. And the first abrupt change edge of the second Pulse-2 is a rising edge, and the second abrupt change edge of the second Pulse-2 is a falling edge. And the first abrupt change edge of the reset Pulse-r is a falling edge, and the second abrupt change edge of the reset Pulse-r is a rising edge. The abrupt edge of the pulse may be characterized by the arrival time or the ending time of the pulse, and in other embodiments, may be characterized in other ways.

Fig. 6 is a block diagram of the structure of the adjusting circuit and the photodetector.

The input end of the regulating circuit is coupled to the output end of the SPAD and is suitable for receiving a first Pulse combination Pulse-1 generated by the SPAD; the output end of the adjusting circuit is coupled to the signal readout circuit, the Pulse-2 is output to the signal readout circuit, the signal readout circuit acquires a first sudden change edge of the Pulse-2, namely SPAD trigger time, and stores data such as SPAD trigger time in each time period of multiple measurements and the number of triggered SPADs, and performs subsequent processing such as histogram generation.

As an implementable manner, the output signal providing unit 1 may include: a bi-stable circuit. The first input terminal of the bi-stable circuit is adapted to receive a first positive voltage VDD. The second input terminal of the bistable circuit is suitable for receiving the first Pulse combination Pulse-1. The reset terminal of the bistable circuit is suitable for receiving the reset Pulse-r. And the output end of the bistable circuit is suitable for outputting the second Pulse-2. The first positive voltage VDD may be a power supply voltage.

More specifically, the bi-stable circuit may employ a D flip-flop. The input D of the D flip-flop is adapted to receive a first positive voltage VDD. The clock signal terminal clk of the D flip-flop is suitable for receiving the first Pulse combination Pulse-1. The reset end rst of the D trigger is suitable for receiving the reset Pulse-r. And the output end Q of the D trigger is suitable for outputting the second Pulse-2.

Since the input terminal D of the D flip-flop receives the first positive voltage VDD, when the clock signal terminal clk of the D flip-flop receives the rising edge of the pulse signal, the output terminal Q of the D flip-flop starts outputting a high level; when the reset end rst of the D trigger receives a reset pulse, the D trigger is reset, and the output end Q of the D trigger starts to output a low level; thus, the output Q of the D flip-flop can generate a pulse signal.

In combination with the above principle, after the SPAD is triggered, the output terminal of the SPAD outputs the first Pulse combination Pulse-1. When the clock signal terminal clk of the D flip-flop receives the rising edge of the first Pulse p11, the output terminal Q of the D flip-flop starts outputting a high level, i.e., generates the rising edge of the second Pulse-2. And then the output end Q of the D trigger maintains high level until the reset end rst of the D trigger receives the falling edge of the reset Pulse-r, the D trigger starts to be reset, and the output end Q of the D trigger starts to output low level, namely the falling edge of the second Pulse-2 is generated. Thus, the output Q of the D flip-flop outputs a complete second Pulse-2.

During the duration (low level duration) of the reset Pulse-r, no matter what level signal is input to the clock signal terminal clk of the D flip-flop, if a second first Pulse p12 is input subsequently, the output terminal Q of the D flip-flop is not affected to keep outputting at a low level. Therefore, the D flip-flop generates the second Pulse-2 only according to the first Pulse p11 and the reset Pulse-r during the time from the rising edge of the second Pulse-2 to the end of the reset, and does not generate an unnecessary Pulse signal according to the second first Pulse p 12. Optionally, the time from the rising edge of the second Pulse-2 to the end of resetting is not less than the Pulse width of the laser Pulse, so that the generation of the double peak phenomenon can be further ensured to be avoided.

In the process, the D trigger does not respond to any input pulse in the reset stage, and the effect is similar to the effect that the SPAD does not sense other photons in the dead time and outputs the trigger signal, so the adjusting unit of the embodiment can achieve the effect of prolonging the SPAD dead time, and the problems that the dead time of the SPAD is smaller than the pulse width of the laser pulse, the operation speed of a rear end circuit is insufficient, data are lost and the like can be avoided. Furthermore, the dead time of the SPAD can be adjusted by setting the time of the reset Pulse-r, so that the function of adjusting the dead time is realized.

The dead time determined by the regulating circuit is not less than the pulse width of the laser pulseIn this case, the dead time cannot be increased infinitely, otherwise the detection accuracy is reduced, and even the adjusting unit cannot output the avalanche signal generated by triggering the SPAD by the subsequent echo signal, so that data loss and detection failure are caused. In this embodiment, the preset time, that is, the time from the rising edge of the second Pulse-2 to the end of the reset of the D flip-flop, is less than or equal to 5W_pulseOn one hand, when the photoelectric detector receives other echo laser pulses, the adjusting circuit can output corresponding SPAD trigger time, and on the other hand, when the ambient light is strong, the dead time is prolonged to be not less than W_pulseAnd is less than or equal to 5W_pulseWhen the ambient light causes the SPAD to trigger frequently to generate excessive noise signals, the data volume output to the signal reading circuit by the adjusting circuit is reduced, and the system operation amount is reduced on the basis of not losing the detection precision.

Specifically, the reset unit 2 generates a first burst edge of the reset Pulse-r according to the first burst edge of the second Pulse-2. The reset unit 2 may include: a control unit 21, a capacitive storage unit 22 and a reset signal providing unit 23.

The control unit 21 generates one of a charging signal and a discharging signal according to a first burst edge of the second Pulse-2, and generates the other of the charging signal and the discharging signal according to a second burst edge of the second Pulse-2. The capacitive storage element 22 may charge and discharge its own stored charge in accordance with the charge signal and the discharge signal. The reset signal supply unit 23 may generate the reset Pulse-r after the voltage of the capacitive memory cell 22 reaches a threshold voltage.

In a specific embodiment, the control unit 21 may include: PMOS pipe P1, NMOS pipe N1 and resistance unit.

The source electrode of the PMOS tube P1 is suitable for being connected with a first positive voltage VDD, and the grid electrode of the PMOS tube P1 is connected with the grid electrode of the NMOS tube N1 and is suitable for receiving the second Pulse-2. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1, the capacitive storage unit 22 and the reset signal providing unit 23. The source electrode of the NMOS pipe N1 is connected with the resistance unit. The first positive voltage VDD may be a power supply voltage. The resistance unit may be a resistance R1 or a variable resistance.

The capacitive memory cell 22 may be a capacitor C1, a first terminal of the capacitor C1 is connected to the drain of the PMOS transistor P1, and a second terminal of the capacitor C1 is grounded or at a relatively low voltage level.

The reset signal supply unit 23 includes an even number of inverters connected in series, and an output terminal of the last inverter is adapted to output the reset pulse. For example, fig. 3 shows a reset signal supply unit 23 composed of 2 inverters. The input end of the first inverter is connected with the drain electrode of the PMOS pipe P1, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is suitable for generating the reset Pulse-r.

With continued reference to fig. 5, when the D flip-flop starts outputting a high level based on the rising edge of the first pulse P11, the gate of the NMOS transistor N1 is at a high level, the gate-source voltage is greater than the turn-on voltage, so that the NMOS transistor N1 is turned on, and the PMOS transistor P1 is turned off. At this time, the NMOS transistor N1, the resistor R1 and the capacitor C1 form a discharge path, the capacitor C1 starts to discharge, and the voltage V1 across the capacitor C1 starts to gradually decrease at a rate that depends on the capacitance value of the capacitor C1 and the resistance value of the resistor R1.

When the voltage V1 on the capacitor C1 is lowered to the inversion threshold of the inverters, a falling edge of the reset Pulse-r is generated after the two inverters pass, and the reset Pulse-r is maintained at a low level. The low level reset Pulse-r is input to the clock signal terminal clk of the D flip-flop, so that the D flip-flop enters a reset state, the output terminal Q of the D flip-flop generates a falling edge of the second Pulse-2, and then the output terminal Q of the D flip-flop is kept at a low level. At this time, the gate of the PMOS transistor P1 is turned on by the low level, the NMOS transistor N1 is turned off, and the voltage V1 across the capacitor C1 starts to rise. Since the equivalent resistance of the PMOS transistor P1 is small, the voltage V1 on the capacitor C1 can be quickly restored to a high level. After passing through the two inverters, a rising edge of the reset Pulse-r of a low level is generated, thereby ending the reset Pulse-r. And after the reset Pulse-r is finished, the D trigger enters a working state and recovers the trigger response.

The time difference from the rising edge of the D trigger output Pulse-2 to the rising edge of the reset Pulse-r is the discharge time tau of the capacitor from VDD to the inversion threshold of the inverter, and the time delay delta t of the two stages of inverters is added; the difference between the rising edge time and the falling edge time of the reset Pulse-r is the delay delta t of the two-stage inverter. Therefore, the time difference of the D flip-flop from the rising edge of the output Pulse-2 to the falling edge of the reset Pulse-r is tau +2 delta t, and the time is the minimum time interval of two adjacent second pulses output by the regulating circuit.

The time of 2 at compared to τ is negligible and the minimum time interval between two adjacent second pulses of the output of the regulating circuit is about the capacitor discharge. In the present embodiment, the inversion threshold of the inverter is VDD/2, and the time required for the corresponding capacitor to discharge from VDD to VDD/2 is about 0.7RC, i.e., τ is 0.7RC, where R is the resistance of the resistor unit and C is the capacitance of the capacitive storage unit 22. The matching degree and the process precision of the resistor and the capacitor are far higher than those of a CMOS device, so that the dead time of the SPAD determined by the adjusting circuit can be kept at a stable value, the controllability of the dead time is enhanced, and the dead time deviation caused by the process is avoided. The output end of each SPAD unit on the area array SPAD chip is coupled with an adjusting circuit, and the deadtime consistency of the SPAD units at different positions on the area array SPAD chip can be improved. The values of R and C can be calculated according to the deadtime of the system design.

The resistance unit of another embodiment of the present application may include a variable resistor R2, as shown in fig. 7.

When the resistance unit adopts the variable resistor R2, the dead time is determined by the resistance value of the variable resistor R2 when the capacitance value C of the capacitive memory cell is constant. When the resistance value of the variable resistor R2 is increased, the deadtime of the SPAD is lengthened, so that the effect of avoiding the double peak problem can be improved; when the resistance value of the variable resistor R2 is reduced, the deadtime corresponding to the SPAD is shortened. The capacitance value C is determined in the design and preparation processes of the regulating circuit, after the circuit element is prepared, the capacitance value C cannot be regulated, and the resistance value of the variable resistor R2 can be regulated according to actual requirements in the use process of the circuit, so that the dead time determined by the regulating circuit is changed.

In fact, the SPA determined in the regulating circuitWhen the D dead time is larger than the pulse width of the laser pulse, the smaller the dead time is, the better the dead time is, so that the follow-up detection signal can be ensured not to be lost. However, when the ambient light is strong, even if there is no echo laser pulse, the ambient light still causes frequent triggering of the SPAD, and these triggering signals are noise, which increases the data processing amount of the system and reduces the signal-to-noise ratio. Therefore, the dead time can be increased to not more than 5W by changing the variable resistor R2 in the present embodiment_pulseThe dead time can be flexibly adjusted according to the ambient light intensity condition in the detection process, so that the signal output quantity of the regulating circuit is reduced when the ambient light is too strong, the system operation quantity can be reduced, the power consumption is reduced, and the signal to noise ratio can be improved.

As shown in fig. 8, in another specific embodiment, the control unit 21 may include: PMOS pipe P1, NMOS pipe N1 and current output type analog-to-digital converter DAC.

The source electrode of the PMOS tube P1 is suitable for being connected with a first positive voltage VDD, and the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube N1 and is suitable for receiving the second Pulse-2. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor, the capacitive storage element 22 and the reset signal providing element 23. The source electrode of the NMOS pipe N1 is connected with the current output type analog-to-digital converter DAC.

Fig. 8 is an equivalent diagram of a current-output type analog-to-digital converter DAC.

The current output type analog-to-digital converter DAC includes: a reference branch and an output branch. The reference branch and the output branch are both composed of MOS tubes and switches. The reference branch comprises an MOS tube Mr, and the output branch comprises an MOS tube M1, an MOS tube M2, an MOS tube M3 and an MOS tube M4. For a given reference branch current I_rOutput current I₀And reference branch current I_rThe relationship of (1) is:

in formula 2, (W/L)₀The width and length parameters of the MOS tube in the reference branch are shown, (W/L)_rRepresenting MOS tubes in output branchesWidth and length parameters.

According to actual needs, the width and length parameters of the MOS transistor M1, the MOS transistor M2, the MOS transistor M3 and the MOS transistor M4 can be set to be different. By closing the switch, switching between different MOS tubes can be realized, and different output currents I can be obtained₀。

Similar to the previous embodiment, the difference between the time of the flip-flop D of this embodiment from the rising edge of the output Pulse-2 to the falling edge of the reset Pulse-r is τ +2 Δ t, which is the minimum time interval between two adjacent second pulses output by the regulating circuit. In the present embodiment, the inversion threshold of the inverter is VDD/2, the time for the capacitor to discharge to VDD/2 is determined by the amount of charge and the discharge current, i.e., (0.5VDD × C)/I, I is the output current value of the current output type analog-to-digital converter DAC, and C is the capacitance value of the capacitive storage unit 22.

When the voltage value of the first positive voltage VDD and the capacitance value of the capacitive storage unit 22 are constant, the dead time is determined by the output current value of the current output type analog-to-digital converter DAC. Therefore, different output currents can be obtained by switching different MOS tubes in the current output type analog-to-digital converter DAC, and switching at different dead time values can be realized.

The dead time is adjusted by adjusting the output current of the current output type analog-to-digital converter DAC, which discharges the charge on the capacitive storage unit 22 to generate a delay.

It can be seen from the above description that the adjusting circuit provided in this embodiment can achieve the effect of adjusting the dead time of the SPAD, and when the ambient light is too strong and the trigger frequency is too high, the signal-to-noise ratio is reduced, the number of trigger events can be effectively reduced, and detection errors caused by insufficient system response speed are avoided. In the laser radar system based on the SPAD detector, the dead time of the SPAD is not less than the pulse width of the laser pulse, so that the phenomena of double peaks and the like of a detection result can be avoided.

The embodiment of the invention also provides a data processing chip which is suitable for the SPAD array. As shown in fig. 10, the SPAD array includes a plurality of rows and a plurality of columns, each row and each column are respectively provided with a plurality of photodetecting units, and each photodetecting unit includes one or more SPADs. When one photodetecting unit includes a plurality of SPADs, the plurality of SPADs may be connected to the same signal readout circuit to be used as one pixel. In the application of ToF measurement, the signal readout circuit usually includes a time To Digital Converter (TDC), and the TDC outputs the SPAD trigger time and the number of SPADs triggered simultaneously within the same time to the synchronization circuit for generating a histogram and determining the subsequent ToF time.

The data processing chip provided by the embodiment of the invention comprises a plurality of adjusting circuits, wherein each adjusting circuit is coupled with one or more photoelectric detectors in one photoelectric detection unit. The dead time of the SPAD is adjusted through the adjusting circuit, and the pulse signal output to a subsequent circuit by the photoelectric detector can be effectively controlled.

As an example in fig. 10, each photodetecting unit 1000 comprises four SPADs, namely SPAD1001A, SPAD1001B, SPAD1001C, SPAD 1001D. The output terminal of each SPAD is coupled to the input terminal of a regulating circuit (the clk terminal of the D flip-flop). Specifically, the output terminal of the SPAD1001A is coupled to the input terminal of the adjusting circuit 1002A, the output terminal of the SPAD1001B is coupled to the input terminal of the adjusting circuit 1002B, the output terminal of the SPAD1001C is coupled to the input terminal of the adjusting circuit 1002C, and the output terminal of the SPAD1001D is coupled to the input terminal of the adjusting circuit 1002D. The output ends (the output end Q of the D flip-flop) of the four adjusting circuits corresponding to the four SPADs in each photodetecting unit 1000 are coupled to the same signal readout circuit, and output Pulse-2 to the TDC.

As shown in fig. 11, the embodiment of the invention further provides an optical system 110.

The optical system 110 includes: a light emitting module 111, a light detecting module 112 and a control module 113. The optical transmission module 111 refers to a part (which may include circuits, devices, structures, etc.) for laser transmission in the optical detection system; the optical detection module 112 refers to a portion (which may include circuits, devices, structures, etc.) of the optical detection system for detecting the echo signal of the laser light.

The light Emitting module 111 includes a light Emitting array 1111, for example, implemented by a Vertical-Cavity Surface-Emitting Laser (VCSEL) array. The light emitting array 1111 includes a plurality of rows and a plurality of columns. Wherein, each row and each column are respectively provided with a plurality of light emitting units 11111, and each light emitting unit 11111 comprises at least one light emitter; the light emitting array 1111 is further configured with a light emitting array driving circuit, coupled to each light emitter, for driving the light emitter to operate.

The light detection module 112 includes: the optical electrical detection array 1121 may be, for example, the optical electrical detection array of fig. 10, and is configured to receive an optical echo signal after the detection beam reaches the target 114. In addition, the optical detection module 112 may further include a signal readout circuit (not shown) for reading out and transmitting the signal generated by the optical detection array 1121 to the control module 113.

In the optical detection system, an emission lens set 1114 can be further arranged and is positioned on the emergent light path of the light emission array 1111; in the optical detection system, a receiving lens group 1122 may be further provided, and the photodetection array 1121 may be located on a focal plane of the receiving lens group 1122.

The control module 113 is coupled to the light emitting array 1111 and the photodetection array 1121; the light emitting arrays are respectively controlled to emit detection light beams according to a certain sequence and power, and the corresponding light detection arrays receive echo signals.

The photo detection module 112 further includes a data processing chip 1123, and the data processing chip 1123 includes a plurality of adjusting circuits, each of which is coupled to one of the photo detectors. The data processing chip of the embodiment of the invention can be the data processing chip shown in fig. 10, and adjusts the trigger signal of each SPAD, thereby achieving the effects of avoiding double peaks and improving the signal-to-noise ratio.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A conditioning circuit adapted to cooperate with a photodetector adapted to receive a laser pulse to produce a first pulse combination, comprising:

an adjusting unit adapted to receive the first pulse combination, to sample only the arrival time of a first pulse in the first pulse combination within a preset time,

W_pulsethe preset time is less than or equal to 5W_pulseIn the formula W_pulseIs the pulse width of the laser pulse.

2. The regulation circuit of claim 1 wherein the regulation unit is adapted to output a second pulse corresponding to the arrival time of a first pulse of the first combination of pulses, the first abrupt edge of the second pulse corresponding to the first abrupt edge of the first pulse.

3. The regulation circuit of claim 2 wherein the first pulse and the second pulse are both positive pulses, the first sharp edge of the second pulse is a rising edge, and the first sharp edge of the first pulse is a rising edge.

4. The adjustment circuit of claim 2, wherein the adjustment unit comprises:

an output signal providing unit adapted to generate the second pulse based on a reset pulse and the first pulse;

a reset unit adapted to generate the reset pulse according to the second pulse.

5. The regulating circuit according to claim 4, wherein the output signal providing unit is adapted to generate a first sharp edge of the second pulse in accordance with a first sharp edge of the first pulse and to generate a second sharp edge of the second pulse signal based on the first sharp edge of the reset pulse.

6. The regulation circuit of claim 4 wherein the reset pulse is a negative pulse and the first abrupt edge of the reset pulse is a falling edge.

7. The adjustment circuit of claim 4, wherein the total duration of the second pulse and the reset pulse is not less than W_pulse。

8. The adjustment circuit according to claim 4, wherein the output signal supply unit includes: a bi-stable circuit;

the first input terminal of the bistable circuit is adapted to receive a first positive voltage;

a second input of the bi-stable circuit is adapted to receive the first combination of pulses;

the reset end of the bistable circuit is suitable for receiving the reset pulse;

the output end of the bistable circuit is suitable for outputting the second pulse.

9. The adjustment circuit according to claim 4, wherein the output signal supply unit includes: a D flip-flop;

the input end of the D trigger is suitable for receiving a first positive voltage;

the clock signal end of the D flip-flop is suitable for receiving the first pulse combination;

the reset end of the D trigger is suitable for receiving the reset pulse;

the output end of the D flip-flop is suitable for outputting the second pulse.

10. The adjustment circuit of claim 4, wherein the reset unit comprises:

a control unit adapted to generate one of a charging signal and a discharging signal according to a first abrupt edge of the second pulse, and generate the other of the charging signal and the discharging signal according to a second abrupt edge of the second pulse;

the capacitive storage unit is suitable for charging and discharging the charges stored by the capacitive storage unit according to the charging signal and the discharging signal;

and a reset signal providing unit which generates the reset pulse after the voltage of the capacitive memory cell reaches a threshold voltage.

11. The adjustment circuit of claim 4, wherein the reset unit comprises: the capacitive storage unit comprises a control unit, a capacitive storage unit and a reset signal supply unit;

the control unit includes: the PMOS tube, the NMOS tube and the resistance unit; the source electrode of the PMOS tube is suitable for being connected with a first positive voltage, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and is suitable for receiving the second pulse, and the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, the capacitive storage unit and the reset signal providing unit; the source electrode of the NMOS tube is connected with the resistance unit;

the capacitive storage cell includes: a capacitor;

the reset signal supply unit includes: and the output end of the last inverter is suitable for outputting the reset pulse.

12. The adjustment circuit of claim 11, wherein the resistance unit comprises a resistor or a variable resistor.

13. The adjustment circuit of claim 4, wherein the reset unit comprises: the capacitive storage unit comprises a control unit, a capacitive storage unit and a reset signal supply unit;

the control unit includes: the device comprises a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube and a current output type analog-to-digital converter; the source electrode of the PMOS tube is suitable for being connected with a first positive voltage, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and is suitable for receiving the second pulse, and the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, the capacitive storage unit and the reset signal providing unit; the source electrode of the NMOS tube is connected with the current output type analog-to-digital converter;

the capacitive storage cell includes: a capacitor;

14. A data processing chip, comprising:

the conditioning circuit of any of claims 1 to 13 adapted to cooperate with one or more photodetectors.

15. A photodetector adapted to cooperate with the conditioning circuit of any one of claims 1 to 13, characterized in that it comprises:

a photoelectric conversion unit adapted to generate the first pulse combination in response to the one laser pulse.

16. The photodetector of claim 15, wherein the photoelectric conversion cell is an avalanche diode.

17. The photodetector of claim 16, wherein the photoelectric conversion unit is a single photon avalanche diode.

18. A photodetection array, comprising:

a plurality of rows and a plurality of columns; wherein each row and each column is provided with a plurality of photo detection units, each photo detection unit comprising at least one photo detector according to any one of claims 15 to 17;

the adjustment circuit of any one of claims 1 to 13, coupled to one or more photodetectors in one photodetector unit.

19. An optical system, comprising:

an optical transmit module comprising: a light emitting array including a plurality of rows and a plurality of columns; wherein, each row and each column are respectively provided with a plurality of light emitting units, and each light emitting unit comprises at least one light emitter; the light emitting array further comprises a light emitting array driving circuit coupled to each of the light emitters for emitting a detection laser beam;

a light detection module comprising: the photodetection array according to claim 18, configured to receive a detection echo.