CN117783643A - Load current detection system - Google Patents
Load current detection system Download PDFInfo
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- CN117783643A CN117783643A CN202410210701.1A CN202410210701A CN117783643A CN 117783643 A CN117783643 A CN 117783643A CN 202410210701 A CN202410210701 A CN 202410210701A CN 117783643 A CN117783643 A CN 117783643A
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- 238000001514 detection method Methods 0.000 title claims abstract description 66
- 238000005070 sampling Methods 0.000 claims abstract description 60
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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Abstract
The invention relates to a load current detection system, and belongs to the technical field of integrated circuits. The load current detection system comprises a power tube current sampling circuit, a current comparison circuit and a load current detection circuit, wherein the power tube current sampling circuit samples load current; the current comparison circuit determines the voltage of the output end according to the load sampling signal; the load current detection circuit outputs a load detection logic signal according to the voltage of the output end of the current comparison circuit, the load sampling signal and the reference voltage, so that the load current detection is realized, and further, other circuits can be used as a judgment basis. The magnitude of the detection current can be changed by adjusting the resistance value of the first resistor. The load current detection system provided by the invention has the advantages of simple structure and low cost, and is suitable for charging modules of various mobile devices.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to the technical field of integrated circuits, and specifically relates to a load current detection system.
Background
With the development of radio technology, various fast-charging mobile devices are becoming more and more popular. With the increase of switching current and charging voltage, the charging power of the power tube is higher and higher, and in some situations, load current needs to be limited. It is therefore inevitably necessary to introduce a current detection circuit in the circuit. And further giving a later-stage circuit as a judging basis for further work according to the load current detection result.
Therefore, it is necessary to study a technical solution of the load current detection circuit.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a load current detection system which has a simple structure and low cost and is suitable for a mobile device charging module.
In order to achieve the above object, a load current detection system of the present invention has the following configuration:
the load current detection system includes: a power tube current sampling circuit, a current comparison circuit and a load current detection circuit,
the power tube current sampling circuit is used for sampling load current Iload to generate a load sampling signal V5;
the current comparison circuit comprises a first resistor R1, and the voltage V3 at the output end of the current comparison circuit is determined according to the first current I1 of the load sampling signal V5 passing through the first resistor R1;
the Load current detection circuit comprises a switch S1 and a comparator CMP, wherein the switch S1 is controlled to be turned on and off by the voltage V3 at the output end of the current comparison circuit, two ends of the switch S1 are respectively connected with the Load sampling signal V5 and the positive input end of the comparator CMP, the negative input end of the comparator CMP is connected with a reference voltage Vref, and the output end of the comparator CMP outputs a Load detection signal load_detect.
In the load current detection system, in the power tube current sampling circuit, load current Iload is sampled by a power tube N1; the grid electrode of the power tube N1 is connected with the output end GATE of a charge pump (charge pump) and is connected with the grid end of the sampling tube N2; the drain electrode of the power tube N1 is connected with the input voltage VIN and the drain electrode of the sampling tube N2; the source electrode of the power tube N1 is connected with the output voltage VOUT; the source electrode of the sampling tube N2 provides the load sampling signal V5; the width-to-length ratio of the power tube N1 to the sampling tube N2 is N:1.
In the load current detection system, the upper end of a first resistor R1 is connected with the source electrode of a sampling tube N2, the current of the first resistor R1 is the first current I1, and the lower end of the first resistor R1 is connected with the upper end of a fourth resistor R4;
the source electrode of the first PMOS tube P1 is connected with the lower end of the fourth resistor R4, and the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the second PMOS tube P2; the drain electrode of the PMOS tube P1 is connected with the voltage V3 at the output end of the current comparison circuit in parallel with the drain electrode of the third NMOS tube N3;
the grid electrode and the drain electrode of the second PMOS tube P2 are in short circuit, and the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the first PMOS tube P1 to form a current mirror; the width-to-length ratio of the first PMOS tube P1 to the second PMOS tube P2 is 1:1; the source electrode of the second PMOS tube P2 is connected with the lower end of the second resistor R2;
the upper end of the second resistor R2 is connected with the output voltage VOUT; and the second resistor R2 is the same as the fourth resistor R4;
the grid electrode of the third NMOS tube N3 is connected with the grid electrodes of the fourth NMOS tube N4 and the fifth NMOS tube N5, the width-to-length ratio of the third NMOS tube N3 to the fourth NMOS tube N4 to the fifth NMOS tube N5 is 1:1:1, and the source electrodes of the third NMOS tube N3, the fourth NMOS tube N4 and the fifth NMOS tube N5 are all grounded;
the grid electrode and the source electrode of the fifth NMOS tube N5 are in short circuit to form a current mirror, and the drain electrode of the fifth NMOS tube N5 is connected with an external reference current source ibias.
In the load current detection system, a preset load detection current, namely the magnitude of the first current I1, is trimmed by adjusting the resistance value of the first resistor R1.
In the load current detection system, the load current detection circuit further includes a third resistor R3, and one end of the switch S1 connected to the positive input end of the comparator CMP is grounded through the third resistor R3.
In the load current detection system, the switch S1 is a sixth NMOS transistor N6, a gate of the sixth NMOS transistor N6 is connected to the voltage V3 at the output end of the current comparison circuit, a drain of the sixth NMOS transistor N6 is connected to the load sampling signal, and a source of the sixth NMOS transistor N6 is connected to the positive input end of the comparator CMP and is grounded through the third resistor R3.
The load current detection system adopting the invention comprises: the power tube current sampling circuit is used for sampling load current; the current comparison circuit determines the voltage of the output end according to the load sampling signal; the load current detection circuit outputs a load detection logic signal according to the voltage of the output end of the current comparison circuit, the load sampling signal and the reference voltage, so that the load current detection is realized, and further, other circuits can be used as a judgment basis. The magnitude of the detection current can be changed by adjusting the resistance value of the first resistor. The load current detection system provided by the invention has the advantages of simple structure and low cost, and is suitable for charging modules of various mobile devices.
Drawings
FIG. 1 is a schematic block diagram of a load current detection system of the present invention;
FIG. 2 is a circuit diagram of a load current detection system according to the present invention;
FIG. 3 is a circuit diagram of an embodiment of a load current detection system according to the present invention;
fig. 4 is a schematic diagram illustrating a simulation of the output signal of the comparator in the embodiment of fig. 3.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
Fig. 1 is a schematic block diagram of a load current detection system according to the present invention.
In one embodiment, the load current detection system, as shown in fig. 1, includes: the power tube current sampling circuit, the current comparison circuit and the load current detection circuit.
Specifically, as shown in fig. 2, the power tube current sampling circuit is configured to sample the load current Iload to generate a load sampling signal V5;
the current comparison circuit comprises a first resistor R1, and the voltage V3 at the output end of the current comparison circuit is determined according to the first current I1 of the load sampling signal V5 passing through the first resistor R1;
the Load current detection circuit comprises a switch S1 and a comparator CMP, wherein the switch S1 is controlled to be turned on and off by the voltage V3 at the output end of the current comparison circuit, two ends of the switch S1 are respectively connected with the Load sampling signal V5 and the positive input end of the comparator CMP, the negative input end of the comparator CMP is connected with a reference voltage Vref, and the output end of the comparator CMP outputs a Load detection signal load_detect.
In a preferred embodiment, as shown in fig. 2 and 3, in the power tube current sampling circuit, the load current Iload is sampled by the power tube N1; the grid electrode of the power tube N1 (a first NMOS tube) is connected with the output end GATE of a charge pump (a charge pump) and is connected with the grid end of a sampling tube N2 (a second NMOS tube); the drain electrode of the power tube N1 is connected with the input voltage VIN and the drain electrode of the sampling tube N2; the source electrode of the power tube N1 is connected with the output voltage VOUT; the source electrode of the sampling tube N2 provides the load sampling signal V5; the width-to-length ratio of the power tube N1 to the sampling tube N2 is N:1.
In the current comparison circuit, the upper end of a first resistor R1 is connected with the source electrode of the sampling tube N2, the current of the first resistor R1 is the first current I1, and the lower end of the first resistor R1 is connected with the upper end of a fourth resistor R4; the preset load detection current, namely the magnitude of the first current I1, can be adjusted by adjusting the resistance value of the first resistor R1;
the source electrode of the first PMOS tube P1 is connected with the lower end of the fourth resistor R4, and the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the second PMOS tube P2; the drain electrode of the PMOS tube P1 is connected with the voltage V3 at the output end of the current comparison circuit in parallel with the drain electrode of the third NMOS tube N3;
the grid electrode and the drain electrode of the second PMOS tube P2 are in short circuit, and the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the first PMOS tube P1 to form a current mirror; the width-to-length ratio of the first PMOS tube P1 to the second PMOS tube P2 is 1:1; the source electrode of the second PMOS tube P2 is connected with the lower end of the second resistor R2;
the upper end of the second resistor R2 is connected with the output voltage VOUT; and the second resistor R2 is the same as the fourth resistor R4;
the grid electrode of the third NMOS tube N3 is connected with the grid electrodes of the fourth NMOS tube N4 and the fifth NMOS tube N5, the width-to-length ratio of the third NMOS tube N3 to the fourth NMOS tube N4 to the fifth NMOS tube N5 is 1:1:1, and the source electrodes of the third NMOS tube N3, the fourth NMOS tube N4 and the fifth NMOS tube N5 are all grounded;
the grid electrode and the source electrode of the fifth NMOS tube N5 are in short circuit to form a current mirror, and the drain electrode of the fifth NMOS tube N5 is connected with an external reference current source ibias.
The load current detection circuit further comprises a third resistor R3, and one end of the switch S1 connected with the positive input end of the comparator CMP is grounded through the third resistor R3.
In a more preferred embodiment, as shown in fig. 3, the switch S1 is a sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 is connected to the output voltage V3 of the current comparing circuit, the drain of the sixth NMOS transistor N6 is connected to the load sampling signal, and the source of the sixth NMOS transistor N6 is connected to the positive input of the comparator CMP and is grounded through the third resistor R3.
In practical applications, the embodiment of the present invention provides a load current detection system as shown in fig. 3.
GATE is the GATE voltage of the power transistor provided by the charge pump, ibias is the externally provided reference current, and Vref is the reference voltage provided by the external circuit. The specific working principle of the load current detection system is as follows:
the N1 tube is a power tube, the N2 tube is a sampling tube, and the sampling ratio of the N1 tube and the N2 tube is N1, so that the current flowing through the N1 tube and the N2 tube is N1. N3, N4, N5 make up the current mirror, where N3: n4: n5=1: 1: 1. p1 and P2 constitute a current mirror, and P1: p2=1: 1. i1, I2 are the currents flowing through the resistors R1 and R2, respectively, so I1: i2 =1: 1. r2, R4 act as current limiting, and r2=r4. The load current is defined as Iload
V4= Isample×R3，
Isample=Vref/R3
=Iload/N
Ismple is the sampling current of the output end of the sampling circuit of the power tube circuit;
if the on-resistance of the N1 tube is defined as Ron, the on-resistance of the sampling tube N2 is Ron x N,
V5=VIN- Ron×N×Isample
=VIN- Ron×N ×Vref/R3,
VOUT=VIN-Iload×Ron，
because i1=i2, and P1 and P2 constitute a current mirror,
so that
V1=V2，
So that
VOUT=V5-VR1
=V5-R1×I1，
Can be pushed out
R1=(V5- VOUT)/I1
=( Iload×Ron - Ron×N×Vref/R3)/I1。
Therefore, the magnitude of the preset load detection current can be trimmed by adjusting the resistance value of R1.
The load current detection system presets a load detection current of 100mA.
When the Load current does not exceed 100mA, the current flowing through the sampling tube N2 is relatively small, so I1 < I2, since the gates of P1 and P2 are the same, the source of P1 is smaller than the source of P2, so the pull-up capability of P1 is smaller than the pull-down capability of N3, so V3 is pulled low, the NMOS switching tube N6 (S1) is turned off, V4 is low, and V4 < Vref gives a comparison signal load_detect low through the comparator CMP.
Conversely, as the load current increases gradually, I1 increases gradually. When the load current exceeds 100mA, I1 > I2, since the gates of P1 and P2 are the same, the source of P1 > the source of P2, so the pull-up capability of P1 is greater than the pull-down capability of N3, so V3 rises, gradually rising to NMOS switch N6 open, v4=isample×r3 when N6 is open, and at this time V4 > Vref, the comparison signal load_detect is given high by comparator CMP.
As can be seen from the simulation diagram fig. 4, when the Load current Iload rises to around 100mA, the Load current detection circuit operates, giving a logic signal load_detect high level.
In addition, the switching transistor S1 shown in fig. 2 may use, but is not limited to, devices having switching characteristics such as NMOS, BJT, etc.; the current mirrors N3, N4, N5, P1, P2 in fig. 2 may use, but are not limited to, devices such as MOS, BJT, etc. that function as current mirrors.
The load current detection system adopting the invention comprises: the power tube current sampling circuit is used for sampling load current; the current comparison circuit determines the voltage of the output end according to the load sampling signal; the load current detection circuit outputs a load detection logic signal according to the voltage of the output end of the current comparison circuit, the load sampling signal and the reference voltage, so that the load current detection is realized, and further, other circuits can be used as a judgment basis. The magnitude of the detection current can be changed by adjusting the resistance value of the first resistor. The load current detection system provided by the invention has the advantages of simple structure and low cost, and is suitable for charging modules of various mobile devices.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. A load current detection system, comprising: a power tube current sampling circuit, a current comparison circuit and a load current detection circuit,
the power tube current sampling circuit is used for sampling load current (Iload) to generate a load sampling signal (V5);
the current comparison circuit comprises a first resistor (R1), and the magnitude of the voltage (V3) at the output end of the current comparison circuit is determined according to the magnitude of a first current (I1) of the load sampling signal (V5) passing through the first resistor (R1);
the Load current detection circuit comprises a switch (S1) and a Comparator (CMP), wherein the switch (S1) is controlled to be turned on and off by the voltage (V3) at the output end of the current comparison circuit, two ends of the switch (S1) are respectively connected with the Load sampling signal (V5) and the positive input end of the Comparator (CMP), the negative input end of the Comparator (CMP) is connected with a reference voltage (Vref), and the output end of the Comparator (CMP) outputs a Load detection signal (load_detect).
2. The load current detection system according to claim 1, wherein the power tube current sampling circuit samples the load current (Iload) by sampling the power tube (N1); the grid electrode of the power tube (N1) is connected with the output end (GATE) of the charge pump (charge pump) and is connected with the grid end of the sampling tube (N2); the drain electrode of the power tube (N1) is connected with the input Voltage (VIN) and the drain electrode of the sampling tube (N2); the source electrode of the power tube (N1) is connected with the output Voltage (VOUT); the source of the sampling tube (N2) provides the load sampling signal (V5); the width-to-length ratio of the power tube (N1) to the sampling tube (N2) is (N: 1).
3. The load current detection system according to claim 2, wherein the upper end of the first resistor (R1) is connected to the source of the sampling tube (N2), the current of the first resistor (R1) is the first current (I1), and the lower end of the first resistor (R1) is connected to the upper end of the fourth resistor (R4);
the source electrode of the first PMOS tube (P1) is connected with the lower end of the fourth resistor (R4), and the grid electrode of the first PMOS tube (P1) is connected with the grid electrode of the second PMOS tube (P2); the drain electrode of the PMOS tube (P1) is connected with the voltage (V3) of the output end of the current comparison circuit in parallel with the drain electrode of the third NMOS tube (N3);
the grid electrode and the drain electrode of the second PMOS tube (P2) are in short circuit, and the grid electrode of the second PMOS tube (P2) is connected with the grid electrode of the first PMOS tube (P1) to form a current mirror; the width-to-length ratio of the first PMOS tube (P1) to the second PMOS tube (P2) is 1:1; the source electrode of the second PMOS tube (P2) is connected with the lower end of the second resistor (R2);
the upper end of the second resistor (R2) is connected with the output Voltage (VOUT); and said second resistor (R2) is identical to said fourth resistor (R4);
the grid electrode of the third NMOS tube (N3) is connected with the grid electrodes of the fourth NMOS tube and the fifth NMOS tube (N4, N5), the width-to-length ratio of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube (N3, N4, N5) is 1:1:1, and the source electrodes of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube (N3, N4, N5) are all grounded;
the grid electrode and the source electrode of the fifth NMOS tube (N5) are in short circuit to form a current mirror, and the drain electrode of the fifth NMOS tube (N5) is connected with an external reference current source (ibias).
4. A load current detection system according to claim 3, characterized in that the magnitude of the preset load detection current, i.e. the first current (I1), is modified by adjusting the resistance value of said first resistor (R1).
5. The load current detection system according to claim 4, wherein the load current detection circuit further comprises a third resistor (R3), and wherein the switch (S1) is connected to one end of the positive input of the Comparator (CMP) to be grounded through the third resistor (R3).
6. The load current detection system according to claim 5, wherein the switch (S1) is a sixth NMOS transistor (N6), a gate of the sixth NMOS transistor (N6) is connected to the output voltage (V3) of the current comparison circuit, a drain of the sixth NMOS transistor (N6) is connected to the load sampling signal, and a source of the sixth NMOS transistor (N6) is connected to the positive input of the Comparator (CMP) and is grounded through the third resistor (R3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410210701.1A CN117783643A (en) | 2024-02-27 | 2024-02-27 | Load current detection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410210701.1A CN117783643A (en) | 2024-02-27 | 2024-02-27 | Load current detection system |
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| CN117783643A true CN117783643A (en) | 2024-03-29 |
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|---|---|---|---|
| CN202410210701.1A Pending CN117783643A (en) | 2024-02-27 | 2024-02-27 | Load current detection system |
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