CN116068259A - High-precision zero current detection circuit and method - Google Patents

High-precision zero current detection circuit and method Download PDF

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Publication number
CN116068259A
CN116068259A CN202310151562.5A CN202310151562A CN116068259A CN 116068259 A CN116068259 A CN 116068259A CN 202310151562 A CN202310151562 A CN 202310151562A CN 116068259 A CN116068259 A CN 116068259A
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CN116068259B (en
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谢凌寒
周颖
卢国云
朱凯
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Wuxi Etek Microelectronics Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention relates to a high-precision zero current detection circuit and a high-precision zero current detection method. The offset voltage compensation circuit is configured to sample and hold offset voltage of the voltage comparator COMP1 when the switching tube driving control signal GT_HSD drives and controls the switching tube FET_HSD to be conducted; when the synchronous rectifier tube FET_LSD is driven to be conducted by the rectifier tube driving control signal GT_LSD, a node voltage first comparison state value generated when the voltage comparator COMP1 is subjected to voltage comparison is configured, the offset voltage offset circuit processes the node voltage first comparison state value by utilizing the sampled offset voltage, so that a node voltage second comparison state value for offset voltage of the voltage comparator COMP1 is obtained, and the node voltage second comparison state value is output. The invention can effectively and approximately eliminate offset current caused by voltage regulation and delay error current caused by delay, and improve the reliability and precision of zero current detection.

Description

High-precision zero current detection circuit and method
Technical Field
The invention relates to a detection circuit and a detection method, in particular to a high-precision zero current detection circuit and a high-precision zero current detection method.
Background
In a synchronous direct current-to-direct current (DC-DC) circuit, in order to improve light load efficiency, when the current of a synchronous rectifying tube is reduced to zero, the synchronous rectifying tube must be turned off in time, otherwise, for a buck DC-DC circuit, current flows from an output to the ground; for a step-up DC-DC circuit, there will be a current flowing from the output to the input power, i.e. for both a step-down DC-DC circuit and a step-up DC-DC circuit, a reduction in efficiency will result.
When the current flowing through the synchronous rectifying tube is large, the synchronous rectifying tube cannot be immediately turned off, otherwise, after the synchronous rectifying tube is turned off, the current passes through the body diode of the synchronous rectifying tube, and at the moment, the voltage drop of the synchronous rectifying diode reaches about 0.7V, and the light load efficiency is reduced. Therefore, it is most desirable to: when the current flowing through the synchronous rectifying tube is reduced to 0, the synchronous rectifying tube is turned off.
Taking the zero current detection of a direct current buck DC-DC circuit as an example, a conventional circuit is shown in fig. 1. In fig. 1, in order to ensure high efficiency in zero current detection of a large current DC-DC circuit, the on-resistance of a synchronous rectifier (fet_lsd) is generally small. However, since the comparator U1 of FIG. 1 may have a small offset V caused by the process OS In the minute disorder V OS The following also results in larger current deviations, specifically:
V OS ＝ΔI 1 r ds
wherein r is ds To synchronize the on-resistance of the rectifier, ΔI 1 The offset error current is obtained.
As can be seen from the above expression, when the minute disorder V OS Is 5mV and has on-resistance r ds At 10 milliohms, then, the resulting offset error current ΔI 1 500mA.
In addition, the delay of the comparator U1 and the driving circuit (DRIVER in fig. 1) also causes current deviation, if the current is detected to be zero, but due to the delay of the comparator U1 and the driving circuit, when the synchronous power tube is turned off, the inductor current drops by a certain value again. Assuming that the delay of the driving circuit and the comparator is t, then the error due to the delay is:
Figure BDA0004090964830000011
wherein V is 0 For the output voltage, L is the inductance of the inductor, ΔI 2 Is a delay error current.
As can be seen from the above-mentioned expression of the delay error, when the output voltage V 0 Different, delay error current ΔI 2 Will also vary. The traditional circuit can not overcome delta I 2 With output voltage V 0 And changes from variation to variation.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a high-precision zero current detection circuit and a high-precision zero current detection method, which can effectively and approximately eliminate offset current caused by voltage regulation and delay error current caused by delay, and improve the reliability and precision of zero current detection.
According to the technical scheme provided by the invention, the high-precision zero current detection circuit comprises:
a driving circuit for generating a rectifying tube driving control signal GT_LSD for driving the switching state of the synchronous rectifying tube FET_LSD and a switching tube driving control signal GT_HSD for driving and controlling the switching state of the switching tube FET_HSD, wherein the rectifying tube driving control signal GT_LSD is complementary to the switching driving control signal GT_HSD in phase;
the automatic zero-setting comparator is used for comparing the voltage of the node A and the voltage of the node B during zero current detection and comprises a voltage comparator COMP1 used for comparing the voltages and an offset voltage offset circuit used for eliminating offset voltage of the voltage comparator COMP1,
the voltage comparator COMP1 is connected with the input end of the driving circuit through an offset voltage counteracting circuit, and the offset voltage counteracting circuit receives a switching tube driving control signal GT_HSD output by the driving circuit;
when the switching tube FET_HSD is driven and controlled to be conducted based on the switching tube driving control signal GT_HSD, an offset voltage counteracting circuit is configured to sample and hold the offset voltage of the voltage comparator COMP1, and a low-level signal is output through the offset voltage counteracting circuit;
and when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, a node voltage first comparison state value generated during voltage comparison of the voltage comparator COMP1 is configured, the offset voltage offset circuit processes the node voltage first comparison state value by using the sampled offset voltage so as to obtain a node voltage second comparison state value for offset voltage of the voltage comparator COMP1, and the node voltage second comparison state value is output.
The offset voltage offset circuit comprises a sampling holder, a voltage comparator COMP2, an output connection circuit and a switch unit group for configuring the working state of the offset voltage offset circuit, wherein,
the differential output end of the voltage comparator COMP1 is connected with the differential input end of the sampling holder, the differential output end of the sampling holder is connected with the differential input end of the voltage comparator COMP2, the output end of the voltage comparator COMP2 is connected with the output connection circuit, and the switching tube driving control signal GT_HSD is received through the output connection circuit;
when the driving control switch tube FET_HSD is conducted based on the driving control signal GT_HSD of the switch tube, the switch unit group is configured so that the differential input end of the voltage comparator COMP1 is grounded, and the differential input end of the voltage comparator COMP2 is grounded with the bias voltage VB;
when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, the switch unit group is configured to utilize the voltage comparator COMP1 to conduct voltage comparison required during zero current detection, and the second comparison state value of the node voltage is output through the sampling keeper, the voltage comparator COMP2 and the output connection circuit in sequence.
The switch unit group comprises a switch SA1, a switch SA2, a switch SB1, a switch SB2, a switch SB3 and a switch SB4, wherein,
the first end of the switch SA1 is connected with the node B, the second end of the switch SA1 is connected with the first end of the switch SB1 and the same-phase end of the voltage comparator COMP1, the second end of the switch SB1 and the first end of the switch SB2 are grounded, the second end of the switch SB2 is connected with the first end of the switch SA2 and the opposite-phase end of the voltage comparator COMP1, and the second end of the switch SA2 is connected with the node A;
the first end of the switch SB3 is connected to the first output terminal OUT1 of the sample holder and the inverting input terminal of the voltage comparator COMP2, the second end of the switch SB3 and the first end of the switch SB4 are connected to the bias voltage VB, and the second end of the switch SB4 is connected to the second output terminal OUT2 of the sample holder and the non-inverting terminal of the voltage comparator COMP 2.
When the switching tube FET_HSD is driven AND controlled to be conducted based on the switching tube driving control signal GT_HSD of high level, the output connection circuit comprises an AND gate AND AND an inverter INV, wherein,
the input end of the inverter INV is used for receiving the switching tube driving control signal gt_hsd, the output end of the inverter INV is connected with one input end of the AND gate AND, the output end of the voltage comparator COMP2 is connected with the other input end of the AND gate AND, AND the output end of the AND gate AND is connected with the driving circuit in an adapting way.
And a delay error current cancellation circuit for canceling the delay error, wherein,
when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, an automatic zero adjustment comparator is configured to compare the voltage of the node A with the voltage of the node B;
when the voltage of the node A is compared with the voltage of the node B, a delay error current eliminating circuit is utilized to load a rectifying tube turn-off compensation current based on delay time and output voltage to the node B, and when the voltage of the node A is equal to the voltage of the node B, a driving circuit controls a rectifying tube driving control signal GT_LSD to turn off a synchronous rectifying tube FET_LSD based on the loaded rectifying tube turn-off compensation current.
The inverting terminal of the voltage comparator COMP1 is connected to one end of the resistor R1 and the output terminal of the current source IB1 to form a node a, where the other end of the resistor R1 is grounded;
the in-phase end of the voltage comparator COMP1 is adaptively connected with one end of a resistor R2, the output end of a current source IB2 and a delay error current cancellation circuit to form a node B, wherein the power supply end of the current source IB2 and the power supply end of the current source IB1 are both connected with a voltage VDD, and the other end of the resistor R2 is connected with the drain end of a synchronous rectifier tube fet_lsd, the source end of a control switch tube fet_hsd and one end of an inductor L to form a node SW;
the source terminal of the synchronous rectifying tube FET_LSD is grounded, the drain terminal of the control switching tube FET_HSD is connected with the voltage VIN, the gate terminal of the synchronous rectifying tube FET_LSD receives the rectifying tube driving control signal GT_LSD output by the driving circuit, the gate terminal of the control switching tube FET_HSD receives the switching tube driving control signal GT_HSD output by the driving circuit, and the output voltage Vo is obtained through the other end of the inductor L.
The delay error current eliminating circuit comprises a node voltage sampling-current converting circuit connected with the node SW and a current mirror connected with the node voltage sampling-current converting circuit in an adapting way, wherein,
the current mirror is connected with the node B in an adaptive way;
the voltage of the node SW is converted into a compensation reference current based on delay time through a node voltage sampling-current conversion circuit, and the compensation reference current forms a rectifying tube turn-off compensation current through a current mirror and is loaded to the node B.
The node voltage sampling-current conversion circuit includes an operational amplifier AMP, wherein,
the non-inverting terminal of the operational amplifier AMP is connected with one end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to form a node C;
the other end of the resistor R3 is connected with the node SW, the inverting end of the operational amplifier AMP is connected with the source end of the NMOS tube MN1 and one end of the resistor R5, the gate end of the NMOS tube MN1 is connected with the output end of the operational amplifier AMP, and the drain end of the NMOS tube MN1 is connected with the current mirror in an adaptive manner;
the other end of the capacitor C1, the other end of the resistor R4 and the other end of the resistor R5 are grounded;
when the current output by the current source IB1 is equal to the current output by the current source IB2 and the voltage of the node a is equal to the voltage of the node B, there are:
Figure BDA0004090964830000041
wherein R is 2 Is a resistor R2Resistance value, R 3 Is the resistance value of the resistor R3, R 4 Is the resistance value of the resistor R4, t is the delay time of the driving circuit and the automatic zero-adjusting comparator, and R ds For the on-resistance of the synchronous rectifier fet_lsd, L is the impedance of the inductance L.
The current mirror comprises an NMOS transistor MN2 and an NMOS transistor MN3, wherein,
the gate terminal of the NMOS tube MN2 is connected with the source terminal of the NMOS tube MN2, the drain terminal of the NMOS tube MN1 and the gate terminal of the NMOS tube MN3, the source terminal of the NMOS tube MN3 is connected with the node B, and the drain terminal of the NMOS tube MN3 and the drain terminal of the NMOS tube MN2 are connected with the voltage VDD.
A high-precision zero current detection method is used for detecting zero current of a step-down DC-DC circuit by using the zero current detection circuit.
The invention has the advantages that: the offset error current caused by the offset voltage of the voltage comparator COMP1 can be eliminated through the automatic zero adjustment comparator, the delay error current caused by delay time is eliminated through the delay error current eliminating circuit, and the reliability and the precision of zero current detection are improved.
Drawings
Fig. 1 is a schematic diagram of an embodiment of a conventional zero current detection circuit.
Fig. 2 shows an embodiment of zero current detection according to the present invention.
Fig. 3 is a schematic diagram of the automatic zero-adjusting comparator in the working state when the driving control signal gt_hsd of the switching tube is at the high level.
Fig. 4 is a schematic diagram of an automatic zero-adjustment comparator in a high level state of the rectifier driving control signal gt_lsd.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
In order to effectively and approximately eliminate offset current caused by voltage regulation, and improve the reliability and precision of zero current detection, one embodiment of the invention comprises the following steps:
a driving circuit for generating a rectifying tube driving control signal GT_LSD for driving the switching state of the synchronous rectifying tube FET_LSD and a switching tube driving control signal GT_HSD for driving and controlling the switching state of the switching tube FET_HSD, wherein the rectifying tube driving control signal GT_LSD is complementary to the switching driving control signal GT_HSD in phase;
the automatic zero-setting comparator is used for comparing the voltage of the node A and the voltage of the node B during zero current detection and comprises a voltage comparator COMP1 used for comparing the voltages and an offset voltage offset circuit used for eliminating offset voltage of the voltage comparator COMP1,
the voltage comparator COMP1 is connected with the input end of the driving circuit through an offset voltage counteracting circuit, and the offset voltage counteracting circuit receives a switching tube driving control signal GT_HSD output by the driving circuit;
when the switching tube FET_HSD is driven and controlled to be conducted based on the switching tube driving control signal GT_HSD, an offset voltage counteracting circuit is configured to sample and hold the offset voltage of the voltage comparator COMP1, and a low-level signal is output through the offset voltage counteracting circuit;
and when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, a node voltage first comparison state value generated during voltage comparison of the voltage comparator COMP1 is configured, the offset voltage offset circuit processes the node voltage first comparison state value by using the sampled offset voltage so as to obtain a node voltage second comparison state value for offset voltage of the voltage comparator COMP1, and the node voltage second comparison state value is output.
Specifically, the driving circuit is mainly used for generating a rectifying tube driving control signal gt_lsd and a switching tube driving control signal gt_hsd, and uses the rectifying tube driving control signal gt_lsd and the switching tube driving control signal gt_hsd to respectively drive corresponding switch states of the synchronous rectifying tube fet_lsd and the switching tube fet_hsd, wherein the switch states are specifically in an on state or an off state, and the driving circuit can adopt the existing common mode, and can specifically meet the requirement of generating the required rectifying tube driving control signal gt_lsd and the switching tube driving control signal gt_hsd.
Fig. 1 and 2 show an embodiment of a synchronous rectifier fet_lsd and a control switch fet_hsd, wherein the synchronous rectifier fet_lsd and the control switch fet_hsd are both in the form of NMOS tubes, and of course, the synchronous rectifier fet_lsd and the control switch fet_hsd may also be in other implementation forms, which is specific to meeting the actual application requirements. The phase of the rectifying tube driving control signal gt_lsd is complementary with that of the switching driving control signal gt_hsd, specifically, the synchronous rectifying tube fet_lsd and the control switching tube fet_hsd are not simultaneously turned on, that is, when the synchronous rectifying tube fet_lsd is in a turned-on state, the control switching tube fet_hsd is in a turned-off state, and similarly, when the control switching tube fet_hsd is in a turned-on state, the synchronous rectifying tube fet_lsd is in a turned-off state.
As is clear from the above description, when performing zero current detection, the voltage comparison between the node a and the node B is required, and in fig. 1, the voltage comparison is performed by the voltage comparator U1, but the offset voltage exists in the voltage comparator U1, which results in a decrease in light load efficiency. In one embodiment of the present invention, voltage detection is implemented by using an AUTO-ZERO comparator, as shown in fig. 2, in fig. 2 auto_zero COMP is an AUTO-ZERO comparator, and the AUTO-ZERO comparator is mainly used for counteracting/eliminating offset current caused by offset voltage.
In order to realize voltage comparison and offset voltage elimination during zero current detection, in one embodiment of the present invention, the auto-zeroing comparator at least includes a voltage comparator and an offset voltage cancellation circuit, wherein the voltage comparator COMP1 is used for comparing the voltages of the node a and the node B, and the offset voltage cancellation circuit is used for canceling the offset voltage generated by the voltage comparator COMP 1. As illustrated in fig. 1 and fig. 2, the voltage comparator COMP1 is adaptively connected to the offset voltage cancellation circuit and is connected to the input end of the driving circuit through the offset voltage cancellation circuit, and in fig. 2, the whole auto-zeroing comparator also needs to receive the switching tube driving control signal gt_hsd output by the driving circuit, specifically, the switching tube driving control signal gt_hsd needs to be loaded to the offset voltage cancellation circuit.
For the above-mentioned node a, node B, etc., an embodiment is shown in fig. 2, specifically, the inverting terminal of the voltage comparator COMP1 is connected to one terminal of the resistor R1 and the output terminal of the current source IB1 to form the node a, where the other terminal of the resistor R1 is grounded;
the in-phase end of the voltage comparator COMP1 is adaptively connected with one end of a resistor R2, the output end of a current source IB2 and a delay error current cancellation circuit to form a node B, wherein the power supply end of the current source IB2 and the power supply end of the current source IB1 are both connected with a voltage VDD, and the other end of the resistor R2 is connected with the drain end of a synchronous rectifier tube fet_lsd, the source end of a control switch tube fet_hsd and one end of an inductor L to form a node SW;
the source terminal of the synchronous rectifying tube FET_LSD is grounded, the drain terminal of the control switching tube FET_HSD is connected with the voltage VIN, the gate terminal of the synchronous rectifying tube FET_LSD receives the rectifying tube driving control signal GT_LSD output by the driving circuit, the gate terminal of the control switching tube FET_HSD receives the switching tube driving control signal GT_HSD output by the driving circuit, and the output voltage Vo is obtained through the other end of the inductor L.
In fig. 2, ro is a load. The driving circuit is connected with the automatic zero-adjusting comparator in an adapting way and is also connected with an external logic control circuit, namely, in an initial state, the corresponding level states of the rectifying tube driving control signal GT_LSD and the switching tube driving control signal GT_HSD output by the driving circuit are controlled by the logic control circuit, are irrelevant to the automatic zero-adjusting comparator, and are in particular consistent with the prior art.
When the control switch tube FET_HSD is turned on by the switch tube driving control signal GT_HSD, the voltage VIN charges the inductor L by the control switch tube FET_HSD, and the current I flows through the inductor L L The current gradually increases. When the synchronous rectifier fet_lsd is turned on by the rectifier drive control signal gt_ls, current flows from GND through the synchronous rectifier fet_lsd to the node SW, and the output voltage Vo is obtained through the inductor L.
As can be seen from the above description, when the NMOS transistor is used for controlling the switching transistor fet_hsd, the automatic zero adjustment comparator outputs a low level signal when the switching transistor driving control signal gt_hsd drives and controls the switching transistor fet_hsd to be turned on. Therefore, when the control switching transistor fet_hsd is on, the offset voltage cancellation circuit samples and holds the offset voltage of the voltage comparator COMP1 in addition to charging the inductor L, and outputs a low-level signal via the offset voltage cancellation circuit, and the switching transistor drive control signal gt_hsd output by the drive circuit is held in a high-level state based on the low-level signal.
The process of sampling and holding the offset voltage of the voltage comparator COMP1 by the offset voltage canceling circuit and outputting the signal in the low level state will be specifically described.
In one embodiment of the present invention, the offset voltage cancellation circuit includes a sample holder, a voltage comparator COMP2, an output connection circuit, and a switch unit group configured to configure an operating state of the offset voltage cancellation circuit, where,
the differential output end of the voltage comparator COMP1 is connected with the differential input end of the sampling holder, the differential output end of the sampling holder is connected with the differential input end of the voltage comparator COMP2, the output end of the voltage comparator COMP2 is connected with the output connection circuit, and the switching tube driving control signal GT_HSD is received through the output connection circuit;
when the switching tube driving control signal GT_HSD drives and controls the switching tube FET_HSD to be conducted, the switching unit group is configured so that the differential input end of the voltage comparator COMP1 is grounded, and the differential input end of the voltage comparator COMP2 is grounded with the bias voltage VB;
when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, the switch unit group is configured to utilize the voltage comparator COMP1 to conduct voltage comparison required during zero current detection, and the second comparison state value of the node voltage is output through the sampling keeper, the voltage comparator COMP2 and the output connection circuit in sequence.
In fig. 3 and 4, an embodiment of the offset voltage offset circuit is shown, where Sample & Hold is the Sample-and-Hold. In specific implementation, according to the level state of the driving control signal gt_hsd of the switching tube, the switching unit group is configured to realize sampling and holding of offset voltage, or to realize comparison of corresponding voltages of the node a and the node B by using the voltage comparator COMP1, and output through the voltage comparator COMP 2.
In one embodiment of the present invention, the switch unit group includes a switch SA1, a switch SA2, a switch SB1, a switch SB2, a switch SB3, and a switch SB4, wherein,
the first end of the switch SA1 is connected with the node B, the second end of the switch SA1 is connected with the first end of the switch SB1 and the same-phase end of the voltage comparator COMP1, the second end of the switch SB1 and the first end of the switch SB2 are grounded, the second end of the switch SB2 is connected with the first end of the switch SA2 and the opposite-phase end of the voltage comparator COMP1, and the second end of the switch SA2 is connected with the node A;
the first end of the switch SB3 is connected to the first output terminal OUT1 of the sample holder and the inverting input terminal of the voltage comparator COMP2, the second end of the switch SB3 and the first end of the switch SB4 are connected to the bias voltage VB, and the second end of the switch SB4 is connected to the second output terminal OUT2 of the sample holder and the non-inverting terminal of the voltage comparator COMP 2.
Specifically, the switches SA1, SA2, SB1, SB2, SB3, and SB4 may take conventional forms, such as a semiconductor fully-controlled switch, and the specific form may be selected according to the needs, so as to meet the actual application requirements.
In fig. 3, in order to configure the switch unit group to perform offset voltage cancellation, in the state schematic diagram, the switch SA1 and the switch SA2 are in an off-state and an on-state, and at this time, the node a and the node B are not connected to the voltage comparator COMP1, and the switch SB1, the switch SB2, the switch SB3 and the switch SB4 are all kept in an on-state, so that the bias voltage VB needs to be within the common-mode input voltage range of the voltage comparator COMP 2.
As can be seen from the above description and fig. 3, the non-inverting terminal and the inverting terminal of the voltage comparator COMP1 are shorted to GND through the switches SB1 and SB2, and the non-inverting terminal and the inverting terminal of the voltage comparator COMP2 are connected to the bias voltage VB through the switches SB3 and SB 4. When the switching transistor driving control signal gt_hsd is in a high level state, a low level signal is outputted by the output connection circuit.
In particular, even if the voltage comparator COMP1 has an equivalent input offset V OS Assume a voltage comparatorThe gain of COMP1 is 20 times, and then the offset output at voltage comparator COMP1 is:
V OS_OUT ＝20*V OS
wherein V is OS_OUT For the voltage comparator COMP1 to input offset V in equivalent manner OS And a lower output.
In particular, when the sample-and-hold device is connected to the voltage comparator COMP1 in an adaptive manner, the voltage comparator COMP1 is used for inputting the offset V OS Output V of the lower part OS_OUT Is stored in the sample hold circuit; further, both the outputs OUT1, OUT2 of the sample-and-hold circuit have been forced to VB. Therefore, in the integrated circuit composed of the voltage comparator COMP1 and the sample-and-hold circuit, the two differential inputs of the integrated circuit are equal, and the two differential outputs OUT1 and OUT2 of the integrated circuit are also equal, and in this case, the offset is approximately 0 in the integrated circuit.
When the rectifier drive control signal gt_lsd is in a high state, the synchronous rectifier fet_lsd is in an on state. After the synchronous rectifying tube FET_LSD is conducted, current flows from GND to a node SW through the synchronous rectifying tube FET_LSD, and then is output through an inductor L, thus obtaining output voltage V O . In phase, a current I flows through an inductance L L Stepwise decrease as shown in fig. 4.
In fig. 4, the switch SA1 is turned on, the non-inverting terminal of the voltage comparator COMP1 is connected to the node B, the switch SA2 is turned on, and the inverting terminal of the voltage comparator COMP1 is connected to the node a; meanwhile, the switch SB3 and the switch SB4 are both in the off state, and at this time, the comparison of the voltages of the node A and the node B is realized. At the beginning of this phase, I L > current IB 2 And R is 2 >>r ds Wherein the current IB 2 I.e. the current outputted by the current source IB2, R2 is the resistance value of the point resistor R2, R ds I.e. the on-resistance of the synchronous rectifier FET _ LSD.
In one embodiment of the present invention, when the switching tube fet_hsd is driven AND controlled to be turned on based on the switching tube driving control signal gt_hsd of high level, the output connection circuit includes an AND gate AND an inverter INV, wherein,
the input end of the inverter INV is used for receiving the switching tube driving control signal gt_hsd, the output end of the inverter INV is connected with one input end of the AND gate AND, the output end of the voltage comparator COMP2 is connected with the other input end of the AND gate AND, AND the output end of the AND gate AND is connected with the driving circuit in an adapting way.
In fig. 3 AND 4, an embodiment of the output training stage is shown, where the switching tube driving control signal gt_hsd is connected to the input terminal of the inverter INV, so that when the switching tube driving control signal gt_hsd is in a high level state, a low level is output through the AND gate AND, that is, when the switching tube driving control signal gt_hsd is in a high level, a low level signal is loaded AND maintained to the driving circuit, so as to avoid the inversion of the output of the driving circuit.
As is clear from the above description, when the switching transistor driving control signal gt_hsd is in the high level state, the voltage corresponding to the node a AND the node B is not compared, AND at this time, a low level signal is applied to the driving circuit via the AND gate AND. When the driving control signal gt_hsd of the switching tube is in a low level state, the auto-zeroing comparator compares the corresponding voltages of the node a and the node B by using the voltage comparator COMP1, and loads a high-level node voltage second comparison state value to the driving circuit when the voltage of the node a is equal to the node B, and at this time, the driving circuit makes the driving control signal gt_lsd of the rectifying tube be in a low level according to the high-level node voltage second comparison state value, that is, turns off the synchronous rectifying tube fet_lsd.
In operation, the offset voltage of the voltage comparator COMP1 is sampled and held only when the switching transistor driving control signal gt_hsd is in a high level state. When the rectifier driving control signal gt_lsd is at a high level, the voltages of the node a and the node B are compared by the voltage comparator COMP1, so as to generate a first comparison state value of the node voltage after the comparison. The node voltage first comparison state value is specifically related to the voltage of the node A and the voltage of the node B, and the mode of specifically generating the node voltage first comparison state value is consistent with the prior art.
Because the offset voltage of the voltage comparator COMP1 is stored in the sample holder, the node voltage first comparison state value can be processed by using the offset voltage of the sample holder to obtain a node voltage second comparison state value for counteracting the offset voltage of the voltage comparator COMP1, AND the node voltage second comparison state value is output through the voltage comparator COMP1 AND the AND gate AND.
The processing of the node voltage first comparison state value by using the sampled and held offset voltage specifically means that the sampled and held offset voltage and the node voltage first comparison state value are operated, where the operation includes addition and subtraction, etc. in the technical field, the operation mode capable of offset voltage can be selected according to the need, and the specific operation mode is based on offset or elimination of offset voltage brought by the voltage comparator COMP 1.
When it is determined that the voltage of the node a is equal to the voltage of the node B based on the node voltage second comparison state value, the high level is output via the AND gate AND, so that the driving circuit outputs the rectifier driving control signal gt_lsd to flip to the low level, that is, turns off the synchronous rectifier fet_lst.
As can be seen from the above description, the voltage comparator COMP1 adopts the differential input and differential output modes, so that the switching noise of the switches SA1 and SA2, and the switching noise of the switches SB1 and SB2 can be effectively cancelled. The sample-and-hold circuit also adopts a double-ended output structure, and can cancel the switching noise of the switch SB3 and the switch SB 4. Therefore, compared with a single-end output comparator with only one stage, the automatic zero-setting comparator has the characteristics of good noise resistance and high precision. In addition, since the two-stage structure is adopted, the voltage comparator COMP1 can quickly amplify the input signal and input the amplified signal to the voltage comparator COMP2, so that the comparator is automatically zeroed and has the characteristics of high gain, high speed and the like.
As can be seen from the above description, when the driving circuit and the voltage comparator COMP1 operate, there is a delay time, which causes a delay error current to exist; in order to eliminate the delay error, in one embodiment of the present invention, a delay error current elimination circuit for eliminating the delay error is further included, wherein,
when the synchronous rectifier tube FET_LSD is driven to be conducted by the rectifier tube driving control signal GT_LSD, the automatic zero adjustment comparator is configured to compare the voltage of the node A with the voltage of the node B;
when the voltage of the node A is compared with the voltage of the node B, a delay error current eliminating circuit is utilized to load a rectifying tube turn-off compensation current based on delay time and output voltage to the node B, and when the voltage of the node A is equal to the voltage of the node B, a driving circuit controls a rectifying tube driving control signal GT_LSD to be in a low level state so as to turn off a synchronous rectifying tube FET_LSD.
As is clear from the above description, when the synchronous rectifier fet_lsd is in the on state, the voltage comparator COMP1 is used to compare the voltages of the node a and the node B. As is clear from the above description, when the voltage of the node a is equal to the voltage of the node B, the driving circuit sets the rectifier driving control signal gt_lsd to be in a low level state to turn off the synchronous rectifier fet_lsd, and when the synchronous rectifier fet_lsd is turned off, the flowing inductance L is not zero.
Therefore, to avoid that the current is not 0 when the synchronous rectifier fet_lsd is turned off, in one embodiment of the present invention, a rectifier turn-off compensation current is provided by the delay error current cancellation circuit and is applied to the node B. At this time, when the voltage of the node A is equal to the voltage of the node B, the driving circuit sets the rectifier driving control signal GT_LSD to be in a low level state after a delay time to turn off the synchronous rectifier FET_LSD, and the synchronous rectifier FET_LSD is turned off, the current I flowing through the inductor L L Is 0.
In one embodiment of the present invention, the delay error current cancellation circuit comprises a node voltage sample-to-current conversion circuit coupled to the node SW and a current mirror adapted to be coupled to the node voltage sample-to-current conversion circuit, wherein,
the current mirror is connected with the node B in an adaptive way;
the voltage of the node SW is converted into a compensation reference current based on delay time through a node voltage sampling-current conversion circuit, and the compensation reference current forms a rectifying tube turn-off compensation current through a current mirror and is loaded to the node B.
Specifically, the voltage of the node SW can be converted into a compensation reference current by the node voltage sampling-current conversion circuit, and the compensation current is formed into a rectifier tube turn-off compensation current by the current mirror, and then is loaded to the node B. The compensation reference circuit is related to the delay time, and the process of obtaining the compensation reference current is specifically described below.
In one embodiment of the present invention, the node voltage sampling-current conversion circuit includes an operational amplifier AMP, wherein,
the non-inverting terminal of the operational amplifier AMP is connected with one end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to form a node C;
the other end of the resistor R3 is connected with the node SW, the inverting end of the operational amplifier AMP is connected with the source end of the NMOS tube MN1 and one end of the resistor R5, the gate end of the NMOS tube MN1 is connected with the output end of the operational amplifier AMP, and the drain end of the NMOS tube MN1 is connected with the current mirror in an adaptive manner;
the other end of the capacitor C1, the other end of the resistor R4 and the other end of the resistor R5 are grounded;
when the current output by the current source IB1 is equal to the current output by the current source IB2 and the voltage of the node a is equal to the voltage of the node B, there are:
Figure BDA0004090964830000101
wherein R is 2 Is the resistance value of the resistor R2, R 3 Is the resistance value of the resistor R3, R 4 Is the resistance value of the resistor R4, t is the delay time of the driving circuit and the automatic zero-adjusting comparator, and R ds For the on-resistance of the synchronous rectifier fet_lsd, L is the impedance of the inductance L.
The current mirror comprises an NMOS transistor MN2 and an NMOS transistor MN3, wherein,
the gate terminal of the NMOS tube MN2 is connected with the source terminal of the NMOS tube MN2, the drain terminal of the NMOS tube MN1 and the gate terminal of the NMOS tube MN3, the source terminal of the NMOS tube MN3 is connected with the node B, and the drain terminal of the NMOS tube MN3 and the drain terminal of the NMOS tube MN2 are connected with the voltage VDD.
One embodiment of a node voltage sampling-to-current conversion circuit and a current mirror is shown in fig. 2, for the current mirror in fig. 2, when NMOS transistor MN2 and NMOS transistor MN3 have the same aspect ratio, then the rectifier turn-off compensation current is equal to the compensation reference current; of course, the width-to-length ratio of the corresponding conductive channels of the NMOS transistor MN2 and the NMOS transistor MN3 can also be adjusted, specifically, the requirement of practical application can be met.
As can be seen from the above description, the magnitude of the compensation reference current is directly related to the delay time, so that the parameters of the whole circuit need to be configured to fulfill the aim of eliminating the delay time. The relationship between the circuit parameters and the delay time is deduced. In the derivation, the following is specified: NMOS transistor MN2 and NMOS transistor MN3 have the same width to length ratio of conducting channel, and current IB outputted by current source IB1 1 Current IB output by current source IB2 2 Equal.
As can be seen from the above description and fig. 2, for node SW, the voltage at node SW is approximately:
V SW ≈-I L r ds (1)
the voltage at node B is:
V B ≈(IB 2 +IB 3 )R 2 -I L r ds (2)
and the voltage at node a is:
V A ＝IB 1 R 1 (3)
above, V SW For the voltage of node SW, V B For the voltage of node B, V A Is the voltage at node a.
When a current I flows through the inductor L L When larger, there is V A >V B . When a current I flows through the inductor L L At step-down, voltage V B Gradually rise when V A ＝V B And when the output voltage of the automatic zero-setting comparator becomes high, the FET_LSD of the synchronous rectification power tube is turned off through the driving circuit.
Since the voltage comparator COMP1 and the driving circuit have fixed time delay t, the voltage is reduced from V A ＝V B From time to time when the synchronous rectification power tube FET_LSD is turned off, during which the inductor current drops
Figure BDA0004090964830000111
/>
Thus, when V A ＝V B At the time, inductance L current I L The value of (2) should be
Figure BDA0004090964830000112
At this time, the synchronous rectifier fet_lsd is turned off, and the inductor current just reaches 0.
Bringing formula (4) into formula (2) and taking V as A ＝V B And IB (IB) 1 ＝IB 2 The method can be used for finishing and obtaining,
Figure BDA0004090964830000113
wherein IB is 3 The compensating current is turned off for the rectifying tube.
From the above description, the NMOS transistor MN2 and the NMOS transistor MN3 have the same width-to-length ratio of the conductive channel, and the voltages at the two input terminals of the operational amplifier AMP are equal, thereby obtaining
Figure BDA0004090964830000114
Wherein V is C For the voltage of node C, R 5 Is the resistance of the resistor R5.
In step-down DC-DC, the average voltage of the node SW is equal to the output voltage V O The capacitor C1 is added between the node C and the ground, so that the function of averaging voltage can be realized. Thus, the voltage at node C is equal to:
Figure BDA0004090964830000121
from formulae (5), (6) and (7)
Figure BDA0004090964830000122
Therefore, when circuit parameters are configured according to the formula (8), the rectifier tube turn-off compensation current corresponding to the delay time t can be obtained, the delay error current can be eliminated by utilizing the rectifier tube turn-off compensation current, and the reliability and the precision of zero current detection of the step-down DC-DC circuit by utilizing the synchronous rectifier tube FET_LSD are improved.
In summary, a high-precision zero current detection method can be obtained, and in one embodiment of the present invention, the zero current detection circuit is utilized to perform zero current detection on the step-down DC-DC circuit.
Specifically, according to the above description, a method and a process for performing zero detection may be obtained, and a specific method for detecting zero current may be referred to the above description, which is not repeated herein.

Claims (10)

1. A high precision zero current detection circuit, comprising:
a driving circuit for generating a rectifying tube driving control signal GT_LSD for driving the switching state of the synchronous rectifying tube FET_LSD and a switching tube driving control signal GT_HSD for driving and controlling the switching state of the switching tube FET_HSD, wherein the rectifying tube driving control signal GT_LSD is complementary to the switching driving control signal GT_HSD in phase;
the automatic zero-setting comparator is used for comparing the voltage of the node A and the voltage of the node B during zero current detection and comprises a voltage comparator COMP1 used for comparing the voltages and an offset voltage offset circuit used for eliminating offset voltage of the voltage comparator COMP1,
the voltage comparator COMP1 is connected with the input end of the driving circuit through an offset voltage counteracting circuit, and the offset voltage counteracting circuit receives a switching tube driving control signal GT_HSD output by the driving circuit;
when the switching tube FET_HSD is driven and controlled to be conducted based on the switching tube driving control signal GT_HSD, an offset voltage counteracting circuit is configured to sample and hold the offset voltage of the voltage comparator COMP1, and a low-level signal is output through the offset voltage counteracting circuit;
and when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, a node voltage first comparison state value generated during voltage comparison of the voltage comparator COMP1 is configured, the offset voltage offset circuit processes the node voltage first comparison state value by using the sampled offset voltage so as to obtain a node voltage second comparison state value for offset voltage of the voltage comparator COMP1, and the node voltage second comparison state value is output.
2. The high-precision zero-current detection circuit of claim 1, wherein: the offset voltage offset circuit comprises a sampling holder, a voltage comparator COMP2, an output connection circuit and a switch unit group for configuring the working state of the offset voltage offset circuit, wherein,
the differential output end of the voltage comparator COMP1 is connected with the differential input end of the sampling holder, the differential output end of the sampling holder is connected with the differential input end of the voltage comparator COMP2, the output end of the voltage comparator COMP2 is connected with the output connection circuit, and the switching tube driving control signal GT_HSD is received through the output connection circuit;
when the driving control switch tube FET_HSD is conducted based on the driving control signal GT_HSD of the switch tube, the switch unit group is configured so that the differential input end of the voltage comparator COMP1 is grounded, and the differential input end of the voltage comparator COMP2 is grounded with the bias voltage VB;
when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, the switch unit group is configured to utilize the voltage comparator COMP1 to conduct voltage comparison required during zero current detection, and the second comparison state value of the node voltage is output through the sampling keeper, the voltage comparator COMP2 and the output connection circuit in sequence.
3. The high-precision zero-current detection circuit of claim 2, wherein: the switch unit group comprises a switch SA1, a switch SA2, a switch SB1, a switch SB2, a switch SB3 and a switch SB4, wherein,
the first end of the switch SA1 is connected with the node B, the second end of the switch SA1 is connected with the first end of the switch SB1 and the same-phase end of the voltage comparator COMP1, the second end of the switch SB1 and the first end of the switch SB2 are grounded, the second end of the switch SB2 is connected with the first end of the switch SA2 and the opposite-phase end of the voltage comparator COMP1, and the second end of the switch SA2 is connected with the node A;
the first end of the switch SB3 is connected to the first output terminal OUT1 of the sample holder and the inverting input terminal of the voltage comparator COMP2, the second end of the switch SB3 and the first end of the switch SB4 are connected to the bias voltage VB, and the second end of the switch SB4 is connected to the second output terminal OUT2 of the sample holder and the non-inverting terminal of the voltage comparator COMP 2.
4. The high-precision zero-current detection circuit of claim 2, wherein: when the switching tube FET_HSD is driven AND controlled to be conducted based on the switching tube driving control signal GT_HSD of high level, the output connection circuit comprises an AND gate AND AND an inverter INV, wherein,
the input end of the inverter INV is used for receiving the switching tube driving control signal gt_hsd, the output end of the inverter INV is connected with one input end of the AND gate AND, the output end of the voltage comparator COMP2 is connected with the other input end of the AND gate AND, AND the output end of the AND gate AND is connected with the driving circuit in an adapting way.
5. The high-precision zero-current detection circuit according to any one of claims 1 to 4, characterized in that: and a delay error current cancellation circuit for canceling the delay error, wherein,
when the synchronous rectifier tube FET_LSD is driven to be conducted based on the rectifier tube driving control signal GT_LSD, an automatic zero adjustment comparator is configured to compare the voltage of the node A with the voltage of the node B;
when the voltage of the node A is compared with the voltage of the node B, a delay error current eliminating circuit is utilized to load a rectifying tube turn-off compensation current based on delay time and output voltage to the node B, and when the voltage of the node A is equal to the voltage of the node B, a driving circuit controls a rectifying tube driving control signal GT_LSD to turn off a synchronous rectifying tube FET_LSD based on the loaded rectifying tube turn-off compensation current.
6. The high-precision zero-current detection circuit of claim 5, wherein: the inverting terminal of the voltage comparator COMP1 is connected to one end of the resistor R1 and the output terminal of the current source IB1 to form a node a, where the other end of the resistor R1 is grounded;
the in-phase end of the voltage comparator COMP1 is adaptively connected with one end of a resistor R2, the output end of a current source IB2 and a delay error current cancellation circuit to form a node B, wherein the power supply end of the current source IB2 and the power supply end of the current source IB1 are both connected with a voltage VDD, and the other end of the resistor R2 is connected with the drain end of a synchronous rectifier tube fet_lsd, the source end of a control switch tube fet_hsd and one end of an inductor L to form a node SW;
the source terminal of the synchronous rectifying tube FET_LSD is grounded, the drain terminal of the control switching tube FET_HSD is connected with the voltage VIN, the gate terminal of the synchronous rectifying tube FET_LSD receives the rectifying tube driving control signal GT_LSD output by the driving circuit, the gate terminal of the control switching tube FET_HSD receives the switching tube driving control signal GT_HSD output by the driving circuit, and the output voltage Vo is obtained through the other end of the inductor L.
7. The high-precision zero-current detection circuit of claim 6, wherein: the delay error current eliminating circuit comprises a node voltage sampling-current converting circuit connected with the node SW and a current mirror connected with the node voltage sampling-current converting circuit in an adapting way, wherein,
the current mirror is connected with the node B in an adaptive way;
the voltage of the node SW is converted into a compensation reference current based on delay time through a node voltage sampling-current conversion circuit, and the compensation reference current forms a rectifying tube turn-off compensation current through a current mirror and is loaded to the node B.
8. The high-precision zero-current detection circuit of claim 7, wherein: the node voltage sampling-current conversion circuit includes an operational amplifier AMP, wherein,
the non-inverting terminal of the operational amplifier AMP is connected with one end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to form a node C;
the other end of the resistor R3 is connected with the node SW, the inverting end of the operational amplifier AMP is connected with the source end of the NMOS tube MN1 and one end of the resistor R5, the gate end of the NMOS tube MN1 is connected with the output end of the operational amplifier AMP, and the drain end of the NMOS tube MN1 is connected with the current mirror in an adaptive manner;
the other end of the capacitor C1, the other end of the resistor R4 and the other end of the resistor R5 are grounded;
when the current output by the current source IB1 is equal to the current output by the current source IB2 and the voltage of the node a is equal to the voltage of the node B, there are:
Figure FDA0004090964820000031
/>
wherein R is 2 Is the resistance value of the resistor R2, R 3 Is the resistance value of the resistor R3, R 4 Is the resistance value of the resistor R4, t is the delay time of the driving circuit and the automatic zero-adjusting comparator, and R ds For the on-resistance of the synchronous rectifier fet_lsd, L is the impedance of the inductance L.
9. The high-precision zero-current detection circuit of claim 8, wherein: the current mirror comprises an NMOS transistor MN2 and an NMOS transistor MN3, wherein,
the gate terminal of the NMOS tube MN2 is connected with the source terminal of the NMOS tube MN2, the drain terminal of the NMOS tube MN1 and the gate terminal of the NMOS tube MN3, the source terminal of the NMOS tube MN3 is connected with the node B, and the drain terminal of the NMOS tube MN3 and the drain terminal of the NMOS tube MN2 are connected with the voltage VDD.
10. A high-precision zero-current detection method, characterized in that the zero-current detection circuit according to any one of claims 1 to 9 is used for zero-current detection of a step-down DC-DC circuit.
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