CN117768011A - FPGA-based adaptive transmission system, method, equipment and medium - Google Patents
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Abstract
The invention provides an adaptive transmission system, method, equipment and medium based on an FPGA. Belonging to the technical field of satellite communication. The adaptive transmission system includes a receiver module, a data processing module, and a transmitter module. The system and the method can adaptively adjust the system parameters according to different channel conditions, and effectively improve the utilization rate of the system spectrum while meeting the error code performance of the system.
Description
Technical Field
the invention belongs to the technical field of satellite communication, and particularly relates to an adaptive transmission system, method, equipment and medium based on an FPGA.
Background
FPGA (field programmable gate array) has the characteristics of rich wiring resources, high repeatability and integration level and low investment, is widely applied in the field of digital circuit design, has the main difficulty of familiarity with hardware systems and internal resources, ensures that the designed language can realize effective coordination among components, improves the readability and the utilization rate of programs, and puts forward higher requirements for designers.
Satellite communication has the advantages of wide coverage, long transmission distance, large communication capacity, good transmission quality, flexible and rapid networking, high confidentiality and the like, and becomes a communication means with great competition at present.
Due to the complexity of satellite communication environment changes, the same transmission mode can greatly restrict the communication efficiency of the whole system. The conventional satellite data transmission system with simple technology and extensive resources has been used for decades, the technology system adopted by the existing link is made into a fixed code modulation mode (Constant Coding and Modulation, CCM), and the data transmission capability is approaching to the limit of the capability.
Disclosure of Invention
The invention aims to solve the problem of larger link gain waste caused by adopting a CCM modulation technology for the existing satellite communication link, and provides an adaptive transmission system, method, equipment and medium based on FPGA. The system and the method can adaptively adjust the system parameters according to different channel conditions, and effectively improve the utilization rate of the system spectrum while meeting the error code performance of the system.
The invention is realized by the following technical scheme, and provides an adaptive transmission system based on an FPGA, which is developed on an FPGA development board and comprises a receiver module, a data processing module and a transmitter module;
the receiver module is used for receiving signals, demodulating the received signals and estimating the signal to noise ratio, and inputting the demodulated signals to the data processing module;
The data processing module is used for receiving the signal sent by the receiver module, performing data processing on the signal and outputting the processed data to the transmitter module;
The transmitter module is used for receiving the signals processed by the data processing module and transmitting and outputting the signals.
Further, the receiver module outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
Further, the receiver module comprises a sampling unit, a frequency discrimination unit, a bit synchronization unit, a signal-to-noise ratio estimation unit and a carrier recovery loop; after the signal is input to the receiver module, the signal firstly enters the sampling unit to be subjected to downsampling to obtain downsampled data, the downsampled data is sent to the frequency discrimination unit to be subjected to carrier frequency coarse synchronization, the signal after carrier frequency coarse synchronization is input to the bit synchronization unit to be subjected to clock error correction to obtain demodulated signal output, the corrected data is input to the signal to noise ratio estimation unit to estimate the signal to noise ratio of the signal, an adaptive rate control signal is output, and meanwhile, the corrected data is input to the carrier recovery loop to be subjected to phase error correction.
further, the signal-to-noise ratio estimation unit outputs the self-adaptive rate control signal according to the signal-to-noise ratio and the error rate index requirement of the system by using a segmentation estimation algorithm combining a square signal and noise variance estimation method and a polynomial data fitting estimation method.
further, the data processing module decodes the input demodulation signal by using a Viterbi decoder, performs frame synchronization processing, and then outputs the decoded signal after RS encoding and de-interleaving.
Further, the transmitter module receives the adaptive rate control signal, selects interpolation extraction multiples of corresponding gears by using an interpolation extraction module, and then adjusts sampling points of each symbol of the signal to realize rate adjustment of the demodulated signal.
The invention provides an adaptive transmission method based on an FPGA, which is realized by using the adaptive transmission system, wherein the adaptive transmission system is developed on an FPGA development board, and the adaptive transmission method specifically comprises the following steps:
the receiver module receives the signals, demodulates the received signals and estimates the signal to noise ratio, and inputs the demodulated signals to the data processing module; the data processing module receives the signal sent by the receiver module, processes the signal and outputs the processed data to the transmitter module; the transmitter module receives the signals processed by the data processing module and transmits and outputs the signals.
Further, the receiver module outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
the invention provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the self-adaptive transmission method based on the FPGA when executing the computer program.
The present invention proposes a computer readable storage medium for storing computer instructions which, when executed by a processor, implement the steps of the FPGA-based adaptive transmission method.
Compared with the prior art, the invention has the following advantages:
1. The invention is based on an FPGA realization platform, carries out signal-to-noise ratio estimation on the received signals and outputs the self-adaptive rate control signals, can self-adaptively adjust system parameters according to different channel conditions, and effectively improves the utilization rate of the system spectrum while meeting the performance of system error codes.
2. The self-adaptive transmission system based on the FPGA is suitable for the satellite communication field, can adapt to the random change condition of a channel, and avoids great link resource waste.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
fig. 1 is a schematic diagram of a baseband processing FPGA development board.
Fig. 2 is a general flow chart of an adaptive transmission system based on an FPGA.
Fig. 3 is a flowchart of an algorithm of the signal-to-noise ratio estimation unit in the embodiment.
Detailed Description
the following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
1-3, the invention provides an adaptive transmission system based on an FPGA, which is developed on an FPGA development board and comprises a receiver module, a data processing module and a transmitter module;
the receiver module is used for receiving signals, demodulating the received signals and estimating the signal to noise ratio, and inputting the demodulated signals to the data processing module;
The data processing module is used for receiving the signal sent by the receiver module, performing data processing on the signal and outputting the processed data to the transmitter module;
The transmitter module is used for receiving the signals processed by the data processing module and transmitting and outputting the signals.
The receiver module also outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
The receiver module comprises a sampling unit, a frequency discrimination unit, a bit synchronization unit, a signal-to-noise ratio estimation unit and a carrier recovery loop; after the signal is input to the receiver module, the signal firstly enters the sampling unit to be subjected to downsampling to obtain downsampled data, the downsampled data is sent to the frequency discrimination unit to be subjected to carrier frequency coarse synchronization, the signal after carrier frequency coarse synchronization is input to the bit synchronization unit to be subjected to clock error correction to obtain demodulated signal output, the corrected data is input to the signal to noise ratio estimation unit to estimate the signal to noise ratio of the signal, an adaptive rate control signal is output, and meanwhile, the corrected data is input to the carrier recovery loop to be subjected to phase error correction.
the signal-to-noise ratio estimation unit outputs an adaptive rate control signal according to the signal-to-noise ratio and the bit error rate index requirement of the system by using a segmentation estimation algorithm combining a square signal and noise variance estimation method and a polynomial data fitting estimation method.
the data processing module decodes the input demodulation signal by using a Viterbi decoder, performs frame synchronization processing, and then outputs the decoded signal after RS encoding and de-interleaving.
The transmitter module receives the self-adaptive rate control signal, selects interpolation extraction multiples of corresponding gears by utilizing an interpolation extraction module, and then adjusts sampling points of each symbol of the signal so as to realize rate adjustment of the demodulated signal.
The invention provides an adaptive transmission method based on an FPGA, which is realized by using the adaptive transmission system, wherein the adaptive transmission system is developed on an FPGA development board, and the adaptive transmission method specifically comprises the following steps:
the receiver module receives the signals, demodulates the received signals and estimates the signal to noise ratio, and inputs the demodulated signals to the data processing module; the data processing module receives the signal sent by the receiver module, processes the signal and outputs the processed data to the transmitter module; the transmitter module receives the signals processed by the data processing module and transmits and outputs the signals.
The receiver module also outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
Examples
The specific implementation mode of the invention is based on an XC7VX690T development platform of Xilinx company, a V7 series development board of Siilinx company (Xilinx) is adopted as a baseband processing board, and the signal processing of the received signal is completed, including synchronization, demodulation, decoding and the like, and in the FPGA, 21 ten thousand LUTs are used as LUT resources, and the resources occupy about 55%; BRAM resources occupy about 20%; the occupation of DSP resources is less than 60%; the XC7VLX690T device can meet the resource use requirement and the derating requirement, and simultaneously provides a special IP core for configuration, thereby greatly simplifying the design of the interface. The baseband processing development board mainly realizes the functions of filtering sampling, digital demodulation and decoding, self-adaptive rate control, digital coding and modulation and the like of signals. The FPGA provides a UART serial port, and the serial port and the upper computer are used for transmitting remote control and telemetry signals.
as best understood with reference to fig. 1 and 2, the present invention proposes an adaptive transmission system based on an FPGA, the adaptive transmission system being developed on an FPGA development board, the adaptive transmission system including a receiver module, a data processing module, and a transmitter module;
the receiver module is used for receiving signals, demodulating the received signals and estimating the signal to noise ratio, and inputting the demodulated signals to the data processing module;
The data processing module is used for receiving the signal sent by the receiver module, performing data processing on the signal and outputting the processed data to the transmitter module;
The transmitter module is used for receiving the signals processed by the data processing module and transmitting and outputting the signals.
The receiver module also outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
The receiver module comprises a sampling unit, a frequency discrimination unit, a bit synchronization unit, a signal-to-noise ratio estimation unit and a carrier recovery loop; after the signal is input to the receiver module, the signal firstly enters the sampling unit to be subjected to downsampling to obtain downsampled data, the downsampled data is sent to the frequency discrimination unit to be subjected to carrier frequency coarse synchronization, the signal after carrier frequency coarse synchronization is input to the bit synchronization unit to be subjected to clock error correction to obtain demodulated signal output, the corrected data is input to the signal to noise ratio estimation unit to estimate the signal to noise ratio of the signal, an adaptive rate control signal is output, and meanwhile, the corrected data is input to the carrier recovery loop to be subjected to phase error correction.
the signal-to-noise ratio estimation unit outputs an adaptive rate control signal according to the signal-to-noise ratio and the bit error rate index requirement of the system by using a segmentation estimation algorithm combining a square signal and noise variance estimation method and a polynomial data fitting estimation method.
the data processing module decodes the input demodulation signal by using a Viterbi decoder, performs frame synchronization processing, and then outputs the decoded signal after RS encoding and de-interleaving.
The transmitter module receives the self-adaptive rate control signal, selects interpolation extraction multiples of corresponding gears by utilizing an interpolation extraction module, and then adjusts sampling points of each symbol of the signal so as to realize rate adjustment of the demodulated signal.
For example, the snr estimation unit algorithm in this embodiment is shown in fig. 3, and by using a segmentation estimation algorithm combining a square signal and noise variance estimation method and a polynomial data fitting estimation method, the snr range is estimated by using a 2-order polynomial data fitting estimation method with relatively low complexity, and the calculation formula is as follows:
In the/>Representing the real part of the signal received by the receiver,/>representing the corresponding imaginary part of the signal received by the receiver,/>Indicating the desire.
Under the condition of low signal-to-noise ratio, a 3-order polynomial data fitting estimation method is adopted, and the calculation formula is as follows:
The signal to noise ratio of the signal is obtained by adopting a square signal and noise variance estimation method under the condition of high signal to noise ratio, and the calculation formula is as follows:
In the method, in the process of the invention,representing the estimated sequence length of the received signal,/>representing the real part of the sign value of the corresponding signal,/>representing the real part of the receiver signal,/>Representing the imaginary part of the signed value of the corresponding signal,/>Representing the imaginary part of the receiver signal.
And outputting an adaptive rate control signal according to the signal-to-noise ratio and the error rate index requirement of the system.
the invention provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the self-adaptive transmission method based on the FPGA when executing the computer program.
The present invention proposes a computer readable storage medium for storing computer instructions which, when executed by a processor, implement the steps of the FPGA-based adaptive transmission method.
The memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a Read Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
In implementation, each step of the method may be implemented by an integrated logic circuit of hardware in a processor or an instruction in a form of a software component. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, or discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
The self-adaptive transmission system, method, equipment and medium based on FPGA provided by the invention are described in detail, and specific examples are applied to illustrate the principle and implementation of the invention, and the description of the above examples is only used for helping to understand the method and core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (8)
1. an adaptive transmission system based on an FPGA is characterized in that the adaptive transmission system is developed on an FPGA development board and comprises a receiver module, a data processing module and a transmitter module;
the receiver module is used for receiving signals, demodulating the received signals and estimating the signal to noise ratio, and inputting the demodulated signals to the data processing module;
The data processing module is used for receiving the signal sent by the receiver module, performing data processing on the signal and outputting the processed data to the transmitter module;
The transmitter module is used for receiving the signals processed by the data processing module and transmitting and outputting the signals;
The receiver module also outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and sends the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data;
The receiver module comprises a sampling unit, a frequency discrimination unit, a bit synchronization unit, a signal-to-noise ratio estimation unit and a carrier recovery loop; after the signal is input to the receiver module, the signal firstly enters the sampling unit to be subjected to downsampling to obtain downsampled data, the downsampled data is sent to the frequency discrimination unit to be subjected to carrier frequency coarse synchronization, the signal after carrier frequency coarse synchronization is input to the bit synchronization unit to be subjected to clock error correction to obtain demodulated signal output, the corrected data is input to the signal to noise ratio estimation unit to estimate the signal to noise ratio of the signal, an adaptive rate control signal is output, and meanwhile, the corrected data is input to the carrier recovery loop to be subjected to phase error correction.
2. The adaptive transmission system according to claim 1, wherein the signal-to-noise ratio estimation unit outputs the adaptive rate control signal according to the signal-to-noise ratio and the bit error rate index requirement of the system by using a segmentation estimation algorithm combining a square signal with a noise variance estimation method and a polynomial data fitting estimation method.
3. The adaptive transmission system according to claim 2, wherein the data processing module decodes the input demodulated signal using a Viterbi decoder, performs frame synchronization processing, and then performs RS encoding and de-interleaving for output.
4. The adaptive transmission system of claim 3, wherein the transmitter module receives the adaptive rate control signal, selects an interpolation extraction multiple of a corresponding gear using an interpolation extraction module, and then adjusts a sampling point of each symbol of the signal to achieve rate adjustment of the demodulated signal.
5. an adaptive transmission method based on an FPGA, wherein the adaptive transmission method is implemented by using the adaptive transmission system according to any one of claims 1 to 4, the adaptive transmission system is developed on an FPGA development board, and the adaptive transmission method specifically includes:
the receiver module receives the signals, demodulates the received signals and estimates the signal to noise ratio, and inputs the demodulated signals to the data processing module; the data processing module receives the signal sent by the receiver module, processes the signal and outputs the processed data to the transmitter module; the transmitter module receives the signals processed by the data processing module and transmits and outputs the signals.
6. The adaptive transmission method according to claim 5, wherein the receiver module further outputs an adaptive rate control signal when performing demodulation and signal-to-noise ratio estimation, and transmits the adaptive rate control signal to the transmitter module; the transmitter module modulates the processed data according to the received self-adaptive rate control signal and then transmits and outputs the data.
7. an electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 5-6 when the computer program is executed.
8. A computer readable storage medium storing computer instructions which, when executed by a processor, implement the steps of the method of any one of claims 5-6.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020080619A (en) * | 2001-04-16 | 2002-10-26 | 주식회사 케이티 | Receiving device and method for time/frequency synchronizing system using satellites |
| CN110943752A (en) * | 2019-10-17 | 2020-03-31 | 南京航空航天大学 | OQPSK self-adaptive variable rate digital transceiver based on adjacent space link protocol |
| CN114362803A (en) * | 2021-12-15 | 2022-04-15 | 长光卫星技术有限公司 | Continuous variable rate satellite communication transponder system based on FPGA |
-
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- 2024-02-22 CN CN202410195348.4A patent/CN117768011A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020080619A (en) * | 2001-04-16 | 2002-10-26 | 주식회사 케이티 | Receiving device and method for time/frequency synchronizing system using satellites |
| CN110943752A (en) * | 2019-10-17 | 2020-03-31 | 南京航空航天大学 | OQPSK self-adaptive variable rate digital transceiver based on adjacent space link protocol |
| CN114362803A (en) * | 2021-12-15 | 2022-04-15 | 长光卫星技术有限公司 | Continuous variable rate satellite communication transponder system based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 李翔宇: "基于邻近空间链路协议的自适应传输***设计", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》, 25 July 2021 (2021-07-25), pages 11 - 12 * |
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