CN114598423B - Method, device and medium for demodulation and decoding combined GMSK and LDPC - Google Patents
Method, device and medium for demodulation and decoding combined GMSK and LDPC Download PDFInfo
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Abstract
The embodiment of the invention discloses a method, a device and a medium for demodulating and decoding combined GMSK and LDPC; the method may include: the baseband digital signal of the received signal is subjected to low-pass filtering and downsampling processing to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode; performing differential processing on the filtered digital signals to obtain differential digital signals; diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data; carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position; and based on the synchronous position, carrying out demodulation and decoding on the digital signals after diversity combination by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
Description
Technical Field
The embodiment of the invention relates to the technical field of wireless communication, in particular to a method, a device and a medium for demodulating and decoding combined Gaussian minimum shift keying (GMSK, gaussian Filtered Minimum Shift Keying) and low-density parity check (LDPC, low Density Parity Check).
Background
The low density parity check (LDPC, low Density Parity Check) code is a linear block code that can be described by a sparse check matrix, and was first proposed by Gallager in 1962, and is therefore also called Gallager code. The LDPC code has decoding performance very close to Shannon (Shannon) limit, and the linear decoding complexity is lower; therefore, the LDPC code has important application value in both theory and practical application. However, when the decoding algorithm of the LDPC is specifically implemented by using actual hardware, a certain storage space is required to be consumed to store the relevant check matrix, so that a larger hardware resource is required.
The combined Gaussian minimum shift keying (GMSK, gaussian Filtered Minimum Shift Keying) is a continuous phase modulation mode and has high spectrum utilization rate. According to the modulation scheme, modulated non-return-to-zero data firstly passes through a Gaussian pulse shaping filter, so that sidelobes on the frequency spectrum of the modulated non-return-to-zero data are reduced, the frequency spectrum is more compact, out-of-band energy radiation is smaller, and adjacent channel interference is smaller. The conventional receiver processing scheme for GMSK separates demodulation and decoding, and such processing cannot make full use of correlation between received symbols, so that the best demodulation effect cannot be achieved.
With the current continuous improvement of the requirements for communication capability and communication reliability, a processing scheme with better performance is required to process the GMSK receiving end.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a method, apparatus, and medium for demodulation and decoding combining GMSK and LDPC; the method can realize the reliable demodulation and decoding of the signals in the low signal-to-noise ratio environment, ensure the safety of information transmission, improve the interference tolerance of a communication system and reduce the complexity of the system.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a demodulation and decoding method for combining gaussian minimum shift keying GMSK and low density parity check LDPC, where the method is applied to a receiving end device, and the method includes:
the baseband digital signal of the received signal is subjected to low-pass filtering and downsampling processing to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
performing differential processing on the filtered digital signals to obtain differential digital signals;
Diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
and based on the synchronous position, carrying out demodulation and decoding on the digital signals after diversity combination by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
In a second aspect, an embodiment of the present invention provides a demodulation and decoding method for combining gaussian minimum shift keying GMSK with low density parity check LDPC, where the method is applied to a transmitting end device, and the method includes:
after information data sent by an information source is encoded according to an LDPC encoding algorithm, the encoded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of multiple pilot frequency data and multiple information data;
and carrying out GMSK modulation on the frame data to be transmitted, and transmitting the modulated frame data to be transmitted to a free space, so that the receiving end equipment carries out demodulation and decoding according to a received receiving signal by the demodulation and decoding method of the joint GMSK and the LDPC according to the first aspect.
In a third aspect, an embodiment of the present invention provides a receiving end device, where the receiving end device includes: the device comprises a preprocessing part, a differential processing part, a diversity combining part, a synchronizing part and a joint demodulation decoding part; wherein,
The preprocessing part is configured to perform low-pass filtering and downsampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
the differential processing part is configured to perform differential processing on the filtered digital signals to obtain differential digital signals;
the diversity combining part is configured to diversity combine the digital signals after the difference according to pilot frequency data and information data respectively;
the synchronization part is configured to perform frame synchronization and bit synchronization on the digital signals after diversity combination to obtain synchronization positions;
the joint demodulation decoding part is configured to perform joint GMSK and LDPC demodulation decoding on the diversity-combined digital signals in an inner and outer iteration mode based on the synchronous position, so as to obtain decoded data.
In a fourth aspect, an embodiment of the present invention provides a transmitting end device, where the transmitting end device includes: a coding section, a time diversity combining section, a modulating section, and a transmitting section; wherein,
The encoding part is configured to encode information data sent by the information source according to an LDPC encoding algorithm;
the time diversity combining part is configured to combine the coded information data and pilot frequency data into frame data to be transmitted in a time diversity structure in a mode of multiple pilot frequency data and multiple information data;
the modulating part is configured to perform GMSK modulation on the frame data to be sent;
the transmitting part is configured to transmit the modulated frame data to be transmitted to free space, so that the receiving end device performs demodulation decoding according to the received signal by the demodulation decoding method of the joint GMSK and LDPC according to the first aspect.
In a fifth aspect, an embodiment of the present invention provides a communication device including a communication interface, a memory, and a processor; the components are coupled together by a bus system; wherein,
the communication interface is used for receiving and transmitting signals in the process of receiving and transmitting information with other external network elements;
the memory is used for storing a computer program capable of running on the processor;
the processor is configured to execute the steps of the demodulation decoding method of combining GMSK and LDPC in the first aspect or the second aspect when the computer program is executed.
In a sixth aspect, an embodiment of the present invention provides a computer storage medium, where a demodulation and decoding program of joint GMSK and LDPC is stored, where the demodulation and decoding program of joint GMSK and LDPC is executed by at least one processor to implement the demodulation and decoding method steps of joint GMSK and LDPC in the first aspect or the second aspect.
The embodiment of the invention provides a method, a device and a medium for demodulating and decoding combined GMSK and LDPC; the method realizes the demodulation and decoding of GMSK and LDPC under the condition of low signal-to-noise ratio of signals through joint iteration, adopts a time diversity mode to improve the interference tolerance of the system, adopts a differential mode to reduce the influence caused by frequency offset and carries out diversity combination, and reduces the complexity of the system by constructing a quasi-cyclic LDPC matrix, thereby realizing the reliable demodulation of GMSK signals under the condition of lower signal-to-noise ratio and ensuring the safety of information transmission.
Drawings
Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention;
fig. 2 is a flow chart of a method for a receiving end device to perform demodulation decoding of joint GMSK and LDPC according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the position and the size of a correlation peak after sliding correlation using a matched filter according to an embodiment of the present invention;
Fig. 4 is a schematic diagram of GMSK modulation flow provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an LDPC decoding process according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an update flow of check nodes according to an embodiment of the present invention;
fig. 7 is a schematic diagram of the composition of a variable node processing unit and a decision output unit according to an embodiment of the present invention;
fig. 8 is a flow chart of a joint GMSK demodulation and LDPC decoding scheme according to an embodiment of the present invention;
fig. 9 is a schematic flow chart of a method for performing demodulation and decoding by combining GMSK and LDPC by a transmitting device according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a frame structure of time diversity transmission according to an embodiment of the present invention;
FIG. 11 is a graph of bit error rate performance of joint demodulation iterations under different signal-to-noise ratios;
fig. 12 is a schematic diagram of a composition of a receiving-end device according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a composition of a transmitting end device according to an embodiment of the present invention;
fig. 14 is a schematic diagram of a specific hardware structure of a communication device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Aiming at the content related to the background technology, the inventor finds that the check matrix of the quasi-cyclic LDPC code (QC-LDPC) has the characteristic of quasi-cyclic in the implementation process, and according to the characteristic of quasi-cyclic, only the shift frequency information of the check matrix is needed to be stored, so that the information of the whole check matrix can be obtained by utilizing the quasi-cyclic characteristic of the check matrix, the storage space can be reduced, and in addition, iterative updating is carried out in a block parallel mode in the decoding process, so that the consumption of hardware resources can be reduced, the time consumed by decoding can be reduced, and the balance between the resource consumption and the time consumption is achieved. In addition, because the related log-likelihood ratio information is generated or needed in the GMSK demodulation process and the LDPC decoding process, the two independent processes of the GMSK demodulation process and the LDPC decoding process in the conventional scheme can be combined to realize the demodulation and decoding of the combined GMSK and the LDPC, and the related information among all received code elements is fully utilized, so that the error probability is reduced, reliable demodulation is formed, and the safety of information transmission is ensured.
Based on this, an embodiment of the present invention is expected to provide a demodulation and decoding scheme combining GMSK and LDPC, and with respect to this scheme, referring to fig. 1, a communication system 10 to which the technical scheme of the embodiment of the present invention can be applied is shown, where the system 10 may include a transmitting end device 11 and a receiving end device 12. As shown in connection with fig. 1, the receiving device 12 may perform a method for combining GMSK and LDPC demodulation decoding as shown in fig. 2, where the method may include:
S201: the baseband digital signal of the received signal is subjected to low-pass filtering and downsampling processing to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting terminal device 11 carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
s202: performing differential processing on the filtered digital signals to obtain differential digital signals;
s203: diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
s204: carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
s205: and based on the synchronous position, carrying out demodulation and decoding on the digital signals after diversity combination by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
Through the technical scheme shown in fig. 2, the demodulation and decoding of GMSK and LDPC under the condition of low signal-to-noise ratio of signals are realized through joint iteration, the interference tolerance of a system is improved in a time diversity mode, the influence caused by frequency offset is reduced in a differential mode, diversity combination is carried out, the complexity of the system is reduced by constructing a quasi-cyclic LDPC matrix, the reliable demodulation of GMSK signals under the condition of low signal-to-noise ratio can be realized, and the safety of information transmission is ensured.
For the technical solution shown in fig. 2, in some possible implementations, the performing differential processing on the filtered digital signal to obtain a differential digital signal includes:
and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
For the above implementation, in particular, since GMSK is a continuous phase modulation scheme, signal reception errors may be caused by frequency offset and phase offset, and since the transmitting end device 11 adopts a time diversity technique, diversity combining of the received signals of the receiving end device 12 is required. Furthermore, since GMSK uses phase change rather than stationary phase to transfer information, the received signals cannot be directly added to the simple signals, and differential processing is required. For differential processing, the detailed process is to delay the received signal with the current received signalConjugate multiplication is carried out, so as to obtain sine and cosine values of the phase change of the front signal and the back signal, and the digital baseband signal of the receiving signal is set as follows: r (k) =i (k) +j Q (k); then the differential I-way data I d(k) And Q-way data Q d(k) The method comprises the following steps of:
I d(k) ＝I(k)I(k-1)+Q(k)Q(k-1)
Q d(k) ＝I(k)Q(k-1)-Q(k)I(k-1)。
for the technical solution shown in fig. 2, in some possible implementations, diversity combining the digital signals after the differentiating according to pilot data and information data includes:
and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after difference, and respectively obtaining the combined pilot frequency data and the combined information data.
For the above implementation manner, specifically, the diversity combining scheme adopted in the embodiment of the present invention belongs to equal gain combining, for example, the time diversity transmission manner adopted by the transmitting end device 11 is set to transmit three pieces of pilot data first and then transmit three pieces of information data, and accordingly, the receiving end device 12 needs to combine the information data length and the pilot data length respectively. The receiving end device 12 is set to have 8 points for each chip sampling point, the pilot data length is 96, and the information data length is 2880, so that the total length of the pilot data is 96×8=762, that is, the pilot needs to perform equal gain combination of 762 data length, and the information data similarly needs to perform equal gain combination of 2880×8=23040.
Based on the above implementation, in some examples, the performing frame synchronization and bit synchronization on the digital signals after diversity combining to obtain a synchronization position includes:
Carrying out matched filtering on the combined pilot frequency data by using waveform data which are obtained by differentiating three sections of pilot frequency data as a matched filter of coefficients;
determining a local peak value in the data after the matched filtering as the maximum value in correlation values appearing in the frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the sampling point number by using the maximum value of the frame synchronization.
For the above example, it should be noted that the purpose of synchronization is to find a starting point of information data transmission in each frame and provide an accurate bit synchronization point for performing joint demodulation decoding subsequently. The embodiment of the invention adopts a scheme of adopting a matched filter for sliding correlation. In detail, the local pseudo code data used for sliding correlation is correlated with the combined differential signal. For example, the local pseudo code sequence adopts complex information of difference after the modulation of the 32×3 long PN sequence, and each chip samples 8 points, i.e. the length of the local pseudo code sequence is 3×32×8, and the local pseudo code sequence is divided into three sections to be used as coefficients of a filter respectively, and sliding correlation is performed by adopting a scheme of a matched filter, as shown in fig. 3, and finally, the correlation amplitude is obtained by adding 3 modules.
Specifically, since the transmitting end device 11 adopts a diversity transmission manner, the correlation peak is not unique, and the position and the size of the correlation peak after correlation shown in fig. 3 are continued to be referred to. Because the correlation amplitude decreases as the signal-to-noise ratio deteriorates, and in order to be able to ensure that the captured peak is maximum, embodiments of the present invention are not able to perform frame synchronization using only the absolute threshold method.
In detail, the specific capturing steps in the frame synchronization process are as follows:
first, the captured current sample point A is guaranteed r(k) The sample value of the 96 th x 8=768 th position before and the sample value of the 96 th x 8=768 th position after are smaller than the current sample value a r(k) Namely, the following conditions are satisfied: a is that r(k) ≥λ 1 A r(k+768) 、……、A r(k) ≥λ 1 A r(k-768) Wherein lambda is 1 Representing the set coefficients;
then, a relative threshold method is adopted, namely 2 signals before the threshold value passes through the current sample point value are added with 2 signals after the current sample point value, and the sum is multiplied by a set threshold coefficient, namely, the threshold value A is satisfied r(k) More than or equal to Threshold, wherein threshold=β (A r(k-2) +A r(k-1) +A r(k+1) +A r(k+2) ) Beta represents the settingCoefficients of (2); when the two conditions are met, the current sample point value can be preliminarily considered as a correlation peak value.
Finally, it is necessary to ensure that the correlation peak of the current sample value is the maximum of the correlation values that occur in this frame, i.e. to determine whether A is satisfied r(k) Gtoreq α max_frame, wherein max_frame=max (a r(n) ) N=0..k-8, i.e. max_frame is the maximum of the correlation peaks before the current chip in the present frame, and this value is reset to zero after synchronization is completed. Alpha is a coefficient greater than zero.
When the above three conditions are satisfied and the duration is longer than the duration of three samples, the peak value is considered to be true, and further the frame synchronization is considered to be completed.
For bit synchronization, the chips are extracted at timing to find the best samples of the signal. In the embodiment of the invention, the number of the sampling points of the chip is set to be 8, namely, the optimal sampling points are extracted from 8 sampling points. And searching the maximum correlation peak around the frame synchronization by using the position of the frame synchronization. And performing serial-parallel conversion on the correlation values, and comparing the magnitudes of eight correlation values near the frame synchronization position, so as to determine the optimal sampling point. The optimal sampling point thus obtained is then the determined synchronization position.
For the technical solution shown in fig. 2, in some possible implementations, based on the synchronization position, the demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an inner-outer iteration manner to obtain decoded data includes:
Performing correlation calculation according to the information data in the diversity-combined digital signals and path information of different states to obtain initial log likelihood ratio information from the previous state to the state at the current moment; and entering an external iteration;
in the current external iteration process, updating forward and backward path metric information based on the initial log-likelihood ratio information and a MAX-LOP-MAP algorithm;
acquiring updated log-likelihood ratio information of a current external iterative process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iterative process as initialized log-likelihood ratio information for LDPC decoding;
the information transmitted by the check node to the variable node and the information transmitted by the variable node to the check node are updated alternately by using the initialized log likelihood ratio information loop for LDPC decoding in an internal iteration mode until the set internal iteration times are reached;
when the set internal iteration times are reached, outputting variable node information updated and obtained in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information updated and obtained in the final internal iteration process is used as initial log likelihood ratio information for carrying out the next external iteration process;
And if the current external iteration times are the set external iteration times, outputting variable node information updated and obtained in the final internal iteration process as decoded data obtained by demodulating and decoding the joint GMSK and the LDPC.
For the above implementation manner, it should be noted that, for the GMSK modulation process, the embodiment of the present invention uses a Max-Log-Map algorithm, as shown in fig. 4, after obtaining the digital signal after diversity combining, the information data in the digital signal may be calculated as initial path metric information, that is, the signal to be demodulated is correlated with the path information of different states stored in advance in the receiving end device 11, so as to obtain Log likelihood ratio information from the last state to the state at the moment, that is, initial Log likelihood ratio information as initial path metric information; in this embodiment, the number of states known by GMSK modulation is 16 in total, each having 2-state transition paths, and the number of states after difference is 8, each having 2-state transition paths. Based on this, the initial log likelihood ratio information λ k [c i (e)；I]The following formula is shown:
wherein c (e) represents a codeword symbol; n=1, 2.n represents the nth sample of the received symbol at time k, And->In-phase and quadrature components, respectively, of locally stored initial state path information +.>Representing the 16 phase values corresponding to the current sample point and locally stored; the transmission symbol is set asIt follows that one chip needs to calculate the initial likelihood information for 16 paths.
Then, the forward and backward path metric information can be updated by using the above information, and when the forward path metric information is calculated as shown in the following formula, it can be known that the path metric information of the current state is related to the previous state;
wherein,i.e. the last (k-1) state +.>State metric information of (2); lambda (lambda) k (c (e); I) is from->Initial path metric information to s-state, lambda k (u (e); I) is similar to the kth bit channel informationHowever, the ratio information may be likelihood information after GMSK demodulation or may be transmitted back after LDPC decoding.
The three pieces of transmission information of different paths are added and compared, and the maximum likelihood information is selected as the present state, so that the forward path metric information is updated in sequence.
Similarly, it can be seen that the calculated backward path metric information is as follows:
from the above equation, the path metric information of the present state is related to the next (k+1th) state, and thus, the backward path metric information is updated in the reverse order. When updating the path metric information, the accumulated value of all the path metric information reaching the current state is calculated, and the maximum value is regarded as the optimal path to be stored.
Finally, the updated log likelihood ratio information lambda is calculated by utilizing the initial path metric information, the forward path metric information and the backward path metric information according to the above method k (u (e); O) if the number of iterations is set, the information is regarded as GMSK demodulated signal and output, and if the number of iterations is not set, the likelihood information lambda is obtained k (u (e); O) is re-treated as initial log-likelihood ratio information lambda k (u (e); I) and iterating again.
In addition, it should be further noted that, for the LDPC decoding process, the embodiment of the present invention preferably performs LDPC decoding by using a modified min-sum algorithm, where the modification factor is 0.8, and the flow is shown in fig. 5. Firstly, initializing variable nodes and check nodes, namely processing and storing LLR information entering a decoding module. L (L) (1) (q ij ) Represented is information, L, transferred by initializing variable node i to check node j (1) (r ji ) For initializing the information transmitted to the variable node i by the check node j, the specific calculation method is shown in the following formula;
L (1) (r ji )＝0,j＝1,2...m,i＝1,2...n
L (1) (q ij )＝L(P i ),i＝1,2...n,j＝1,2...m
wherein m is the number of rows of the check matrix, and m is more than 0; n is the code length, n is more than 0; l (P) i ) Is the log likelihood ratio value of the channel information of the i-th bit. Because the LDPC code adopted by the embodiment of the invention is Quasi-cyclic LDPC code (QC-LDPC), the matrix structure can adopt a Quasi-cyclic structure, so that the stored address only needs to set the first non-zero position of the cyclic matrix, other non-zero positions can be obtained according to the Quasi-cyclic characteristic of the non-cyclic LDPC code, the other non-zero positions of the check matrix are not required to be stored, and the storage resource can be greatly reduced.
Then, when the check node is updated with the variable node information, the minimum value, the next smallest value, and the exclusive or value of the sign bit are obtained from the absolute values thereof based on all the obtained information, and then the updated likelihood information can be calculated based on the following expression.
Wherein L is (l-1) (q i'j ) Representing the information transmitted from the first-1 circulation variable node i to the check node j, and updating the updated L (l) (r ji ) Information transmitted to a variable node i for the first cycle check node j; rj represents; alpha represents. The updating of check nodes is shown in fig. 6.
Next, variable nodes are updated with check node information as shown in the following equation:
wherein L is (l) (q ij ) Representing the first cycle variable node i to schoolChecking information transmitted by the node j; l (L) (l) (r j'i ) Information representing the transmission of the first cycle check node j to the variable node i; q (Q) i A representation; that is, variable node information is updated to be the sum of the initial LLR information and the check node information related thereto in addition to the information of the current check node. In detail, in the implementation process, the variable node processing unit and the decision output unit are shown in fig. 7.
Then, the cycle number is determined, if the cycle number is not reached, the cycle update of the check node information and the variable node information is continued, and if the iteration number is reached, the updated variable node information L is obtained (l) (q ij ) It should be noted that the variable node information at this time is represented by the following expression, and should be all check node information and initial log likelihood ratio information L (P i ) And (3) summing.
And then hard decision is carried out on the sign bit according to the positive and negative of the sign bit. If L (Q) i ) If > 0 is determined to be 1, if L (Q i ) If less than 0, the signal is judged to be zero, and if demodulation and decoding iteration is needed, L (Q i ) Iterations of demodulation are performed for the channel transfer information.
Based on the GMSK demodulation and LDPC decoding schemes, it can be known that both the GMSK demodulation algorithm and the LDPC decoding algorithm can perform self-circulation, the GMSK demodulation scheme uses log-likelihood information output by itself to continuously input for external iteration, while the LDPC uses continuous updating between the check node and the variable node for internal iteration, and the calculated value output by the LDPC is also likelihood information. Therefore, in order to enable GMSK demodulation to be combined with the LDPC decoding scheme, as shown in fig. 8, the embodiment of the present invention preferably inputs likelihood information calculated in the LDPC decoding process to the GMSK demodulation process again as initial likelihood information of a new external iteration number process in the external iteration process, thereby implementing iteration between demodulation and decoding.
Through the implementation mode and the content, the decoding information for setting the internal iteration cycle times is used for carrying out external iteration cycle judgment output, and the decoding information can be sent to an upper computer of the receiving end equipment 11 through a network port of the receiving end equipment 11 to complete the communication of the whole system.
Based on the same inventive concept as the previous technical solution, referring to fig. 9, a method for performing demodulation decoding by combining GMSK and LDPC by a transmitting end device 11 is shown, where the method includes:
s901: after information data sent by an information source is encoded according to an LDPC encoding algorithm, the encoded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of multiple pilot frequency data and multiple information data;
s902: and carrying out GMSK modulation on the frame data to be transmitted, and transmitting the modulated frame data to be transmitted to a free space, so that the receiving end equipment carries out demodulation and decoding according to the received receiving signals and the demodulation and decoding method of the joint GMSK and the LDPC shown in the figures 2 to 8.
For the technical solution shown in fig. 9, in some examples, the transmitting end device 11 performs LDPC encoding with a quasi-cyclic LDPC code constructed by using PEF algorithm, that is, multiplies an information sequence U of 2160 symbols by a generator matrix G, and has dimensions 2160×2880, to obtain a codeword sequence C of 2880 symbols, i.e., c=ug·.
Then, after framing the coded codeword sequence C and the pilot sequence, frame data with a codeword length of 2976 symbols is obtained. The data is retransmitted for 3 times, and one frame of retransmitted data is changed into the format of fig. 10, namely 96 pieces of pilot data are transmitted three times first, and then information data are transmitted three times:
for the frame structure of time diversity transmission shown in fig. 10. In the implementation process based on FPGA hardware, two RAMs are preferably utilized to perform ping-pong operation, for example, pilot data with the length of 32 x 3 is stored in a No. 1 RAM, information data with the length of 2880 is stored in a No. 2 RAM, the pilot data is firstly read out from the No. 1 RAM (the reading times are three times), and the information data is read out from the Internet access RAM at high speed and written into the No. 2 RAM; then, the information data is read out from the No. 2 RAM (the number of times of reading is three times); the two steps are then performed alternately until no data is to be transmitted.
For GMSK modulation of the coded codeword sequence C, since GMSK modulation is related only to the accumulated phase and the instantaneous phase, andthe state transitions of (a) are finite, so that GMSK modulation can be implemented using a look-up table, i.e. making(understandably, <' > a- >Symmetric to it) table is stored. When modulating, generating address according to current state and next state transition, and reading corresponding data output in the memory table. The BT value of GMSK modulation is set to 0.25, the association length L is equal to 3, and thus the number of states is 16, and there are two transition paths for each state, so there are 32 transition paths in total, that is, 32 state transition data. Further, since the number of sampling points per symbol interval is set to 100 at the time of modulation, the cosine values stored in the ROM are 100×32=3200 data in total. Because of the symmetrical relation between the sine value and the cosine value, only the cosine value is needed to be stored, which reduces half of storage amount and effectively saves hardware resources. In the FPGA implementation, each time a code element is input, the output waveform address can be calculated according to the code element sequence, the current state and the state transition, and then 100 data are continuously output to finish the modulation of the current code element.
In order to embody the technical effects of the technical scheme, the embodiment of the invention is embodied through a specific simulation experiment, and the simulation conditions are as follows: the information frame length is 2160, the LDPC coding efficiency is 3/4, and the quasi-cyclic LDPC code constructed by PEF algorithm is adopted. The code length after coding is 2880, 5000 frames of information are transmitted altogether, the modulation mode adopts GMSK, the sampling point number is 8, and the simulation result is joint solution under different signal to noise ratio conditions The bit error rate performance map of the iteration is tuned as shown in fig. 11. In fig. 11, each curve represents different numbers of outer iterations of LOP-MAP and inner iterations of LDPC, from which it can be seen that after multiple iterations, the technical solution of the embodiment of the present invention can be implemented under a lower signal-to-noise ratio (e.g. b /N 0 =5 dB) to a very low bit error rate (10 -7 ～10 -6 )。
Based on the same inventive concept as the foregoing technical solution, referring to fig. 12, the receiving-end device 12 related to fig. 1 in the embodiment of the present invention may include: a preprocessing section 121, a differential processing section 122, a diversity combining section 123, a synchronizing section 124, and a joint demodulation decoding section 125; wherein,
the preprocessing part 121 is configured to perform low-pass filtering and downsampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
the differential processing section 122 is configured to perform differential processing on the filtered digital signal to obtain a differential digital signal;
The diversity combining section 123 is configured to diversity-combine the digital signals after the difference according to pilot data and information data, respectively;
the synchronization part 124 is configured to perform frame synchronization and bit synchronization on the digital signals after diversity combining to obtain a synchronization position;
the joint demodulation decoding section 125 is configured to perform joint GMSK and LDPC demodulation decoding on the diversity-combined digital signal by means of inner and outer iteration based on the synchronization position, so as to obtain decoded data.
For the above-described scheme, in some examples, the differential processing section 122 is configured to: and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
For the above scheme, in some examples, the diversity combining section 123 is configured to: and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after difference, and respectively obtaining the combined pilot frequency data and the combined information data.
For the above-described scheme, in some examples, the synchronization portion 124 is configured to:
Carrying out matched filtering on the combined pilot frequency data by using waveform data which are obtained by differentiating three sections of pilot frequency data as a matched filter of coefficients;
determining a local peak value in the data after the matched filtering as the maximum value in correlation values appearing in the frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the sampling point number by using the maximum value of the frame synchronization.
For the above scheme, in some examples, the joint demodulation decoding section 125 is configured to:
performing correlation calculation according to the information data in the diversity-combined digital signals and path information of different states to obtain initial log likelihood ratio information from the previous state to the state at the current moment; and entering an external iteration;
in the current external iteration process, updating forward and backward path metric information based on the initial log-likelihood ratio information and a MAX-LOP-MAP algorithm;
acquiring updated log-likelihood ratio information of a current external iterative process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iterative process as initialized log-likelihood ratio information for LDPC decoding;
The information transmitted by the check node to the variable node and the information transmitted by the variable node to the check node are updated alternately by using the initialized log likelihood ratio information loop for LDPC decoding in an internal iteration mode until the set internal iteration times are reached;
when the set internal iteration times are reached, outputting variable node information updated and obtained in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information updated and obtained in the final internal iteration process is used as initial log likelihood ratio information for carrying out the next external iteration process;
and if the current external iteration times are the set external iteration times, outputting variable node information updated and obtained in the final internal iteration process as decoded data obtained by demodulating and decoding the joint GMSK and the LDPC.
Further, referring to fig. 13, the transmitting-end apparatus 11 referred to in fig. 1 described above includes: an encoding section 131, a time diversity combining section 132, a modulating section 133, and a transmitting section 134; wherein,
the encoding part 131 is configured to encode information data sent by the information source according to an LDPC encoding algorithm;
The time diversity combining part 132 is configured to combine the encoded information data and pilot data into frame data to be transmitted in a time diversity structure in a manner of multiple pilot data and multiple information data;
the modulating section 133 is configured to GMSK-modulate the frame data to be transmitted;
the transmitting section 134 is configured to transmit the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation decoding according to the demodulation decoding method of the joint GMSK and LDPC according to claims 1 to 5 based on the received reception signal.
It will be appreciated that in this embodiment, a "part" may be a part of a circuit, a part of a processor, a part of a program or software, etc., and of course may be a unit, or a module may be non-modular.
In addition, each component in the present embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional modules.
The integrated units, if implemented in the form of software functional modules, may be stored in a computer-readable storage medium, if not sold or used as separate products, and based on such understanding, the technical solution of the present embodiment may be embodied essentially or partly in the form of a software product, which is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or processor to perform all or part of the steps of the method described in the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Accordingly, the present embodiment provides a computer storage medium storing a demodulation decoding program of joint GMSK and LDPC, which when executed by at least one processor implements the demodulation decoding method steps of joint GMSK and LDPC shown in fig. 2 or fig. 9.
According to the above-mentioned transmitting end device 11 or receiving end device 12 and computer storage medium, referring to fig. 14, a specific hardware structure of a communication device 140 capable of implementing the above-mentioned transmitting end device 11 or receiving end device 12 is shown, where the communication device 140 may be a wireless device, a mobile or cellular phone (including a so-called smart phone), a Personal Digital Assistant (PDA), a video game console (including a video display, a mobile video game device, a mobile video conference unit), a laptop computer, a desktop computer, a television set-top box, a tablet computing device, an e-book reader, a fixed or mobile media player, etc. The communication device 140 includes: a communication interface 1401, a memory 1402 and a processor 1403; the various components are coupled together by a bus system 1404. It is appreciated that the bus system 1404 is used to enable connected communications between these components. The bus system 1404 includes a power bus, a control bus, and a status signal bus in addition to the data bus. The various buses are labeled as bus system 1404 in fig. 14 for clarity of illustration. Wherein,
The communication interface 1401 is configured to receive and send signals during the process of receiving and sending information with other external network elements;
the memory 1402 for storing a computer program capable of running on the processor 1403;
the processor 1403 is configured to execute the steps of the demodulation decoding method for implementing the joint GMSK and LDPC shown in fig. 2 or fig. 9 when the computer program is executed.
It is to be appreciated that memory 1402 in embodiments of the present invention can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). The memory 1402 of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
While processor 1403 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be accomplished by integrated logic circuitry of hardware in processor 1403 or instructions in the form of software. The processor 1403 described above may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. Which is located in a memory 1402 and a processor 1403 reads information in the memory 1402 and in combination with its hardware performs the steps of the method described above.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP devices, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
It should be understood that the above exemplary solutions of the transmitting end device 11 or the receiving end device 12 and the communication device 140 belong to the same concept as the above solutions of the demodulation and decoding methods of the joint GMSK and the LDPC, and therefore, for details not described in detail in the above solutions of the transmitting end device 11 or the receiving end device 12 and the communication device 140, reference may be made to the description of the above solutions of the demodulation and decoding methods of the joint GMSK and the LDPC. The embodiments of the present application will not be described in detail.
It should be noted that: the technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A demodulation and decoding method for combining gaussian minimum shift keying GMSK and low density parity check LDPC, wherein the method is applied to a receiving end device, and the method comprises:
the baseband digital signal of the received signal is subjected to low-pass filtering and downsampling processing to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
performing differential processing on the filtered digital signals to obtain differential digital signals;
diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
Carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
based on the synchronous position, demodulating and decoding the diversity-combined digital signals by combining GMSK and LDPC in an inner-outer iteration mode to obtain decoded data;
the method for demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an internal and external iteration mode based on the synchronous position to obtain decoded data comprises the following steps:
performing correlation calculation according to the information data in the diversity-combined digital signals and path information of different states to obtain initial log likelihood ratio information from the previous state to the state at the current moment; and entering an external iteration;
in the current external iteration process, updating forward and backward path metric information based on the initial log-likelihood ratio information and a MAX-LOP-MAP algorithm;
acquiring updated log-likelihood ratio information of a current external iterative process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iterative process as initialized log-likelihood ratio information for LDPC decoding;
The information transmitted by the check node to the variable node and the information transmitted by the variable node to the check node are updated alternately by using the initialized log likelihood ratio information loop for LDPC decoding in an internal iteration mode until the set internal iteration times are reached;
when the set internal iteration times are reached, outputting variable node information updated and obtained in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information updated and obtained in the final internal iteration process is used as initial log likelihood ratio information for carrying out the next external iteration process;
and if the current external iteration times are the set external iteration times, outputting variable node information updated and obtained in the final internal iteration process as decoded data obtained by demodulating and decoding the joint GMSK and the LDPC.
2. The method of claim 1, wherein the differentiating the filtered digital signal to obtain a differentiated digital signal comprises:
and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
3. The method of claim 1, wherein diversity combining the differentiated digital signal according to pilot data and information data, respectively, comprises:
and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after difference, and respectively obtaining the combined pilot frequency data and the combined information data.
4. The method of claim 3, wherein said frame synchronizing and bit synchronizing the diversity-combined digital signal to obtain the synchronization position comprises:
carrying out matched filtering on the combined pilot frequency data by using waveform data which are obtained by differentiating three sections of pilot frequency data as a matched filter of coefficients;
determining a local peak value in the data after the matched filtering as the maximum value in correlation values appearing in the frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the sampling point number by using the maximum value of the frame synchronization.
5. A demodulation and decoding method for combining gaussian minimum shift keying GMSK and low density parity check LDPC, wherein the method is applied to a transmitting end device, and the method comprises:
After information data sent by an information source is encoded according to an LDPC encoding algorithm, the encoded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of multiple pilot frequency data and multiple information data;
and carrying out GMSK modulation on the frame data to be transmitted, and transmitting the modulated frame data to be transmitted to a free space, so that the receiving end equipment carries out demodulation and decoding according to a received receiving signal by the demodulation and decoding method of the combined GMSK and LDPC according to claims 1 to 4.
6. A receiver device, the receiver device comprising: the device comprises a preprocessing part, a differential processing part, a diversity combining part, a synchronizing part and a joint demodulation decoding part; wherein,
the preprocessing part is configured to perform low-pass filtering and downsampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is modulated according to GMSK after the transmitting end carries out LDPC coding on the signal to be transmitted, and the modulated signal is transmitted to a free space in a time diversity mode;
the differential processing part is configured to perform differential processing on the filtered digital signals to obtain differential digital signals;
The diversity combining part is configured to diversity combine the digital signals after the difference according to pilot frequency data and information data respectively;
the synchronization part is configured to perform frame synchronization and bit synchronization on the digital signals after diversity combination to obtain synchronization positions;
the joint demodulation decoding part is configured to perform joint GMSK and LDPC demodulation decoding on the diversity-combined digital signals in an inner and outer iteration mode based on the synchronous position to obtain decoded data;
wherein the joint demodulation coding section is configured to:
performing correlation calculation according to the information data in the diversity-combined digital signals and path information of different states to obtain initial log likelihood ratio information from the previous state to the state at the current moment; and entering an external iteration;
in the current external iteration process, updating forward and backward path metric information based on the initial log-likelihood ratio information and a MAX-LOP-MAP algorithm;
acquiring updated log-likelihood ratio information of a current external iterative process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
Taking the updated log-likelihood ratio information of the current external iterative process as initialized log-likelihood ratio information for LDPC decoding;
the information transmitted by the check node to the variable node and the information transmitted by the variable node to the check node are updated alternately by using the initialized log likelihood ratio information loop for LDPC decoding in an internal iteration mode until the set internal iteration times are reached;
when the set internal iteration times are reached, outputting variable node information updated and obtained in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information updated and obtained in the final internal iteration process is used as initial log likelihood ratio information for carrying out the next external iteration process;
and if the current external iteration times are the set external iteration times, outputting variable node information updated and obtained in the final internal iteration process as decoded data obtained by demodulating and decoding the joint GMSK and the LDPC.
7. A transmitting-end device, characterized in that the transmitting-end device comprises: a coding section, a time diversity combining section, a modulating section, and a transmitting section; wherein,
The encoding part is configured to encode information data sent by the information source according to an LDPC encoding algorithm;
the time diversity combining part is configured to combine the coded information data and pilot frequency data into frame data to be transmitted in a time diversity structure in a mode of multiple pilot frequency data and multiple information data;
the modulating part is configured to perform GMSK modulation on the frame data to be sent;
the transmitting section is configured to transmit the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation decoding according to the received reception signal according to the demodulation decoding method of joint GMSK and LDPC according to claims 1 to 4.
8. A communication device comprising a communication interface, a memory, and a processor; the components are coupled together by a bus system; wherein,
the communication interface is used for receiving and transmitting signals in the process of receiving and transmitting information with other external network elements;
the memory is used for storing a computer program capable of running on the processor;
said processor being arranged to perform the demodulation decoding method steps of the joint GMSK and LDPC method of any one of claims 1 to 4 or claim 6 when said computer program is run.
9. A computer storage medium storing a joint GMSK and LDPC demodulation decoding procedure which when executed by at least one processor implements the demodulation decoding method steps of any one of claims 1 to 4 or claim 5.
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