CN117747611B

CN117747611B - Silicon carbide MOSFET cell structure with low leakage current and device

Info

Publication number: CN117747611B
Application number: CN202311748149.3A
Authority: CN
Inventors: 姜利达; 刘昊; 朱洋洋; 洪涛
Original assignee: Wuxi Xindong Semiconductor Technology Co ltd
Current assignee: Wuxi Xindong Semiconductor Technology Co ltd
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-07-02
Anticipated expiration: 2043-12-19
Also published as: CN117747611A

Abstract

The invention discloses a silicon carbide MOSFET cell structure and a device with low leakage current, which change the structure of a traditional JFET by introducing a plane grid or a grid bus and a field oxide layer into the JFET, and enable the first conductivity type semiconductor to be inverted under the action of an electric field when power is applied through the cooperation of the plane grid or the grid bus and the first conductivity type semiconductor under the plane grid or the grid bus, thereby realizing pinch-off, effectively reducing the leakage current during pinch-off, and generating high current density and low on resistance. The invention forms a plurality of cell structures with different layouts by making the plane grid or the grid bus vertical or parallel to the trench grid. According to the invention, the shielding region or the buried region is arranged, so that the gate oxide layer can be effectively protected from the influence of a high electric field. In addition, the invention adjusts the ion concentration of the source contact region and the contact region through the source metal ohmic contact or grounding, changes the technical means of the distance between the two well regions, the two shielding regions and the two buried regions, and the like, and can effectively reduce the leakage current of the device in the off state.

Description

Silicon carbide MOSFET cell structure with low leakage current and device

Technical Field

The invention relates to the field of silicon carbide MOSFETs, in particular to a low-leakage-current silicon carbide MOSFET cell structure and a device.

Background

A problem with silicon carbide MOSFET devices in the prior art is that their channel mobility is very low compared to their bulk mobility. To improve channel mobility, normally-off MOSFETs may be connected in parallel with normally-on JFETs, with the channel being opened by the JFETs to improve channel mobility of the overall device. However, the main problems faced by normally-on JFETs are: the high leakage current in the off state results in the device being in a short circuit state, and thus an additional external power supply is required to turn off all gates before the main power supply is applied, which makes it difficult for the device to be used as a general inverter. It can be seen how to reduce leakage current is a major challenge in the development of silicon carbide MOSFET devices.

Disclosure of Invention

The invention aims to: the invention aims to provide a silicon carbide MOSFET cell structure and a device with low leakage current, which can effectively reduce the leakage current and solve the problems in the prior art.

The technical scheme is as follows: the invention relates to a low leakage current silicon carbide MOSFET cell structure, which is sequentially provided with a drain electrode, a first conduction type medium layer, a first conduction type buffer layer, a first conduction type drift layer and a current diffusion layer from bottom to top, wherein one side of the current diffusion layer is provided with a first trench gate MOSFET, the other side is provided with a second trench gate MOSFET and a third trench gate MOSFET positioned behind the second trench gate MOSFET, a first plane gate JFET is arranged between the first trench gate MOSFET and the second trench gate MOSFET, and a second plane gate JFET is arranged between the first trench gate MOSFET and the third trench gate MOSFET; the first planar gate JFET and the second planar gate JFET are identical in structure and are all normally-on, the second trench gate MOSFET and the third trench gate MOSFET are identical in structure, and the three trench gate MOSFETs are all normally-off;

The first trench gate MOSFET comprises a first trench gate, wherein a first well region is respectively arranged at the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, a first contact region is arranged at the left side of the left first source contact region, a first left source metal is arranged above the left first source contact region and the first contact region, and a first right source metal is arranged above the right first source contact region; the second trench gate MOSFET comprises a second trench gate, wherein a second well region is respectively arranged at the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, a second contact region is arranged at the right side of the right side second source contact region, a second right side source metal is arranged above the right side second source contact region and the second contact region, and a second left side source metal is arranged above the left side second source contact region; the first planar gate JFET comprises a first planar gate, a first conductive type semiconductor is arranged below the first planar gate, and the first conductive type semiconductor is positioned between a first source contact area on the right side and a second source contact area on the left side; the first conductive type semiconductor of the second planar gate JFET is positioned between the first source contact region on the right side and the source contact region on the left side of the third trench gate MOSFET; the first left source metal, the first right source metal, the second left source metal, the second right source metal, the left source metal and the right source metal of the third trench gate MOSFET are all connected with sources, the gates of the first trench gate, the second trench gate, the third trench gate MOSFET, the first plane gate and the gates of the second plane gate JFET are all connected with gates, and the gates of the first plane gate and the second plane gate JFET are all perpendicular to the gates of the three trench gate MOSFETs; the first source contact region, the second source contact region and the source contact region of the third trench gate MOSFET are all of a first conduction type, and the first well region, the first contact region, the second well region, the second contact region, the well region and the contact region of the third trench gate MOSFET are all of a second conduction type.

Further, the first right side source metal ohmic contact is grounded;

And/or

A second left source metal ohmic contact or ground;

And/or

The left side source metal ohmic contact of the third trench gate MOSFET is grounded.

This can further reduce leakage current of the device in the off state.

Further, the ion concentration ranges of the first contact region and the first source contact region on the left side are 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the first source contact region on the right side ranges from 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the second source contact region on the left side ranges from 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration ranges of the second source contact region and the second contact region on the right side are 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the source contact region at the left side of the third trench gate MOSFET is 1 multiplied by 10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the source contact region on the right side of the third trench gate MOSFET and the contact region on the right side thereof is 1×10 ¹⁸～1×10²¹cm^-3.

This can further reduce leakage current of the device in the off state.

Further, the value range of the distance X1 between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is 0.5-1 mu m;

And/or

The distance between the first well region on the right side of the first trench gate and the well region on the left side of the gate of the third trench gate MOSFET is in the range of 0.5-1 mu m.

Therefore, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the first plane gate JFET and/or the second plane gate JFET is better, and the leakage current of the device in the off state is further reduced.

Further, a first shielding region is arranged below the first well region on the right side of the first trench gate;

And/or

A second shielding region is arranged below the second well region at the left side of the second trench gate;

And/or

And a shielding region is arranged below the well region at the left side of the grid electrode of the third trench gate MOSFET.

By arranging the shielding region, the high electric field can be moved from the gate oxide layer of the trench gate to the depletion layer between the shielding region and the current diffusion region, the gate oxide layer is protected from the high electric field, and the device is prevented from being broken down easily.

Further, when a first shielding region is arranged below the first well region on the right side of the first trench gate, and a second shielding region is arranged below the second well region on the left side of the second trench gate, the value range of the distance X2 between the first shielding region and the second shielding region is 0.5-1 mu m;

And when a first shielding region is arranged below the first well region on the right side of the first trench gate, and a shielding region is arranged below the well region on the left side of the gate of the third trench gate MOSFET, the distance between the first shielding region and the shielding region of the third trench gate MOSFET is in the range of 0.5-1 mu m.

Therefore, the distance between the two shielding regions is controlled, so that the pinch-off effect of the depletion layers of the two shielding regions in the off state of the first plane grid JFET and/or the second plane grid JFET is better, and the leakage current of the device in the off state is further reduced.

The low leakage current silicon carbide MOSFET cell structure is sequentially provided with a drain electrode, a first conduction type dielectric layer, a first conduction type buffer layer, a first conduction type drift layer and a current diffusion layer from bottom to top, wherein one side of the current diffusion layer is provided with a first trench gate MOSFET, the other side of the current diffusion layer is provided with a second trench gate MOSFET, and a plane gate JFET is arranged between the first trench gate MOSFET and the second trench gate MOSFET; the planar gate JFET is normally-on, and the two trench gate MOSFETs are both normally-off;

The first trench gate MOSFET comprises a first trench gate, wherein a first well region is respectively arranged at the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, a first contact region is arranged at the left side of the left first source contact region, a first left source metal is arranged above the left first source contact region and the first contact region, and a first right source metal is arranged above the right first source contact region; the second trench gate MOSFET comprises a second trench gate, wherein a second well region is respectively arranged at the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, a second contact region is arranged at the right side of the right side second source contact region, a second right side source metal is arranged above the right side second source contact region and the second contact region, and a second left side source metal is arranged above the left side second source contact region; the planar gate JFET comprises a planar gate, and a first conductive type semiconductor is arranged below the planar gate and is positioned between a first source contact area on the right side and a second source contact area on the left side; the first left source metal, the first right source metal, the second left source metal and the second right source metal are all connected with sources, the first trench gate, the second trench gate and the plane gate are all connected with gates, and the plane gate is parallel to the gates of the two trench gate MOSFETs; the first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type.

Further, the first right side source metal ohmic contact is grounded;

And/or

A second left source metal ohmic contact or ground;

And/or

The ion concentration ranges of the first contact region and the first source contact region on the left side are 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the second source contact region and the second contact region on the right side is 1×10 ¹⁸～1×10²¹cm^-3.

This can further reduce leakage current of the device in the off state.

Further, the distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is in the range of 0.5-1 μm. Thus, the distance between the two well regions is controlled, the pinch-off effect of the depletion layers of the two well regions in the off state of the planar gate JFET is better, and the leakage current of the device in the off state is further reduced.

And/or

And a second shielding region is arranged below the second well region at the left side of the second trench gate.

Further, when a first shielding region is arranged below the first well region on the right side of the first trench gate, and a second shielding region is arranged below the second well region on the left side of the second trench gate, the distance between the first shielding region and the second shielding region is in the range of 0.5-1 μm. Thus, the distance between the two shielding regions is controlled, the pinch-off effect of the depletion layers of the two shielding regions of the planar gate JFET in the off state is better, and the leakage current of the device in the off state is further reduced.

The invention relates to a low leakage current silicon carbide MOSFET cell structure, which is sequentially provided with a drain electrode, a first conduction type medium layer, a first conduction type buffer layer, a first conduction type drift layer and a current diffusion layer from bottom to top, wherein one side of the current diffusion layer is provided with a first trench gate MOSFET, the other side is provided with a second trench gate MOSFET and a third trench gate MOSFET positioned behind the second trench gate MOSFET, a first plane gate JFET is arranged between the first trench gate MOSFET and the second trench gate MOSFET, and a second plane gate JFET is arranged between the first trench gate MOSFET and the third trench gate MOSFET; the first planar gate JFET and the second planar gate JFET are identical in structure and are all normally-on, the second trench gate MOSFET and the third trench gate MOSFET are identical in structure, and the three trench gate MOSFETs are all normally-off;

The first trench gate MOSFET comprises a first trench gate, wherein a first well region is arranged on the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, the first source contact region on the left side is communicated with the first source contact region on the right side, a first contact region is arranged on the left side of the first source contact region on the left side, and first source metal is arranged above the first source contact region on the left side and the first contact region; the second trench gate MOSFET comprises a second trench gate, wherein a second well region is arranged on the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, the second source contact region on the left side is communicated with the second source contact region on the right side, the second contact region is arranged on the right side of the second source contact region on the right side, and second source metal is arranged above the second source contact region on the right side and the second contact region; the first planar gate JFET comprises a first planar gate, a first conductive type semiconductor is arranged below the first planar gate, and the first conductive type semiconductor is positioned between a first source contact area on the right side and a second source contact area on the left side; the first conductive type semiconductor of the second planar gate JFET is positioned between the first source contact region on the right side and the source contact region on the left side of the third trench gate MOSFET; the first source metal, the second source metal, the source metal of the third trench gate MOSFET, the first plane gate and the grid electrode of the second plane gate JFET are all connected with the source, the first trench gate, the second trench gate and the grid electrode of the third trench gate MOSFET are all connected with the grid electrode, and the grid electrodes of the first plane gate MOSFET and the second plane gate JFET are all perpendicular to the grid electrodes of the three trench gate MOSFETs; the first source contact region, the second source contact region and the source contact region of the third trench gate MOSFET are all of a first conduction type, and the first well region, the first contact region, the second well region, the second contact region, the well region and the contact region of the third trench gate MOSFET are all of a second conduction type.

Further, the ion concentration ranges of the first source contact region and the first contact region on the left side are 1×10 ¹⁸～1×10²¹cm^-3;

And/or

This can further reduce leakage current of the device in the off state.

Further, the value range of the distance X3 between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is 0.5-1 mu m;

And/or

Therefore, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions is better when the first planar gate JFET and/or the second planar gate JFET are in the off state, and the leakage current of the device in the off state is further reduced.

Further, a first buried region is arranged below the first trench gate;

And/or

A second buried region is arranged below the second trench gate;

And/or

A buried region is arranged below the grid electrode of the third trench gate MOSFET.

By providing the buried region, the drain voltage at high drain-source bias can be limited, the JFET region can be shielded, and the gate oxide layer of the trench gate can be protected from a high electric field at high drain voltage.

Further, when a first buried region is arranged below the first trench gate and a second buried region is arranged below the second trench gate, the distance X4 between the first buried region and the second buried region is 0.5-1 μm;

When the first buried region is arranged below the first trench gate, and the buried region is arranged below the gate of the third trench gate MOSFET, the distance between the first buried region and the buried region of the third trench gate MOSFET is in the range of 0.5-1 mu m.

Therefore, the distance between the two buried regions is controlled, so that the pinch-off effect of the depletion layers of the two buried regions in the cut-off state of the first planar gate JFET and/or the second planar gate JFET is better, and the leakage current of the device in the cut-off state is further reduced.

The first trench gate MOSFET comprises a first trench gate, wherein a first well region is arranged on the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, the first source contact region on the left side is communicated with the first source contact region on the right side, a first contact region is arranged on the left side of the first source contact region on the left side, and first source metal is arranged above the first source contact region on the left side and the first contact region; the second trench gate MOSFET comprises a second trench gate, wherein a second well region is arranged on the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, the second source contact region on the left side is communicated with the second source contact region on the right side, the second contact region is arranged on the right side of the second source contact region on the right side, and second source metal is arranged above the second source contact region on the right side and the second contact region; the planar gate JFET comprises a planar gate, and a first conductive type semiconductor is arranged below the planar gate and is positioned between a first source contact area on the right side and a second source contact area on the left side; the first source metal, the second source metal and the plane grid are connected with the source, the first trench grid and the second trench grid are connected with the grid, and the plane grid is parallel to the grids of the two trench grid MOSFETs; the first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type.

And/or

This can further reduce leakage current of the device in the off state.

Further, the distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is in the range of 0.5-1 μm.

Thus, the distance between the two well regions is controlled, the pinch-off effect of the depletion layers of the two well regions in the off state of the planar gate JFET is better, and the leakage current of the device in the off state is further reduced.

Further, a first buried region is arranged below the first trench gate;

And/or

A second buried region is arranged below the second trench gate.

Further, when a first buried region is arranged below the first trench gate and a second buried region is arranged below the second trench gate, the distance between the first buried region and the second buried region is in the range of 0.5-1 μm.

Thus, the distance between the two buried regions is controlled, the pinch-off effect of the depletion layers of the two buried regions in the off state of the planar gate JFET is better, and the leakage current of the device in the off state is further reduced.

The low leakage current silicon carbide MOSFET cell structure is sequentially provided with a drain electrode, a first conduction type dielectric layer, a first conduction type buffer layer, a first conduction type drift layer and a current diffusion layer from bottom to top, wherein one side of the current diffusion layer is provided with a first trench gate MOSFET, the other side of the current diffusion layer is provided with a second trench gate MOSFET, and a grid bus type JFET is arranged between the first trench gate MOSFET and the second trench gate MOSFET; the grid bus type JFET is normally-on type, and the two trench gate MOSFETs are both normally-off type;

The first trench gate MOSFET comprises a first trench gate, wherein a first well region is respectively arranged at the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, a first contact region is arranged at the left side of the left first source contact region, a first left source metal is arranged above the left first source contact region and the first contact region, and a first right source metal is arranged above the right first source contact region; the second trench gate MOSFET comprises a second trench gate, wherein a second well region is respectively arranged at the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, a second contact region is arranged at the right side of the right side second source contact region, a second right side source metal is arranged above the right side second source contact region and the second contact region, and a second left side source metal is arranged above the left side second source contact region; the grid bus type JFET comprises a first conductive type semiconductor positioned between a first source contact area on the right side and a second source contact area on the left side, a field oxide layer is arranged above the first conductive type semiconductor, and a grid bus is arranged inside the field oxide layer; the first left source metal, the first right source metal, the second left source metal and the second right source metal are all connected with sources, the first trench gate, the second trench gate and the gate bus are all connected with gates, and the gate bus is parallel to the gates of the two trench gate MOSFETs; the first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type.

Further, the first right side source metal ohmic contact is grounded;

And/or

A second left source metal ohmic contact or ground;

And/or

This can further reduce leakage current of the device in the off state.

Further, the distance X5 between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is in the range of 0.5-1 μm.

Therefore, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the grid bus type JFET is better, and the leakage current of the device in the off state is further reduced.

And/or

Further, when a first shielding region is arranged below the first well region on the right side of the first trench gate, and a second shielding region is arranged below the second well region on the left side of the second trench gate, the value range of the distance X6 between the first shielding region and the second shielding region is 0.5-1 μm. Therefore, the distance between the two shielding areas is controlled, so that the pinch-off effect of the depletion layers of the two shielding areas of the grid bus type JFET in the off state is better, and the leakage current of the device in the off state is further reduced.

The low-leakage-current silicon carbide MOSFET device comprises any one of the low-leakage-current silicon carbide MOSFET cell structures.

The beneficial effects are that: compared with the prior art, the invention has the following beneficial effects:

1. According to the invention, the planar grid is introduced into the JFET, so that the structure of the traditional JFET is changed, and the planar grid is matched with the first conductive type semiconductor below the planar grid, so that the first conductive type semiconductor is inverted under the action of an electric field when the power is applied, pinch-off is realized, leakage current during pinch-off can be effectively reduced, and high current density and low on-resistance can be generated;

2. According to the invention, the structure of the traditional JFET is changed by introducing the grid bus and the field oxide layer into the JFET, and the grid bus is matched with the first conductive type semiconductor below the grid bus, so that the first conductive type semiconductor is inverted under the action of an electric field when the power is applied, pinch-off is realized, leakage current during pinch-off can be effectively reduced, and high current density and low on-resistance can be generated;

3. according to the invention, the planar grid or the grid bus is perpendicular to or parallel to the trench grid, so that a plurality of cell structures with different layouts are formed, the space is fully utilized, and a plurality of actual requirements can be met;

4. According to the invention, the shielding area or the buried area is arranged, so that the gate oxide layer can be effectively protected from the influence of a high electric field;

5. According to the invention, the source metal ohmic contact or grounding is adopted, the ion concentration of the source contact region and the contact region is regulated, the technical means of changing the distances among the two well regions, the two shielding regions and the two buried regions are changed, and the leakage current of the device in the off state can be effectively reduced.

Drawings

FIG. 1 is a schematic diagram of a cell according to example 1 of the present invention;

FIG. 2 is a layout of a cell of example 1 in an embodiment of the present invention;

FIG. 3 is a layout of a cell according to example 2 of the present invention;

FIG. 4 is a schematic diagram of a cell structure according to example 3 of the present invention;

FIG. 5 is a layout of a cell of example 3 in an embodiment of the present invention;

FIG. 6 is a layout of a cell of example 4 in an embodiment of the present invention;

FIG. 7 is a schematic diagram of a cell structure according to example 5 of the present invention;

fig. 8 is a layout of a cell of example 5 in an embodiment of the present invention.

Detailed Description

The present embodiment discloses a low leakage current silicon carbide MOSFET cell structure, which has the following five examples.

Example 1:

Embodiment 1 discloses a silicon carbide MOSFET cell structure with low leakage current, which is shown in fig. 1, and sequentially comprises a drain electrode 111, a first conductivity type dielectric layer 121, a first conductivity type buffer layer 122, a first conductivity type drift layer 123, and a current diffusion layer 124 from bottom to top. As can be seen from fig. 2, one side of the current diffusion layer 124 is provided with a first trench gate MOSFET193, the other side is provided with a second trench gate MOSFET194 and a third trench gate MOSFET195 positioned behind the second trench gate MOSFET, a first planar gate JFET191 is provided between the first trench gate MOSFET193 and the second trench gate MOSFET194, and a second planar gate JFET192 is provided between the first trench gate MOSFET193 and the third trench gate MOSFET 195. The first and second planar gate JFETs 191 and 192 are identical in structure and all normally-on, the second and third trench gate MOSFETs 194 and 195 are identical in structure and all three trench gate MOSFETs are all normally-off.

As shown in fig. 1, the first trench-gate MOSFET193 includes a first trench gate 13, a first well region 141 is disposed on each of the left and right sides of the first trench gate 13, a first source contact region 142 is disposed above each of the first well regions 141, a first contact region 143 is disposed on the left side of the first source contact region 142, a first left source metal 145 is disposed above the first source contact region 142 and the first contact region 143, and a first right source metal 146 is disposed above the first source contact region 142. The first trench gate 13 includes a trench 131 formed on the current diffusion layer 124, a gate polysilicon 132 is disposed in the trench 131, and a gate oxide layer 133 is disposed between the trench 131 and the gate polysilicon 132. The first right source metal 146 may be ohmic-contacted or grounded, the ion concentration ranges of the first contact region 143 and the left first source contact region 142 may be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration range of the right first source contact region 142 may also be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3 to further reduce leakage current. Wherein the ion concentration of the first contact region 143 and the first source contact region 142 on the left side is adjusted to adjust the magnitude of the contact resistance Rc1, and the ion concentration of the first source contact region 142 on the right side is adjusted to adjust the magnitude of the resistance of the first conductivity type semiconductor 18. A first shielding region 144 may be disposed under the first well region 141 on the right side of the first trench gate 13 to protect the gate oxide layer 133 from the high electric field.

As shown in fig. 1, the second trench-gate MOSFET194 includes a second trench gate 15, a second well region 161 is disposed on each of the left and right sides of the second trench gate 15, a second source contact region 162 is disposed above each of the second well regions 161, a second contact region 163 is disposed on the right side of the right second source contact region 162, a second right source metal 166 is disposed above the right second source contact region 162 and the second contact region 163, and a second left source metal 165 is disposed above the left second source contact region 162. The second trench gate 15 has the same structure as the first trench gate 13. The second left source metal 165 may be ohmic-contacted or grounded, the ion concentration range of the left second source contact region 162 may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration ranges of the right second source contact region 162 and the second contact region 163 may also be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. Wherein the ion concentrations of the second source contact region 162 and the second contact region 163 on the right side are adjusted to adjust the magnitude of the contact resistance Rc2, and the ion concentration of the second source contact region 162 on the left side is adjusted to adjust the magnitude of the resistance of the first conductivity type semiconductor 18. A second shielding region 164 may be disposed under the second well region 161 at the left side of the second trench gate 15 to protect the gate oxide layer of the second trench gate 15 from the high electric field.

The third trench gate MOSFET195 has the same structure as the second trench gate MOSFET194, and will not be described again. Similarly, as shown in fig. 2, the left source metal 1951 of the third trench-gate MOSFET195 may be ohmic-contacted or grounded, the ion concentration range of the left source contact region may be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration range of the right source contact region and the right contact region thereof may be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, so as to further reduce the leakage current. A shield region may also be provided under the well region to the left of the gate of the third trench-gate MOSFET195 to protect the gate oxide layer from high electric fields.

As shown in fig. 1, the first planar gate JFET191 includes a first planar gate 17, and a first conductivity-type semiconductor 18 is disposed under the first planar gate 17, the first conductivity-type semiconductor 18 being located between the first source contact region 142 on the right side and the second source contact region 162 on the left side. The first planar gate 17 includes a gate oxide layer 172 provided over the first conductive type semiconductor 18, and a gate polysilicon 171 located inside the gate oxide layer 172. The first conductive type semiconductor 18 is in a strip shape, the lower end of the first conductive type semiconductor 18 is provided with a protrusion, the protrusion and the strip body form two right-angle bends, the first well region 141 on the right side of the first trench gate 13 is contacted with the first conductive type semiconductor 18 at the right-angle bend on the left side, the second well region 161 on the left side of the second trench gate 15 is contacted with the first conductive type semiconductor 18 at the right-angle bend on the right side, and the current diffusion layer 124 between the first well region 141 on the right side and the second well region 161 on the left side is opposite under the protrusion.

The second planar gate JFET192 has the same structure as the first planar gate JFET 191. The first conductive type semiconductor of the second planar gate JFET192 is located between the first source contact region 142 on the right side and the source contact region on the left side of the third trench gate MOSFET 195. The first conductive type semiconductor is also in a strip shape, the lower end of the first conductive type semiconductor is provided with a bulge, the bulge and the strip body form two right-angle bends, the first well region 141 on the right side of the first trench gate 13 is contacted with the first conductive type semiconductor at the right-angle bend on the left side, the well region on the left side of the third trench gate MOSFET195 is contacted with the first conductive type semiconductor at the right-angle bend on the right side, and thus the current diffusion layer 124 between the first well region 141 on the right side and the well region on the left side of the third trench gate MOSFET195 is opposite under the bulge.

The first left source metal 145, the first right source metal 146, the second left source metal 165, the second right source metal 166, the left source metal 1951 and the right source metal 1952 of the third trench gate MOSFET195 are all connected to the source 112, the first trench gate 13, the second trench gate 15, the gate of the third trench gate MOSFET195, the gate of the first planar gate 17 and the gate of the second planar gate JFET192 are all connected to the gate 113, and the gates of the first planar gate 17 and the second planar gate JFET192 are all perpendicular to the gates of the three trench gate MOSFETs. The source contact regions of the first source contact region 142, the second source contact region 162 and the third trench gate MOSFET195 are all of the first conductivity type, and the well regions and the contact regions of the first well region 141, the first contact region 143, the second well region 161, the second contact region 163 and the third trench gate MOSFET195 are all of the second conductivity type. The first conductivity type may be N-type or P-type, and the second conductivity type may be P-type or N-type.

As shown in fig. 1, the distance X1 between the first well 141 on the right side of the first trench gate 13 and the second well 161 on the left side of the second trench gate 15 may be adjusted to be 0.5-1 μm, and the distance between the first well 141 on the right side of the first trench gate 13 and the well on the left side of the gate of the third trench gate MOSFET195 may be also adjusted to be 0.5-1 μm. Thus, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the first planar gate JFET191 and/or the second planar gate JFET192 is better, and the leakage current of the device in the off state is further reduced.

As shown in fig. 1, the distance X2 between the first shielding region 144 and the second shielding region 164 may be adjusted to a value ranging from 0.5 μm to 1 μm, and the distance between the first shielding region 144 and the shielding region of the third trench gate MOSFET195 may be also adjusted to a value ranging from 0.5 μm to 1 μm. Thus, the distance between the two shielding regions is controlled, so that the pinch-off effect of the depletion layers of the two shielding regions in the off state of the first planar gate JFET191 and/or the second planar gate JFET192 is better, and the leakage current of the device in the off state is further reduced.

Example 2:

Embodiment 2 discloses a silicon carbide MOSFET cell structure with low leakage current, as shown in FIG. 3, a drain electrode, a first conductive type dielectric layer, a first conductive type buffer layer, a first conductive type drift layer and a current diffusion layer are sequentially arranged from bottom to top, one side of the current diffusion layer is provided with a first trench gate MOSFET21, the other side is provided with a second trench gate MOSFET22, and a plane gate JFET23 is arranged between the first trench gate MOSFET21 and the second trench gate MOSFET 22; the planar gate JFET23 is normally-on and both trench gate MOSFETs are normally-off.

The first trench-gate MOSFET21 includes a first trench gate, each of the left and right sides of the first trench gate has a first well region, each of the first well regions has a first source contact region above, the left side of the first source contact region on the left side has a first contact region, the first source contact region on the left side and the upper side of the first contact region have a first left source metal 211, and the upper side of the first source contact region on the right side has a first right source metal 212. The first trench gate comprises a trench formed on the current diffusion layer, gate polysilicon is arranged in the trench, and a gate oxide layer is arranged between the trench and the gate polysilicon. The first right side source metal 212 may be ohmic-contacted or grounded, and the ion concentration ranges of the first contact region and the left side first source contact region may be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration range of the right side first source contact region may also be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3 to further reduce leakage current. A first shielding region may be disposed under the first well region on the right side of the first trench gate to protect the gate oxide layer from the high electric field.

The second trench-gate MOSFET22 includes a second trench gate, each of the left and right sides of the second trench gate has a second well region, each of the second well regions has a second source contact region above, the right side of the second source contact region on the right side has a second contact region, the second source contact region on the right side and the second contact region above have a second right source metal 222, and the second source contact region on the left side has a second left source metal 221 above. The second trench gate has the same structure as the first trench gate. The second left source metal 221 may be ohmic-contacted or grounded, and the ion concentration range of the left second source contact region may be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration ranges of the right second source contact region and the second contact region may also be adjusted to be 1×10 ¹⁸～1×10²¹cm^-3, to further reduce the leakage current. A second shielding region may be disposed under the second well region at the left side of the second trench gate to protect the gate oxide layer of the second trench gate from the high electric field.

The planar gate JFET23 includes a planar gate below which a first conductivity type semiconductor is disposed between a first source contact region on the right side and a second source contact region on the left side. The planar gate includes a gate oxide layer over the first conductivity type semiconductor and gate polysilicon within the gate oxide layer. The first conductive type semiconductor is in a strip shape, the lower end of the first conductive type semiconductor is provided with a bulge, the bulge and the strip-shaped body form two right-angle bends, a first well region on the right side of the first trench gate is in contact with the first conductive type semiconductor at the right-angle bend position on the left side, a second well region on the left side of the second trench gate is in contact with the first conductive type semiconductor at the right-angle bend position on the right side, and therefore a current diffusion layer between the first well region on the right side and the second well region on the left side is opposite to the lower part of the bulge.

The first left source metal 211, the first right source metal 212, the second left source metal 221 and the second right source metal 222 are all connected to the sources, the first trench gate, the second trench gate and the planar gate are all connected to the gates, and the planar gate is parallel to the gates of the two trench gate MOSFETs. The first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type. The first conductivity type may be N-type or P-type, and the second conductivity type may be P-type or N-type.

The distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate can be adjusted to be 0.5-1 μm. Thus, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the planar gate JFET23 is better, and the leakage current of the device in the off state is further reduced.

The distance between the first shielding region and the second shielding region can be regulated to be 0.5-1 μm. Thus, the distance between the two shielding regions is controlled, so that the pinch-off effect of the depletion layers of the two shielding regions in the off state of the planar gate JFET23 is better, and the leakage current of the device in the off state is further reduced.

Example 3:

Embodiment 3 discloses a silicon carbide MOSFET cell structure with low leakage current, as shown in fig. 4, a drain 311, a first conductive type dielectric layer 321, a first conductive type buffer layer 322, a first conductive type drift layer 323 and a current diffusion layer 324 are sequentially disposed from bottom to top, and as can be seen from fig. 5, a first trench gate MOSFET393 is disposed on one side of the current diffusion layer 324, a second trench gate MOSFET394 and a third trench gate MOSFET395 disposed behind the first trench gate MOSFET393 and the second trench gate MOSFET394, a first planar gate JFET391 is disposed between the first trench gate MOSFET393 and the third trench gate MOSFET395, and a second planar gate JFET392 is disposed between the first trench gate MOSFET393 and the third trench gate MOSFET 395. The first and second planar gate JFETs 391 and 392 are identical in structure and all normally-on, the second and third trench gate MOSFETs 394 and 395 are identical in structure and all three trench gate MOSFETs are all normally-off.

As shown in fig. 4, the first trench-gate MOSFET393 includes a first trench gate 33, a first well region 341 is disposed on each of the left and right sides of the first trench gate 33, a first source contact region 342 is disposed above each of the first well regions 341, the first source contact region 342 on the left side is in communication with the first source contact region 342 on the right side, a first contact region 343 is disposed on the left side of the first source contact region 342 on the left side, and a first source metal 345 is disposed above the first source contact region 342 and the first contact region 343 on the left side. The first trench gate 33 includes a trench 331 formed on the current diffusion layer 324, a gate polysilicon 332 is disposed in the trench 331, and a gate oxide layer 333 is disposed between the trench 331 and the gate polysilicon 332. The ion concentration ranges of the first source contact region 342 and the first contact region 343 on the left side may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. A first buried region 344 may be disposed under the first trench gate 33 to protect the gate oxide layer 333 from a high electric field.

As shown in fig. 4, the second trench-gate MOSFET394 includes the second trench gate 35, a second well region 361 is disposed on each of the left and right sides of the second trench gate 35, a second source contact region 362 is disposed above each of the second well regions 361, the second source contact region 362 on the left side is in communication with the second source contact region 362 on the right side, a second contact region 363 is disposed on the right side of the second source contact region 362, and a second source metal 355 is disposed above the second source contact region 362 and the second contact region 363 on the right side. The second trench gate 35 has the same structure as the first trench gate 33. The ion concentration ranges of the second source contact region 362 and the second contact region 363 on the right side may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. A second buried region 364 may be disposed under the second trench gate 35 to protect the gate oxide layer of the second trench gate 35 from a high electric field.

The third trench gate MOSFET395 has the same structure as the second trench gate MOSFET394 and will not be described again. Similarly, as shown in fig. 5, the ion concentration range of the source contact region on the right side of the third trench gate MOSFET395 and the contact region on the right side thereof can be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. A buried region may also be provided under the gate of the third trench-gate MOSFET395 to protect the gate oxide layer from high electric fields.

As shown in fig. 4, the first planar gate JFET391 includes a first planar gate 37 with a first conductivity type semiconductor 38 disposed below the first planar gate 37, the first conductivity type semiconductor 38 being located between a first source contact region 342 on the right and a second source contact region 362 on the left. The first planar gate 37 includes a gate oxide layer 372 provided over the first conductivity type semiconductor 38, and a gate polysilicon 371 located inside the gate oxide layer 372. The first conductive type semiconductor 38 is in a strip shape, the lower end of the first conductive type semiconductor 38 is provided with a protrusion, the protrusion and the strip body form two right-angle bends, the first well region 341 on the right side of the first trench gate 33 is contacted with the first conductive type semiconductor 38 at the right-angle bend on the left side, the second well region 361 on the left side of the second trench gate 35 is contacted with the first conductive type semiconductor 38 at the right-angle bend on the right side, and the current diffusion layer 324 between the first well region 341 on the right side and the second well region 361 on the left side is opposite under the protrusion.

The second planar gate JFET392 is identical in structure to the first planar gate JFET 391. The first conductivity type semiconductor of the second planar gate JFET392 is located between the first source contact region 342 on the right and the source contact region on the left of the third trench gate MOSFET 395. The first conductive type semiconductor is also in a strip shape, the lower end of the first conductive type semiconductor is provided with a bulge, the bulge and the strip body form two right-angle bends, the first well region 341 on the right side of the first trench gate 33 is contacted with the first conductive type semiconductor at the right-angle bend on the left side, the well region on the left side of the third trench gate MOSFET395 is contacted with the first conductive type semiconductor at the right-angle bend on the right side, and thus the current diffusion layer 324 between the first well region 341 on the right side and the well region on the left side of the third trench gate MOSFET395 is opposite under the bulge.

The source metal 3951 of the first source metal 345, the second source metal 355, the third trench gate MOSFET395, the first planar gate 37 and the gate of the second planar gate JFET392 are all connected to the source 312, the gates of the first trench gate 33, the second trench gate 35 and the third trench gate MOSFET395 are all connected to the gate 313, and the gates of the first planar gate 37 and the second planar gate JFET392 are all perpendicular to the gates of the three trench gate MOSFETs. The source contact regions of the first source contact region 342, the second source contact region 362 and the third trench gate MOSFET395 are all of the first conductivity type, and the well regions and the contact regions of the first well region 341, the first contact region 343, the second well region 361, the second contact region 363, the third trench gate MOSFET395 are all of the second conductivity type. The first conductivity type may be N-type or P-type, and the second conductivity type may be P-type or N-type.

As shown in fig. 4, the distance X3 between the first well region 341 on the right side of the first trench gate 33 and the second well region 361 on the left side of the second trench gate 35 may be adjusted to be 0.5-1 μm, and the distance between the first well region 341 on the right side of the first trench gate 33 and the well region on the left side of the gate of the third trench gate MOSFET395 may be also adjusted to be 0.5-1 μm. Thus, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the first planar gate JFET391 and/or the second planar gate JFET392 is better, and the leakage current of the device in the off state is further reduced.

As shown in fig. 4, the range of the distance X4 between the first buried region 344 and the second buried region 364 may be adjusted to 0.5-1 μm, and the range of the distance between the first buried region 344 and the buried region of the third trench gate MOSFET395 may be also adjusted to 0.5-1 μm. Thus, the distance between the two buried regions is controlled, so that the pinch-off effect of the depletion layers of the two buried regions in the off state of the first planar gate JFET391 and/or the second planar gate JFET392 is better, and the leakage current of the device in the off state is further reduced.

Example 4:

Embodiment 4 discloses a silicon carbide MOSFET cell structure with low leakage current, as shown in fig. 6, a drain electrode, a first conductivity type dielectric layer, a first conductivity type buffer layer, a first conductivity type drift layer, and a current diffusion layer are sequentially disposed from bottom to top, wherein one side of the current diffusion layer is provided with a first trench gate MOSFET41, the other side is provided with a second trench gate MOSFET42, and a planar gate JFET43 is disposed between the first trench gate MOSFET41 and the second trench gate MOSFET 42. The planar gate JFET43 is normally-on and both trench gate MOSFETs are normally-off.

The first trench-gate MOSFET41 includes a first trench gate, each of the left and right sides of the first trench gate has a first well region, each of the first well regions has a first source contact region above, the first source contact region on the left side is in communication with the first source contact region on the right side, the first contact region is disposed on the left side of the first source contact region on the left side, and the first source metal 411 is disposed above the first source contact region and the first contact region on the left side. The first trench gate comprises a trench formed on the current diffusion layer, gate polysilicon is arranged in the trench, and a gate oxide layer is arranged between the trench and the gate polysilicon. The ion concentration range of the first source contact region and the first contact region on the left side can be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. A first buried region may be disposed under the first trench gate to protect the gate oxide layer from a high electric field.

The second trench-gate MOSFET42 includes a second trench gate, each of the left and right sides of the second trench gate has a second well region, each of the second well regions has a second source contact region above, the second source contact region on the left side is in communication with the second source contact region on the right side, the second contact region is disposed on the right side of the second source contact region on the right side, and the second source metal 421 is disposed above the second source contact region and the second contact region on the right side. The second trench gate has the same structure as the first trench gate. The ion concentration range of the second source contact region and the second contact region on the right side can be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. A second buried region may be disposed under the second trench gate to protect the gate oxide layer from the high electric field.

The planar gate JFET43 includes a planar gate below which a first conductivity type semiconductor is disposed between a first source contact region on the right side and a second source contact region on the left side. The planar gate includes a gate oxide layer over the first conductivity type semiconductor and gate polysilicon within the gate oxide layer. The first conductive type semiconductor is in a strip shape, the lower end of the first conductive type semiconductor is provided with a bulge, the bulge and the strip-shaped body form two right-angle bends, a first well region on the right side of the first trench gate is in contact with the first conductive type semiconductor at the right-angle bend position on the left side, a second well region on the left side of the second trench gate is in contact with the first conductive type semiconductor at the right-angle bend position on the right side, and therefore a current diffusion layer between the first well region on the right side and the second well region on the left side is opposite to the lower part of the bulge.

The first source metal 411, the second source metal 421 and the planar gate are all connected to the source, the first trench gate and the second trench gate are all connected to the gate, and the planar gate is parallel to the gates of the two trench gate MOSFETs. The first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type. The first conductivity type may be N-type or P-type, and the second conductivity type may be P-type or N-type.

The distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate can be adjusted to be 0.5-1 μm. Thus, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the planar gate JFET43 is better, and the leakage current of the device in the off state is further reduced.

The range of the distance between the first buried region and the second buried region may be adjusted to 0.5-1 μm. Thus, the distance between the two buried regions is controlled, so that the pinch-off effect of the depletion layers of the two buried regions in the off state of the planar gate JFET43 is better, and the leakage current of the device in the off state is further reduced.

Example 5:

Embodiment 5 discloses a low leakage current silicon carbide MOSFET cell structure, which is provided with a drain electrode 511, a first conductivity type dielectric layer 521, a first conductivity type buffer layer 522, a first conductivity type drift layer 523 and a current diffusion layer 524 from bottom to top as shown in fig. 7. Referring to fig. 8, a first trench gate MOSFET591 is provided on one side of the current diffusion layer 524, a second trench gate MOSFET592 is provided on the other side, and a gate bus JFET593 is provided between the first trench gate MOSFET591 and the second trench gate MOSFET 592. The gate bus JFET593 is normally on and both trench gate MOSFETs are normally off.

As shown in fig. 7, the first trench-gate MOSFET591 includes a first trench gate 53, a first well region 541 is disposed on each of the left and right sides of the first trench gate 53, a first source contact region 542 is disposed above each of the first well regions 541, a first contact region 543 is disposed on the left side of the first source contact region 542, a first left source metal 545 is disposed above the first source contact region 542 and the first contact region 543, and a first right source metal 546 is disposed above the first source contact region 542. The first trench gate 53 includes a trench 531 formed on the current diffusion layer 524, a gate polysilicon 532 is disposed in the trench 531, and a gate oxide layer 533 is disposed between the trench 531 and the gate polysilicon 532. The first right source metal 546 may be ohmic-contacted or grounded, the ion concentration range of the first contact region 543 and the left first source contact region 542 may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration range of the right first source contact region 542 may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. Wherein the ion concentration of the first contact region 543 and the first source contact region 542 on the left side is adjusted to adjust the magnitude of the contact resistance Rc3, and the ion concentration of the first source contact region 542 on the right side is adjusted to adjust the magnitude of the resistance of the first conductivity type semiconductor 58. A first shield region 544 may be disposed under the first well region 541 on the right side of the first trench gate 53 to protect the gate oxide layer 533 from the high electric field.

As shown in fig. 7, the second trench-gate MOSFET592 includes a second trench gate 55, a second well region 561 is disposed on each of the left and right sides of the second trench gate 55, a second source contact region 562 is disposed above each of the second well regions 561, a second contact region 563 is disposed on the right side of the right second source contact region 562, a second right source metal 566 is disposed above the right second source contact region 562 and the second contact region 563, and a second left source metal 565 is disposed above the left second source contact region 562. The second trench gate 55 has the same structure as the first trench gate 53. The second left source metal 565 may be ohmic-contacted or grounded, the ion concentration range of the left second source contact region 562 may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3, and the ion concentration ranges of the right second source contact region 562 and the second contact region 563 may be adjusted to 1×10 ¹⁸～1×10²¹cm^-3 to further reduce the leakage current. Wherein the ion concentrations of the second source contact region 562 and the second contact region 563 on the right side are adjusted to adjust the magnitude of the contact resistance Rc4, and the ion concentration of the second source contact region 562 on the left side is adjusted to adjust the magnitude of the resistance of the first conductivity type semiconductor 58. A second shielding region 564 may be disposed under the second well region 561 at the left side of the second trench gate 55 to protect the gate oxide layer of the second trench gate 55 from the high electric field.

As shown in fig. 7, the gate bus JFET593 includes a first conductivity type semiconductor 58 located between a first source contact region 542 on the right side and a second source contact region 562 on the left side, a field oxide layer 572 is provided over the first conductivity type semiconductor 58, and a gate bus 571 is provided inside the field oxide layer 572. The first conductive type semiconductor 58 is in a strip shape, the lower end of the first conductive type semiconductor 58 is provided with a protrusion, the protrusion and the strip body form two right-angle bends, the first well region 541 on the right side of the first trench gate 53 is contacted with the first conductive type semiconductor 58 at the right-angle bend on the left side, the second well region 561 on the left side of the second trench gate 55 is contacted with the first conductive type semiconductor 58 at the right-angle bend on the right side, and the current diffusion layer 524 between the first well region 541 on the right side and the second well region 561 on the left side is opposite under the protrusion.

The first left source metal 545, the first right source metal 546, the second left source metal 565 and the second right source metal 566 are all connected to the source 512, the first trench gate 53, the second trench gate 55 and the gate bus bar 571 are all connected to the gate 513, and the gate bus bar 571 is parallel to the gates of the two trench gate MOSFETs. Wherein, the first source contact region 542 and the second source contact region 562 are of the first conductivity type, and the first well region 541, the first contact region 543, the second well region 561 and the second contact region 563 are of the second conductivity type. The first conductivity type may be N-type or P-type, and the second conductivity type may be P-type or N-type.

The distance X5 between the first well 541 on the right side of the first trench gate 53 and the second well 561 on the left side of the second trench gate 55 can be adjusted to a value in the range of 0.5-1 μm. Thus, the distance between the two well regions is controlled, so that the pinch-off effect of the depletion layers of the two well regions in the off state of the grid bus type JFET593 is better, and the leakage current of the device in the off state is further reduced.

The range of values for the distance X6 between the first shield region 544 and the second shield region 564 may be adjusted to 0.5-1 μm. Thus, the distance between the two shielding regions is controlled, so that the pinch-off effect of the depletion layers of the two shielding regions in the off state of the grid bus type JFET593 is better, and the leakage current of the device in the off state is further reduced.

The embodiment also discloses a silicon carbide MOSFET device with low leakage current, and any one of the cell structures can be adopted.

The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present invention should be included in the scope of the present invention.

Claims

1. A low leakage current silicon carbide MOSFET cell structure is characterized in that: a drain electrode (111), a first conductive type medium layer (121), a first conductive type buffer layer (122), a first conductive type drift layer (123) and a current diffusion layer (124) are sequentially arranged from bottom to top, a first trench gate MOSFET (193) is arranged on one side of the current diffusion layer (124), a second trench gate MOSFET (194) and a third trench gate MOSFET (195) positioned behind the second trench gate MOSFET are arranged on the other side of the current diffusion layer, a first plane gate JFET (191) is arranged between the first trench gate MOSFET (193) and the second trench gate MOSFET (194), and a second plane gate JFET (192) is arranged between the first trench gate MOSFET (193) and the third trench gate MOSFET (195); the first plane grid JFET (191) and the second plane grid JFET (192) have the same structure and are all normally-on, the second trench grid MOSFET (194) and the third trench grid MOSFET (195) have the same structure, and the three trench grid MOSFETs are all normally-off;

The first trench gate MOSFET (193) comprises a first trench gate (13), wherein a first well region (141) is arranged on the left side and the right side of the first trench gate (13), a first source contact region (142) is arranged above each first well region (141), a first contact region (143) is arranged on the left side of the left side first source contact region (142), a first left side source metal (145) is arranged above the left side first source contact region (142) and the first contact region (143), and a first right side source metal (146) is arranged above the right side first source contact region (142); the second trench gate MOSFET (194) comprises a second trench gate (15), wherein a second well region (161) is arranged on the left side and the right side of the second trench gate (15), a second source contact region (162) is arranged above each second well region (161), a second contact region (163) is arranged on the right side of the right side second source contact region (162), a second right side source metal (166) is arranged above the right side second source contact region (162) and the second contact region (163), and a second left side source metal (165) is arranged above the left side second source contact region (162); the first planar gate JFET (191) comprises a first planar gate (17), a first conductive type semiconductor (18) is arranged below the first planar gate (17), and the first conductive type semiconductor (18) is positioned between a first source contact region (142) on the right side and a second source contact region (162) on the left side; the first conductivity type semiconductor of the second planar gate JFET (192) is located between the first source contact region (142) on the right side and the source contact region on the left side of the third trench gate MOSFET (195); the first left source metal (145), the first right source metal (146), the second left source metal (165), the second right source metal (166), the left source metal (1951) and the right source metal (1952) of the third trench gate MOSFET (195) are all connected with the source (112), the first trench gate (13), the second trench gate (15), the gate of the third trench gate MOSFET (195), the gate of the first planar gate (17) and the gate of the second planar gate JFET (192) are all connected with the gate (113), and the gates of the first planar gate (17) and the second planar gate JFET (192) are all perpendicular to the gates of the three trench gate MOSFETs; the source contact regions of the first source contact region (142), the second source contact region (162) and the third trench gate MOSFET (195) are all of a first conductivity type, and the well regions and the contact regions of the first well region (141), the first contact region (143), the second well region (161), the second contact region (163) and the third trench gate MOSFET (195) are all of a second conductivity type.

2. The low leakage current silicon carbide MOSFET cell structure of claim 1, wherein: the first right side source metal (146) ohmic contact or ground;

And/or

A second left side source metal (165) ohmic contact or ground;

And/or

The left side source metal (1951) of the third trench gate MOSFET (195) is in ohmic contact or grounded.

3. The low leakage current silicon carbide MOSFET cell structure of claim 1, wherein: the ion concentration range of the first contact region (143) and the first source contact region (142) on the left side is 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the first source contact region (142) on the right side ranges from 1 x 10 ¹⁸～1×10²¹cm^-3;

And/or

The second source contact region (162) on the left has an ion concentration in the range of 1 x 10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the second source contact region (162) and the second contact region (163) on the right side is 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the source contact region on the left side of the third trench gate MOSFET (195) is in the range of 1X 10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the source contact region on the right side of the third trench gate MOSFET (195) and the contact region on the right side thereof is 1×10 ¹⁸～1×10²¹cm^-3.

4. The low leakage current silicon carbide MOSFET cell structure of claim 1, wherein: the distance X1 between the first well region (141) on the right side of the first trench gate (13) and the second well region (161) on the left side of the second trench gate (15) is in the range of 0.5-1 mu m;

And/or

The distance between the first well region (141) on the right side of the first trench gate (13) and the well region on the left side of the gate of the third trench gate MOSFET (195) is in the range of 0.5-1 mu m.

5. The low leakage current silicon carbide MOSFET cell structure of claim 1, wherein: a first shielding region (144) is arranged below the first well region (141) on the right side of the first trench gate (13);

And/or

A second shielding region (164) is arranged below the second well region (161) at the left side of the second trench gate (15);

And/or

A shielding region is arranged below the well region at the left side of the grid electrode of the third trench grid MOSFET (195).

6. The low leakage current silicon carbide MOSFET cell structure of claim 5, wherein: when a first shielding region (144) is arranged below a first well region (141) on the right side of the first trench gate (13) and a second shielding region (164) is arranged below a second well region (161) on the left side of the second trench gate (15), the value range of the distance X2 between the first shielding region (144) and the second shielding region (164) is 0.5-1 mu m;

And when a first shielding region (144) is arranged below the first well region (141) on the right side of the first trench gate (13), and a shielding region is arranged below the well region on the left side of the gate of the third trench gate MOSFET (195), the distance between the first shielding region (144) and the shielding region of the third trench gate MOSFET (195) is in a value range of 0.5-1 mu m.

7. A low leakage current silicon carbide MOSFET cell structure is characterized in that: the semiconductor device is characterized in that a drain electrode, a first conductive type medium layer, a first conductive type buffer layer, a first conductive type drift layer and a current diffusion layer are sequentially arranged from bottom to top, one side of the current diffusion layer is provided with a first trench gate MOSFET (21), the other side of the current diffusion layer is provided with a second trench gate MOSFET (22), and a plane gate JFET (23) is arranged between the first trench gate MOSFET (21) and the second trench gate MOSFET (22); the plane grid JFET (23) is normally-on, and the two trench grid MOSFETs are both normally-off;

The first trench gate MOSFET (21) comprises a first trench gate, wherein a first well region is arranged on the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, a first contact region is arranged on the left side of the left side first source contact region, a first left side source metal (211) is arranged above the left side first source contact region and the first contact region, and a first right side source metal (212) is arranged above the right side first source contact region; the second trench gate MOSFET (22) comprises a second trench gate, wherein a second well region is arranged on the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, a second contact region is arranged on the right side of the right side second source contact region, a second right side source metal (222) is arranged above the right side second source contact region and the second contact region, and a second left side source metal (221) is arranged above the left side second source contact region; the planar gate JFET (23) comprises a planar gate, and a first conductive type semiconductor is arranged below the planar gate and positioned between a first source contact area on the right side and a second source contact area on the left side; the first left source metal (211), the first right source metal (212), the second left source metal (221) and the second right source metal (222) are all connected with sources, the first trench gate, the second trench gate and the plane gate are all connected with gates, and the plane gate is parallel to the gates of the two trench gate MOSFETs; the first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type.

8. The low leakage current silicon carbide MOSFET cell structure of claim 7, wherein: the first right side source metal (212) ohmic contact or ground;

And/or

A second left source metal (221) ohmic contact or ground;

And/or

9. The low leakage current silicon carbide MOSFET cell structure of claim 7, wherein: the distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is in the range of 0.5-1 mu m.

10. The low leakage current silicon carbide MOSFET cell structure of claim 7, wherein: a first shielding region is arranged below the first well region on the right side of the first trench gate;

And/or

11. The low leakage current silicon carbide MOSFET cell structure of claim 10, wherein: and when the first shielding region is arranged below the first well region on the right side of the first trench gate, and the second shielding region is arranged below the second well region on the left side of the second trench gate, the value range of the distance between the first shielding region and the second shielding region is 0.5-1 mu m.

12. A low leakage current silicon carbide MOSFET cell structure is characterized in that: the drain electrode (311), the first conductive type medium layer (321), the first conductive type buffer layer (322), the first conductive type drift layer (323) and the current diffusion layer (324) are sequentially arranged from bottom to top, a first trench gate MOSFET (393) is arranged on one side of the current diffusion layer (324), a second trench gate MOSFET (394) and a third trench gate MOSFET (395) positioned behind the second trench gate MOSFET are arranged on the other side of the current diffusion layer (324), a first plane gate JFET (391) is arranged between the first trench gate MOSFET (393) and the second trench gate MOSFET (394), and a second plane gate JFET (392) is arranged between the first trench gate MOSFET (393) and the third trench gate MOSFET (395); the first plane grid JFET (391) and the second plane grid JFET (392) are identical in structure and are all normally-on, the second trench grid MOSFET (394) and the third trench grid MOSFET (395) are identical in structure, and the three trench grid MOSFETs are all normally-off;

The first trench gate MOSFET (393) comprises a first trench gate (33), wherein a first well region (341) is arranged on the left side and the right side of the first trench gate (33), a first source contact region (342) is arranged above each first well region (341), the first source contact region (342) on the left side is communicated with the first source contact region (342) on the right side, a first contact region (343) is arranged on the left side of the first source contact region (342) on the left side, and a first source metal (345) is arranged above the first source contact region (342) on the left side and the first contact region (343); the second trench gate MOSFET (394) comprises a second trench gate (35), wherein a second well region (361) is arranged on the left side and the right side of the second trench gate (35), a second source contact region (362) is arranged above each second well region (361), the second source contact region (362) on the left side is communicated with the second source contact region (362) on the right side, a second contact region (363) is arranged on the right side of the second source contact region (362), and a second source metal (355) is arranged above the second source contact region (362) on the right side and the second contact region (363); the first planar gate JFET (391) comprises a first planar gate (37), a first conductive type semiconductor (38) is arranged below the first planar gate (37), and the first conductive type semiconductor (38) is positioned between a first source contact region (342) on the right side and a second source contact region (362) on the left side; the first conductivity type semiconductor of the second planar gate JFET (392) is located between the first source contact region (342) on the right side and the source contact region on the left side of the third trench gate MOSFET (395); the first source metal (345), the second source metal (355), the source metal (3951) of the third trench gate MOSFET (395), the first plane gate (37) and the grid of the second plane gate JFET (392) are all connected with the source (312), the grid of the first trench gate (33), the grid of the second trench gate (35) and the grid of the third trench gate MOSFET (395) are all connected with the grid (313), and the grid of the first plane gate (37) and the grid of the second plane gate JFET (392) are all vertical to the grid of the three trench gate MOSFETs; the source contact regions of the first source contact region (342), the second source contact region (362) and the third trench gate MOSFET (395) are all of a first conductivity type, and the well regions and the contact regions of the first well region (341), the first contact region (343), the second well region (361), the second contact region (363) and the third trench gate MOSFET (395) are all of a second conductivity type.

13. The low leakage current silicon carbide MOSFET cell structure of claim 12, wherein: the ion concentration range of the first source contact region (342) and the first contact region (343) at the left side is 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the second source contact region (362) and the second contact region (363) on the right side is 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the source contact region on the right side of the third trench gate MOSFET (395) and the contact region on the right side thereof is 1×10 ¹⁸～1×10²¹cm^-3.

14. The low leakage current silicon carbide MOSFET cell structure of claim 12, wherein: the distance X3 between the first well region (341) on the right side of the first trench gate (33) and the second well region (361) on the left side of the second trench gate (35) is in the range of 0.5-1 mu m;

And/or

The distance between the first well region (341) on the right side of the first trench gate (33) and the well region on the left side of the gate of the third trench gate MOSFET (395) is in the range of 0.5-1 μm.

15. The low leakage current silicon carbide MOSFET cell structure of claim 12, wherein: a first buried region (344) is arranged below the first trench gate (33);

And/or

A second buried region (364) is arranged below the second trench gate (35);

And/or

A buried region is provided under the gate of the third trench gate MOSFET (395).

16. The low leakage current silicon carbide MOSFET cell structure of claim 15, wherein: when a first buried region (344) is arranged below the first trench gate (33) and a second buried region (364) is arranged below the second trench gate (35), the distance X4 between the first buried region (344) and the second buried region (364) is in the range of 0.5-1 μm;

when a first buried region (344) is arranged below the first trench gate (33) and a buried region is arranged below the gate of the third trench gate MOSFET (395), the distance between the first buried region (344) and the buried region of the third trench gate MOSFET (395) is in the range of 0.5-1 μm.

17. A low leakage current silicon carbide MOSFET cell structure is characterized in that: the semiconductor device is characterized in that a drain electrode, a first conductive type medium layer, a first conductive type buffer layer, a first conductive type drift layer and a current diffusion layer are sequentially arranged from bottom to top, one side of the current diffusion layer is provided with a first trench gate MOSFET (41), the other side of the current diffusion layer is provided with a second trench gate MOSFET (42), and a plane gate JFET (43) is arranged between the first trench gate MOSFET (41) and the second trench gate MOSFET (42); the plane grid JFET (43) is normally-on, and the two trench grid MOSFETs are both normally-off;

The first trench gate MOSFET (41) comprises a first trench gate, wherein a first well region is arranged on the left side and the right side of the first trench gate, a first source contact region is arranged above each first well region, the first source contact region on the left side is communicated with the first source contact region on the right side, a first contact region is arranged on the left side of the first source contact region on the left side, and first source metal (411) is arranged above the first source contact region on the left side and the first contact region; the second trench gate MOSFET (42) comprises a second trench gate, wherein a second well region is arranged on the left side and the right side of the second trench gate, a second source contact region is arranged above each second well region, the second source contact region on the left side is communicated with the second source contact region on the right side, a second contact region is arranged on the right side of the second source contact region on the right side, and second source metal (421) is arranged above the second source contact region on the right side and the second contact region; the planar gate JFET (43) comprises a planar gate, and a first conductive type semiconductor is arranged below the planar gate and positioned between a first source contact area on the right side and a second source contact area on the left side; the first source metal (411), the second source metal (421) and the plane grid are connected with the source, the first trench grid and the second trench grid are connected with the grid, and the plane grid is parallel to the grid of the two trench grid MOSFETs; the first source contact region and the second source contact region are of a first conductivity type, and the first well region, the first contact region, the second well region and the second contact region are of a second conductivity type.

18. The low leakage current silicon carbide MOSFET cell structure of claim 17, wherein: the ion concentration range of the first source contact region and the first contact region at the left side is 1 multiplied by 10 ¹⁸～1×10²¹cm^-3;

And/or

19. The low leakage current silicon carbide MOSFET cell structure of claim 17, wherein: the distance between the first well region on the right side of the first trench gate and the second well region on the left side of the second trench gate is in the range of 0.5-1 mu m.

20. The low leakage current silicon carbide MOSFET cell structure of claim 17, wherein: a first buried region is arranged below the first trench gate;

And/or

A second buried region is arranged below the second trench gate.

21. The low leakage current silicon carbide MOSFET cell structure of claim 20, wherein: when the first buried region is arranged below the first trench gate, and the second buried region is arranged below the second trench gate, the distance between the first buried region and the second buried region is 0.5-1 μm.

22. A low leakage current silicon carbide MOSFET cell structure is characterized in that: the drain electrode (511), the first conductive type medium layer (521), the first conductive type buffer layer (522), the first conductive type drift layer (523) and the current diffusion layer (524) are sequentially arranged from bottom to top, one side of the current diffusion layer (524) is provided with a first trench gate MOSFET (591), the other side is provided with a second trench gate MOSFET (592), and a gate bus type JFET (593) is arranged between the first trench gate MOSFET (591) and the second trench gate MOSFET (592); the grid bus type JFET (593) is normally-on, and the two trench gate MOSFETs are both normally-off;

The first trench gate MOSFET (591) comprises a first trench gate (53), a first well region (541) is respectively arranged on the left side and the right side of the first trench gate (53), a first source contact region (542) is arranged above each first well region (541), a first contact region (543) is arranged on the left side of the left first source contact region (542), a first left source metal (545) is arranged above the left first source contact region (542) and the first contact region (543), and a first right source metal (546) is arranged above the right first source contact region (542); the second trench gate MOSFET (592) comprises a second trench gate (55), wherein a second well region (561) is arranged on the left side and the right side of the second trench gate (55), a second source contact region (562) is arranged above each second well region (561), a second contact region (563) is arranged on the right side of the right side second source contact region (562), a second right side source metal (566) is arranged above the right side second source contact region (562) and the second contact region (563), and a second left side source metal (565) is arranged above the left side second source contact region (562); the grid bus type JFET (593) comprises a first conductive type semiconductor (58) positioned between a first source contact region (542) on the right side and a second source contact region (562) on the left side, a field oxide layer (572) is arranged above the first conductive type semiconductor (58), and a grid bus bar (571) is arranged inside the field oxide layer (572); the first left source metal (545), the first right source metal (546), the second left source metal (565) and the second right source metal (566) are all connected to the source (512), the first trench gate (53), the second trench gate (55) and the gate bus (571) are all connected to the gate (513), and the gate bus (571) is parallel to the gates of the two trench gate MOSFETs; wherein the first source contact region (542) and the second source contact region (562) are of a first conductivity type, and the first well region (541), the first contact region (543), the second well region (561) and the second contact region (563) are of a second conductivity type.

23. The low leakage current silicon carbide MOSFET cell structure of claim 22, wherein: the first right side source metal (546) ohmic contact or ground;

And/or

A second left side source metal (565) ohmic contact or ground;

And/or

The ion concentration ranges of the first contact region (543) and the first source contact region (542) on the left side are 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the first source contact region (542) on the right side ranges from 1×10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration of the second source contact region (562) on the left side ranges from 1 x 10 ¹⁸～1×10²¹cm^-3;

And/or

The ion concentration range of the second source contact region (562) and the second contact region (563) on the right side is 1×10 ¹⁸～1×10²¹cm^-3.

24. The low leakage current silicon carbide MOSFET cell structure of claim 22, wherein: the distance X5 between the first well region (541) at the right side of the first trench gate (53) and the second well region (561) at the left side of the second trench gate (55) is in the range of 0.5-1 μm.

25. The low leakage current silicon carbide MOSFET cell structure of claim 22, wherein: a first shielding region (544) is arranged below the first well region (541) on the right side of the first trench gate (53);

And/or

A second shielding region (564) is arranged below the second well region (561) at the left side of the second trench gate (55).

26. The low leakage current silicon carbide MOSFET cell structure of claim 25, wherein: when the first shielding region (544) is arranged below the first well region (541) on the right side of the first trench gate (53) and the second shielding region (564) is arranged below the second well region (561) on the left side of the second trench gate (55), the value range of the distance X6 between the first shielding region (544) and the second shielding region (564) is 0.5-1 μm.

27. A low leakage current silicon carbide MOSFET device, characterized by: a silicon carbide MOSFET cell structure comprising a low leakage current as recited in any one of claims 1-26.