CN117728366A - A quick overvoltage protection circuit for LDO - Google Patents
A quick overvoltage protection circuit for LDO Download PDFInfo
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- CN117728366A CN117728366A CN202311656856.XA CN202311656856A CN117728366A CN 117728366 A CN117728366 A CN 117728366A CN 202311656856 A CN202311656856 A CN 202311656856A CN 117728366 A CN117728366 A CN 117728366A
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Abstract
The invention relates to a rapid overvoltage protection circuit for LDO, belonging to the technical field of electronic circuits. The rapid overvoltage protection circuit for the LDO comprises a comparator and a rapid overvoltage protection unit, wherein the rapid overvoltage protection unit comprises a first voltage dividing resistor R connected in series 1 And a second voltage dividing resistor R 2 Also comprises a first voltage dividing resistor R 1 A parallel fast capacitor C, a first voltage dividing resistor R 1 One end is connected with an input voltage V IN The other end is a sampling signal V 1 The reverse input end of the comparator is connected with the reference voltage V REF The positive input end is connected with the sampling signal V 1 . Thus when the input voltage V IN When the delta V is fluctuated in a large range, the voltage difference at the two ends of the capacitor C does not generate abrupt change, and the input voltage of the comparator samples the signal V 1 And the delta V can be fluctuated along with the input voltage, so that quick response to the change of the input voltage is realized, and the LDO chip is protected from damage.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to the technical field of LDO chip circuit structures, and specifically relates to a circuit for rapid overvoltage protection of an LDO.
Background
With the development of electronic technology, power management chips are widely used in electronic devices. Among them, LDO (low dropout regulator) chips are an indispensable class. The LDO chip inevitably encounters a problem of circuit overvoltage in daily use, and thus the circuit overvoltage module becomes an indispensable part of the LDO chip.
However, in the existing overvoltage module, when the input voltage V IN When the fluctuation occurs in a large range, the input voltage of the comparator cannot change in a short time, so that the overvoltage protection circuit cannot work normally, and the power switch tube can be broken down.
Accordingly, providing an overvoltage protection circuit that can respond quickly to voltage changes is a problem that is highly desirable in the art.
Disclosure of Invention
The object of the present invention is to overcome the drawbacks of the prior art described above and to provide an overvoltage protection circuit which is capable of fast response to voltage variations.
In order to achieve the above object, the fast overvoltage protection circuit for LDO of the present invention has a comparator and a fast overvoltage protection unit.
The reverse input end of the comparator is connected with a reference voltage V REF The positive input end of the comparator is connected with the sampling signal V 1 The method comprises the steps of carrying out a first treatment on the surface of the The rapid overvoltage protection unit comprises a first voltage dividing resistor R connected in series 1 And a second voltage dividing resistor R 2 Also comprises a first voltage dividing resistor R 1 A parallel fast capacitor C, the first voltage dividing resistor R 1 One end of (2) is connected with the input voltage V IN The other end is the sampling signal V 1 And is connected with the positive input end of the comparator and the second voltage dividing resistor R 2 The second voltage-dividing resistor R 2 The other end of which is grounded.
In the fast overvoltage protection circuit for the LDO, the comparator comprises a differential pair and an amplifier. The differential pair comprises a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a first P-type MOS tube MP1 and a second P-type MOS tube MP2; the amplifier comprises a fourth P-type MOS tube MP4 and a fifth P-type MOS tube MP5; the fourth P-type MOS tube MP4 and the third P-type MOS tube MP3 form a hysteresis module.
Wherein the grid electrode of the first N-type MOS tube MN1 is connected with the reference voltage V REF ；
The drain electrode of the first N-type MOS tube MN1 is connected with the grid electrodes of the first P-type MOS tube MP1, the second P-type MOS tube MP2 and the third P-type MOS tube MP3, and is also connected with the drain electrode of the first P-type MOS tube MP 1;
the sources of the first P-type MOS tube MP1, the second P-type MOS tube MP2, the third P-type MOS tube MP3 and the fifth P-type MOS tube MP5 are all connected with a power supply voltage V DD ；
The drain electrode of the second P-type MOS tube MP2 is connected with the drain electrode of the second N-type MOS tube MN2 and the grid electrode of the fifth P-type MOS tube MP5;
the grid electrode of the second N-type MOS tube MN2 is connected with the sampling signal V 1 ；
The sources of the first N-type MOS tube MN1 and the second N-type MOS tube MN2 are connected with the drain of the third N-type MOS tube MN3,
the grid electrode of the third N-type MOS tube MN3 is connected with the grid electrode of the fourth N-type MOS tube MN 4;
the drains of the fourth N-type MOS transistor MN4 and the fifth P-type MOS transistor MP5 are output ends of the comparator, and are connected to the gates of the fourth P-type MOS transistor MP 4;
the sources of the third N-type MOS tube MN3 and the fourth N-type MOS tube MN4 are grounded;
the drain electrode of the third P-type MOS tube MP3 is connected with the source electrode of the fourth P-type MOS tube MP 4;
the drain electrode of the fourth P-type MOS tube MP4 is connected with the grid electrode of the fifth P-type MOS tube MP 5.
In the rapid overvoltage protection circuit for LDO, the drains of the fourth N-type MOS transistor MN4 and the fifth P-type MOS transistor MP5 are both connected to the input terminal of the schmitt trigger SMIT, the output terminal of the schmitt trigger SMIT is connected to one input terminal of the inverter INV2, the other input terminal of the inverter INV2 is grounded, and the output terminal of the inverter INV2 is connected to the gate of the fourth P-type MOS transistor MP 4.
In the rapid overvoltage protection circuit for the LDO, the length-width ratio of the first P-type MOS tube MP1 is consistent with that of the second P-type MOS tube MP 2.
The rapid overvoltage protection circuit for LDO comprises a comparator and a rapid overvoltage protection unit, wherein the rapid overvoltage protection unit comprises a first voltage dividing resistor R connected in series 1 And a second voltage dividing resistor R 2 Also comprises a first voltage dividing resistor R 1 A parallel fast capacitor C, a first voltage dividing resistor R 1 One end is connected with an input voltage V IN The other end is a sampling signal V 1 The reverse input end of the comparator is connected with the reference voltage V REF The positive input end is connected with the sampling signal V 1 . Thus when the input voltage V IN When the delta V is fluctuated in a large range, the voltage difference at the two ends of the capacitor C does not generate abrupt change, and the input voltage of the comparator samples the signal V 1 And the delta V can be fluctuated along with the input voltage, so that quick response to the change of the input voltage is realized, and the LDO chip is protected from damage.
Drawings
Fig. 1 is a schematic circuit diagram of a fast overvoltage protection circuit for LDO according to the present invention.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
Fig. 1 is a schematic circuit diagram of a fast overvoltage protection circuit for LDO according to the present invention.
In one embodiment, the fast overvoltage protection circuit for an LDO includes a comparator and a fast overvoltage protection unit.
Wherein the rapid overvoltage protection unit comprises a first voltage dividing resistor R connected in series 1 And a second voltage dividing resistor R 2 Also comprises a first voltage dividing resistor R 1 A parallel fast capacitor C, the first voltage dividing resistor R 1 One end of (2) is connected with the input voltage V IN The other end is the sampling signal V 1 And is connected with the positive input end of the comparator and the second voltage dividing resistor R 2 The first step ofVoltage-dividing resistor R 2 The other end of which is grounded. The reverse input end of the comparator is connected with a reference voltage V REF The positive input end of the comparator is connected with the sampling signal V 1 。
In a preferred embodiment, the comparator comprises a differential pair and an amplifier. The differential pair may be a five-tube differential pair, as shown in fig. 1, and includes a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a first P-type MOS tube MP1, and a second P-type MOS tube MP2, where aspect ratios of the first P-type MOS tube MP1 and the second P-type MOS tube MP2 are consistent. The amplifier comprises a fourth P-type MOS tube MP4 and a fifth P-type MOS tube MP5; the fourth P-type MOS tube MP4 and the third P-type MOS tube MP3 form a hysteresis module.
Wherein the grid electrode of the first N-type MOS tube MN1 is connected with the reference voltage V REF The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the first N-type MOS tube MN1 is connected with the grid electrodes of the first P-type MOS tube MP1, the second P-type MOS tube MP2 and the third P-type MOS tube MP3, and is also connected with the drain electrode of the first P-type MOS tube MP 1; the sources of the first P-type MOS tube MP1, the second P-type MOS tube MP2, the third P-type MOS tube MP3 and the fifth P-type MOS tube MP5 are all connected with a power supply voltage V DD The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the second P-type MOS tube MP2 is connected with the drain electrode of the second N-type MOS tube MN2 and the grid electrode of the fifth P-type MOS tube MP5; the grid electrode of the second N-type MOS tube MN2 is connected with the sampling signal V 1 The method comprises the steps of carrying out a first treatment on the surface of the The sources of the first N-type MOS tube MN1 and the second N-type MOS tube MN2 are connected with the drain electrode of the third N-type MOS tube MN3, and the grid electrode of the third N-type MOS tube MN3 is connected with the grid electrode of the fourth N-type MOS tube MN 4; the drains of the fourth N-type MOS transistor MN4 and the fifth P-type MOS transistor MP5 are output ends of the comparator, and are connected to the gates of the fourth P-type MOS transistor MP 4; the sources of the third N-type MOS tube MN3 and the fourth N-type MOS tube MN4 are grounded; the drain electrode of the third P-type MOS tube MP3 is connected with the source electrode of the fourth P-type MOS tube MP 4; the drain electrode of the fourth P-type MOS tube MP4 is connected with the grid electrode of the fifth P-type MOS tube MP 5.
In a preferred embodiment, the drains of the fourth N-type MOS transistor MN4 and the fifth P-type MOS transistor MP5 are both connected to an input terminal of a schmitt trigger SMIT, an output terminal of the schmitt trigger SMIT is connected to one input terminal of the inverter INV2 and an input terminal of the not gate INV1, the other input terminal of the inverter INV2 is grounded, and an output terminal of the inverter INV2 is connected to the gate of the fourth P-type MOS transistor MP 4.
In practical application, the fast overvoltage protection circuit for LDO of the present invention is shown in fig. 1.
The first N-type MOS transistor MN1, the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, the first P-type MOS transistor MP1, and the second P-type MOS transistor MP2 are five differential pairs. The five-tube differential pair and a common source amplifier composed of a fifth P-type MOS tube MP5 and a fourth P-type MOS tube MP4 form a two-stage comparator together. The two-stage comparator has higher gain, and can increase the comparison accuracy of the voltage. The reverse input end of the voltage comparator inputs a reference voltage V which is provided by a band gap reference module and is irrelevant to temperature REF The third N-type MOS tube MN3 and the fourth N-type MOS tube MN4 provide stable bias V for the differential pair and the fifth P-type MOS tube MP5 bia . The positive input terminal inputs the input voltage V to the switch IN Sampling signal V generated by resistor voltage division 1 。
The third P-type MOS tube MP3 and the fourth P-type MOS tube MP4 are a pair of asymmetric currents introduced when the comparator outputs low level, and hysteresis voltage with a certain value is generated through the asymmetry of the two branches. The hysteresis between the upper threshold and the lower threshold is realized by the offset characteristic of the pointer pair five-tube differential pair, and the hysteresis voltage between the upper threshold and the lower threshold can be calculated by calculating the input offset voltage of the five-tube differential pair. Ideally, when the voltages at the two input ends of the five-tube differential pair are equal, the differential output is zero, but in practical situations, even if the input voltages are equal, the output will have a tiny voltage, and at this time, an input offset voltage needs to be added to the input ends, so that the output voltage is zero. The offset voltage of the five-tube differential pair generally comprises a system offset voltage and a random offset voltage. Random offset voltages are generally caused by mismatch of actual parameters of two pipes due to randomness in the manufacturing process, and system offset voltages are generally caused by inherent mismatch caused by structural defects of a differential pair, and can be avoided by improving the structure. The offset voltage in the circuit is mainly generated by changing the structure.
In fig. 1, a random offset input voltage V generated by a first N-type MOS transistor MN1 and a second N-type MOS transistor MN2 OS,R Is delta V TH,N ：
V OS，R ＝ΔV TH，N ＝V TH1 -V TH2
In the above, deltaV TH,N V is the difference between the threshold voltages of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 TH1 Is the threshold voltage, V, of the first N-type MOS transistor MN1 TH2 The threshold voltage of the second N-type MOS transistor MN 2;
system offset input voltage V of first N-type MOS tube MN1 and second N-type MOS tube MN2 OS,S The method comprises the following steps:
in the above, I D1 、I D2 The leakage current of the first N-type MOS tube MN1 tube and the leakage current of the second N-type MOS tube MN2 tube are respectively, k' is the technological parameter of the MOS tube, (W/L) 1 、(W/L) 2 The width-to-length ratio of the first N-type MOS tube MN1 and the second N-type MOS tube MN2 is respectively; v (V) GS Is the source-drain voltage of the MOS tube, V TH Is the threshold voltage of the MOS tube;
offset input voltage V generated by first N-type MOS tube MN1 and second N-type MOS tube MN2 OS,N The method comprises the following steps:
similarly, offset voltage V generated by first P-type MOS tube MP1 and second P-type MOS tube MP2 OS,P The method comprises the following steps:
the first P-type MOS tube MP1 and the second P-type MOS tube are connectedThe offset voltage generated by the tube MP2 is equivalent to the differential input end, and the offset voltage generated by the first N-type MOS tube MN1 and the second N-type MOS tube MN2 is added with the voltage equivalent to the differential input end of the first P-type MOS tube MP1 and the second P-type MOS tube MP2, so that the offset voltage V of the system can be obtained OS About:
the method comprises the following steps:
offset voltage V calculated here OS The threshold voltage set for the circuit can change the offset ratio of the width-to-length ratio of the MOS tube according to the specific requirement of the circuit on the threshold voltage to obtain a corresponding voltage threshold, and in the circuit design of the invention, the overvoltage protection hysteresis is set at about 0.2V and the undervoltage protection hysteresis is set at about 0.1V.
Schmitt trigger SMIT prevents false triggering of the overvoltage protection circuit around a threshold in the circuit. The comparator is in the circuit and utilizes the fast capacitor C to realize fast overvoltage protection. In the case of a circuit without a capacitor, when the input voltage V IN When the fluctuation occurs in a large range, the first voltage dividing resistor R is used for 1 The power switch tube has a certain inductance, the input voltage of the comparator cannot change in a short time, so that the overvoltage protection circuit cannot work normally, and the power switch tube can break down; when the input port of the circuit is connected with the capacitor, the voltage difference at the two ends of the capacitor C can not be changed suddenly, and the voltage V is input IN When the delta V is fluctuated in a large range, the voltage V is input into the comparator 1 And also fluctuates with the voltage DeltaV, thereby realizing the input voltage V IN A rapid response to the change.
Specifically, the overvoltage protection circuit is implemented by applying an input voltage V IN Through a first voltage dividing resistor R 1 And a second voltage dividing resistor R 2 Divided voltage is used as the grid input voltage V of the second N-type MOS tube MN2 1 And judging whether the power supply voltage is below an overvoltage protection threshold value by adopting a current comparison mode. After the circuit starts to power up, the voltage V is input IN Gradually rise, as shown in FIG. 1, current I 1 Through the first P-type MOS tube MP1 and the first N-type MOS tube MN1, the current I is as the width-to-length ratio of the first P-type MOS tube MP1 and the second P-type MOS tube MP2 is consistent 1 The current I is copied to the second P-type MOS tube MP2 through the first P-type MOS tube MP1 and flows through the second P-type MOS tube MP2 3 Equal to I 1 Current I 3 And I 2 A comparison is made. As the differential pair input tube is an NMOS tube, the current with large grid voltage is larger according to the current formula of the saturation region, thus I 3 >I 2 . However, the second P-type MOS tube MP2 is connected in series with the second N-type MOS tube MN2 in order to satisfy I 3 ＝I 2 It is necessary to increase I 2 At this time, the gate voltage V of the second N-type MOS transistor MN2 is increased 1 . When V is 1 <V REF When the signal is processed by the comparator and then outputs a low level, the signal passes through the schmitt trigger SMIT and the inverter INV2 and then outputs a low level, the fourth P-type MOS tube MP4 is conducted, and current is injected into the branch of the second N-type MOS tube MN 2. With V IN Gradually increase, V 1 And also starts to increase. When V is 1 ＝V REF When the comparator output level is turned over, the next state is entered, at this time V 1 The value of (a) is the upper threshold voltage V of the overvoltage protection circuit H . When V is 1 >V REF When the comparator outputs a high-level signal, the high-level signal is output to be high level after passing through the schmitt trigger SMIT and the inverter INV2, the fourth P-type MOS transistor MP4 is turned off, and the third P-type MOS transistor MP3 and the fourth P-type MOS transistor MP4 stop injecting current to the second N-type MOS transistor MN 2.
At V 1 >V REF Under the condition of I 2 >I 3 If desired I 2 ＝I 3 The gate input voltage V of the second N-type MOS transistor MN2 needs to be reduced 1 When the input voltage V IN Start to gradually descend at this time V 1 And also starts to decrease. At this time, the output voltage of the comparator is high, the signal is processed by the schmitt trigger SMIT and the inverter INV2 and then output to be high, and the gate of the fourth P-type MOS MP4 is connected to the gate of the third P-type MOS transistorThe voltage is high, the fourth P-type MOS tube MP4 is cut off, the fourth P-type MOS tube MP4 stops injecting current into the second N-type MOS tube MN2, when V IN Gradually drop down to V 1 ＝V REF When the circuit is inverted, V 1 Has a value of lower threshold voltage V L 。
The rapid overvoltage protection circuit for LDO comprises a comparator and a rapid overvoltage protection unit, wherein the rapid overvoltage protection unit comprises a first voltage dividing resistor R connected in series 1 And a second voltage dividing resistor R 2 Also comprises a first voltage dividing resistor R 1 A parallel fast capacitor C, a first voltage dividing resistor R 1 One end is connected with an input voltage V IN The other end is a sampling signal V 1 The reverse input end of the comparator is connected with the reference voltage V REF The positive input end is connected with the sampling signal V 1 . Thus when the input voltage V IN When the delta V is fluctuated in a large range, the voltage difference at the two ends of the capacitor C does not generate abrupt change, and the input voltage of the comparator samples the signal V 1 And the delta V can be fluctuated along with the input voltage, so that quick response to the change of the input voltage is realized, and the LDO chip is protected from damage.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (4)
1. A fast overvoltage protection circuit for an LDO, comprising: comparator and fast overvoltage protection unit, the reverse input of the comparator is connected with reference voltage (V REF ) The positive input of the comparator is connected to a sampling signal (V 1 ) The method comprises the steps of carrying out a first treatment on the surface of the The fast overvoltage protection unit comprises a first voltage dividing resistor (R 1 ) And a second voltage dividing resistor (R 2 ) Also comprises a voltage divider resistor (R 1 ) A fast capacitor (C) connected in parallel, said first voltage dividing resistor (R 1 ) One end of (2) is connected with an input voltage (V IN ) The other end is the sampling signal (V 1 ) And is connected to the positive input of the comparator and the second voltage dividing resistor (R 2 ) The second voltage-dividing resistor (R 2 ) The other end of which is grounded.
2. The rapid overvoltage protection circuit for LDO according to claim 1, wherein the comparator comprises a differential pair and an amplifier, the differential pair comprising a first N-type MOS transistor (MN 1), a second N-type MOS transistor (MN 2), a third N-type MOS transistor (MN 3), a first P-type MOS transistor (MP 1) and a second P-type MOS transistor (MP 2); the amplifier comprises a fourth P-type MOS tube (MP 4) and a fifth P-type MOS tube (MP 5); the fourth P-type MOS tube (MP 4) and the third P-type MOS tube (MP 3) form a hysteresis module,
the grid electrode of the first N-type MOS tube (MN 1) is connected with the reference voltage (V) REF )；
The drain electrode of the first N-type MOS tube (MN 1) is connected with the grid electrodes of the first P-type MOS tube (MP 1), the second P-type MOS tube (MP 2) and the third P-type MOS tube (MP 3), and is also connected with the drain electrode of the first P-type MOS tube (MP 1);
the sources of the first P-type MOS tube (MP 1), the second P-type MOS tube (MP 2), the third P-type MOS tube (MP 3) and the fifth P-type MOS tube (MP 5) are all connected with a power supply voltage (V) DD )；
The drain electrode of the second P-type MOS tube (MP 2) is connected with the drain electrode of the second N-type MOS tube (MN 2) and the grid electrode of the fifth P-type MOS tube (MP 5);
the grid electrode of the second N-type MOS tube (MN 2) is connected with the sampling signal (V) 1 )；
The sources of the first N-type MOS tube (MN 1) and the second N-type MOS tube (MN 2) are connected with the drain of the third N-type MOS tube (MN 3);
the grid electrode of the third N-type MOS tube (MN 3) is connected with the grid electrode of the fourth N-type MOS tube (MN 4);
the drains of the fourth N-type MOS tube (MN 4) and the fifth P-type MOS tube (MP 5) are the output ends of the comparator and are connected with the grid electrode of the fourth P-type MOS tube (MP 4);
the sources of the third N-type MOS tube (MN 3) and the fourth N-type MOS tube (MN 4) are grounded;
the drain electrode of the third P-type MOS tube (MP 3) is connected with the source electrode of the fourth P-type MOS tube (MP 4);
the drain electrode of the fourth P-type MOS tube (MP 4) is connected with the grid electrode of the fifth P-type MOS tube (MP 5).
3. The rapid overvoltage protection circuit for LDO according to claim 2, wherein the drains of the fourth N-type MOS transistor (MN 4) and the fifth P-type MOS transistor (MP 5) are connected to the input of a schmitt trigger (SMIT), the output of the schmitt trigger (SMIT) is connected to one input of an inverter (INV 2), the other input of the inverter (INV 2) is grounded, and the output of the inverter (INV 2) is connected to the gate of the fourth P-type MOS transistor (MP 4).
4. The rapid overvoltage protection circuit for LDO according to claim 2, wherein the aspect ratio of the first P-type MOS transistor (MP 1) and the second P-type MOS transistor (MP 2) is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311656856.XA CN117728366B (en) | 2023-12-06 | A quick overvoltage protection circuit for LDO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311656856.XA CN117728366B (en) | 2023-12-06 | A quick overvoltage protection circuit for LDO |
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| Publication Number | Publication Date |
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| CN117728366A true CN117728366A (en) | 2024-03-19 |
| CN117728366B CN117728366B (en) | 2024-07-30 |
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| CN103001490A (en) * | 2012-12-20 | 2013-03-27 | 西安电子科技大学 | Direct current (DC)-DC conversion controller with overload protection function |
| JP2014060484A (en) * | 2012-09-14 | 2014-04-03 | Renesas Electronics Corp | Semiconductor device |
| CN108803764A (en) * | 2018-06-25 | 2018-11-13 | 电子科技大学 | A kind of LDO circuit of fast transient response |
| CN208608726U (en) * | 2018-08-09 | 2019-03-15 | 厦门安斯通微电子技术有限公司 | A kind of LDO output over-voltage protection structure not increasing quiescent current |
| CN115542990A (en) * | 2022-09-28 | 2022-12-30 | 瀚昕微电子(无锡)有限公司 | Quick response LDO circuit with multiple protection functions |
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014060484A (en) * | 2012-09-14 | 2014-04-03 | Renesas Electronics Corp | Semiconductor device |
| CN103001490A (en) * | 2012-12-20 | 2013-03-27 | 西安电子科技大学 | Direct current (DC)-DC conversion controller with overload protection function |
| CN108803764A (en) * | 2018-06-25 | 2018-11-13 | 电子科技大学 | A kind of LDO circuit of fast transient response |
| CN208608726U (en) * | 2018-08-09 | 2019-03-15 | 厦门安斯通微电子技术有限公司 | A kind of LDO output over-voltage protection structure not increasing quiescent current |
| CN115542990A (en) * | 2022-09-28 | 2022-12-30 | 瀚昕微电子(无锡)有限公司 | Quick response LDO circuit with multiple protection functions |
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