CN117712087A - Method for improving uniformity of Efuse - Google Patents
Method for improving uniformity of Efuse Download PDFInfo
- Publication number
- CN117712087A CN117712087A CN202311597792.0A CN202311597792A CN117712087A CN 117712087 A CN117712087 A CN 117712087A CN 202311597792 A CN202311597792 A CN 202311597792A CN 117712087 A CN117712087 A CN 117712087A
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- Prior art keywords
- efuse
- cathode
- wafer
- oxide layer
- anode
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- 238000004528 spin coating Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a method for improving uniformity of Efuse, comprising an anode structure for forming an Efuse anode and a cathode structure for forming an Efuse cathode on a wafer; the cathode structure is covered with an oxide layer and a SiN layer formed on the oxide layer; spin coating photoresist on a wafer, and exposing and developing; wherein regions of the cathode structure are not developed; performing SAB etching on the wafer, wherein the etching is not performed because the area of the cathode structure is covered by the photoresist; removing the photoresist on the cathode structure, and then removing an oxide layer in the etched area of the wafer SAB; a metal silicide is formed on the anode structure. The invention protects the Efuse cathode by utilizing the SAB silicon nitride in the prior art, and enables the cathode to form a metal-free silicide structure in the subsequent process, thereby remarkably improving the uniformity of resistance value after Efuse programming and greatly improving the yield of Efuse.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving uniformity of Efuse.
Background
Along with the progress of semiconductor process, the integration level of the chip is higher and higher, but at the same time, various defects are more and more easy to occur in the chip, which seriously affects the yield and the reliability of the chip. Efuse (electrically programmable fuse) it belongs to one-time programmable memory technology, when the chip is failed, the redundant circuit formed by Efuse can be used to replace failed failure circuit module, and the output of the chip can be regulated by reading the information in Efuse memory circuit, so that the working performance of the chip can be improved. Therefore, the Efuse plays an important role in improving the yield and the reliability of the chip.
Efuse utilizes electromigration and thermal fusing phenomena to realize the change of resistance values before and after programming, and the stability and uniformity of the resistance values before and after programming directly influence the programming effect and the reliability of the resistance values, thereby influencing the yield of chips. Therefore, the method provides a method for improving the uniformity of the Efuse, utilizes SAB Nitride to enable a cathode to form non-silicon, and reduces the migration quantity of metal atoms to enable the electromigration of the metal atoms to be more sufficient, thereby improving the uniformity of the resistance after programming.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving uniformity of Efuse, which is used for solving the problem that the programming effect and reliability are poor and the chip yield is affected due to unstable and uneven Efuse resistance values before and after programming in the prior art.
To achieve the above and other related objects, the present invention provides a method of improving uniformity of an Efuse,
step one, providing a wafer, wherein the wafer comprises an anode structure for forming an Efuse anode and a cathode structure for forming an Efuse cathode; the cathode structure is covered with an oxide layer and a SiN layer formed on the oxide layer;
spin coating photoresist on the wafer, and exposing and developing; wherein regions of the cathode structure are not developed;
step three, performing SAB etching on the wafer, wherein the etching is not performed because the area of the cathode structure is covered by photoresist;
step four, removing the photoresist on the cathode structure, and then removing an oxide layer in the etched area of the wafer SAB;
and fifthly, forming metal silicide on the anode structure.
Preferably, the cathode structure in the first step includes a gate structure, and the gate structure includes a polysilicon structure and a sidewall attached to a sidewall of the polysilicon structure.
Preferably, in the second step, the area of the anode structure is developed.
Preferably, in the third step, the region of the anode structure of the wafer is subjected to SAB etching.
Preferably, in the fourth step, the oxide layer is removed by wet etching.
Preferably, the length of the cathode structure of the Efuse is 0.1-0.3 μm; the width is 0.5-0.7 mu m.
Preferably, the programming voltage of the Efuse is 2.3-3.0V; the programming time is 8-15 mu s.
Preferably, the length of the Efuse contact hole is 0.5-0.8 μm; the width is 0.5-0.8 mu m.
As described above, the method for improving uniformity of an Efuse of the present invention has the following advantageous effects: the invention protects the Efuse cathode by utilizing the SAB silicon nitride in the prior art, and enables the cathode to form a metal-free silicide (non-silicide) structure in the subsequent process, thereby remarkably improving the uniformity of resistance value after Efuse programming and greatly improving the yield of Efuse.
Drawings
FIGS. 1 to 4 are schematic views showing a cathode structure in each step of a method for improving uniformity of Efuse in the present invention;
fig. 5 shows a flow chart of a method of improving the uniformity of an Efuse in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a method for improving uniformity of Efuse, which at least comprises the following steps:
step one, providing a wafer, wherein the wafer comprises an anode structure for forming an Efuse anode and a cathode structure for forming an Efuse cathode; the cathode structure is covered with an oxide layer and a SiN layer formed on the oxide layer;
in a further aspect of the present invention, the cathode structure in the step one of the present embodiments includes a gate structure, where the gate structure includes a polysilicon structure and a sidewall attached to a sidewall of the polysilicon structure.
As shown in fig. 1, the first step provides a wafer having an anode structure for forming an Efuse anode and a cathode structure for forming an Efuse cathode; wherein the cathode structure comprises an STI structure 01, the cathode structure is covered with an oxide layer 02 and a SiN layer 03 formed on the oxide layer 02; as shown in fig. 1, the cathode structure includes a gate structure, and the gate structure includes a polysilicon structure and a sidewall attached to a sidewall of the polysilicon structure.
Spin coating photoresist on the wafer, and exposing and developing; wherein regions of the cathode structure are not developed;
further, the region of the anode structure is developed in step two of the present embodiment.
As shown in fig. 1, the second step is to spin-coat photoresist on the wafer, expose and develop; wherein regions of the cathode structure are not developed; areas of the anode structure are developed. That is, the cathode structure is covered with the photoresist 04.
Step three, performing SAB etching on the wafer, wherein the etching is not performed because the area of the cathode structure is covered by photoresist;
in the third step of the present embodiment, the SAB etching is performed on the area of the anode structure of the wafer.
As shown in fig. 2, in the third step, SAB (metal silicide blocking layer) etching is performed on the wafer, wherein no etching is performed because the area of the cathode structure is covered by the photoresist 04; since the region of the anode structure is developed, SAB etching is performed on the region of the anode structure of the wafer.
Step four, removing the photoresist on the cathode structure, and then removing an oxide layer in the etched area of the wafer SAB;
in the fourth step of the present embodiment, the oxide layer is removed by wet etching.
As shown in fig. 3, in the fourth step, photoresist on the cathode structure is removed, and then an oxide layer is removed from the etched area of the wafer SAB; and removing the oxide layer by wet etching. That is, the oxide layer on the area of the wafer except the cathode structure is removed by wet etching.
And fifthly, forming metal silicide on the anode structure. As shown in fig. 4, in this step five, a metal silicide is formed on the anode structure. So that regions on the cathode structure are not silicided.
The length of the cathode structure of the Efuse is 0.1-0.3 mu m; the width is 0.5-0.7 mu m.
Further, the programming voltage of the Efuse of the embodiment is 2.3-3.0V; the programming time is 8-15 mu s.
The length of the Efuse contact hole in the embodiment is 0.5-0.8 mu m; the width is 0.5-0.8 mu m.
In summary, the present invention utilizes the existing process SAB silicon nitride to protect the Efuse cathode, so that the cathode forms a metal-free silicide (non-silicide) structure in the subsequent process, thereby remarkably improving the uniformity of the resistance value after Efuse programming and greatly improving the yield of Efuse. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A method of improving uniformity of an Efuse, comprising at least:
step one, providing a wafer, wherein the wafer comprises an anode structure for forming an Efuse anode and a cathode structure for forming an Efuse cathode; the cathode structure is covered with an oxide layer and a SiN layer formed on the oxide layer;
spin coating photoresist on the wafer, and exposing and developing; wherein regions of the cathode structure are not developed;
step three, performing SAB etching on the wafer, wherein the etching is not performed because the area of the cathode structure is covered by photoresist;
step four, removing the photoresist on the cathode structure, and then removing an oxide layer in the etched area of the wafer SAB;
and fifthly, forming metal silicide on the anode structure.
2. The method of improving uniformity of an Efuse of claim 1, wherein: the cathode structure in the first step comprises a gate structure, wherein the gate structure comprises a polysilicon structure and a side wall attached to the side wall of the polysilicon structure.
3. The method of improving uniformity of an Efuse of claim 1, wherein: in the second step, the area of the anode structure is developed.
4. The method of improving uniformity of an Efuse of claim 1, wherein: and thirdly, carrying out SAB etching on the area of the anode structure of the wafer.
5. The method of improving uniformity of an Efuse of claim 1, wherein: and step four, removing the oxide layer by wet etching.
6. The method of improving uniformity of an Efuse of claim 1, wherein: the length of the cathode structure of the Efuse is 0.1-0.3 mu m; the width is 0.5-0.7 mu m.
7. The method of improving uniformity of an Efuse of claim 1, wherein: the programming voltage of the Efuse is 2.3-3.0V; the programming time is 8-15 mu s.
8. The method of improving uniformity of an Efuse of claim 1, wherein: the length of the Efuse contact hole is 0.5-0.8 mu m; the width is 0.5-0.8 mu m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597792.0A CN117712087A (en) | 2023-11-27 | 2023-11-27 | Method for improving uniformity of Efuse |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311597792.0A CN117712087A (en) | 2023-11-27 | 2023-11-27 | Method for improving uniformity of Efuse |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117712087A true CN117712087A (en) | 2024-03-15 |
Family
ID=90150582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311597792.0A Pending CN117712087A (en) | 2023-11-27 | 2023-11-27 | Method for improving uniformity of Efuse |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117712087A (en) |
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2023
- 2023-11-27 CN CN202311597792.0A patent/CN117712087A/en active Pending
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