CN117709245A - Test code transcoding system and method, test device and chip test method - Google Patents

Abstract

The invention provides a test code transcoding system, comprising: the transcoding unit is used for converting hexadecimal input information into binary data streams, the input information comprises HEX data and a host read/write request, and the data streams comprise HEX data streams and read/write request data streams; the communication instruction decoding unit is connected with the output end of the transcoding unit and is used for converting the HEX data stream and the read/write request data stream into communication instructions according to a communication protocol; the analysis unit is connected with the output end of the communication instruction decoding unit and is used for generating at least a starting position mark and an ending position mark in the communication instruction so as to obtain a complete communication instruction; the link unit is connected with the output end of the analysis unit and is used for converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine. The test code transcoding system provided by the invention solves the problems of easy error, low efficiency, poor flexibility and redundant test codes caused by manual transcoding of a test engineer in the prior art.

Description

Test code transcoding system and method, test device and chip test method

Technical Field

The present invention relates to the field of chip testing technologies, and in particular, to a test code transcoding system and method, a test device, and a chip testing method.

Background

With the rapid development of the integrated circuit industry, the number of transistors integrated on a chip is increased, and functions which can be realized are also increased, so that in order to enable customers to have better chip use experience, the stability of the chip must be ensured, and the chip functions are realized according to design expectations; this requires extensive testing before the chip is provided to the customer, which also makes testing a significant segment.

At present, the test flow of the chip is as follows: entering a test mode, the test machine can identify test codes, configure related function registers through a communication PAD (such as I2C, SPI and the like), and observe whether each function is correct through an output PAD. In the process of RTL simulation verification, a simulation waveform in the fsdb format is generated, and a design engineer generates a test code by sampling a communication PAD and outputting a signal waveform of the PAD; however, the test bench cannot be directly identified, and a test engineer is required to manually perform transcoding to obtain the test code identifiable by the test bench, and based on the test code, the test of the chip is completed.

Because the design engineer, the test engineer and the system engineer of the chip are relatively independent, the test code generated by the design engineer through sampling the signal waveform cannot be directly used by the test engineer; the test engineer needs to transcode the test code into a test code recognizable by the test machine. However, the converted test code may not pass during the chip test, which may be caused by the error of the instruction in the test code caused by the hand error during the transcoding process, in this case, the test engineer and the design engineer have to re-analyze the test code, and the error correction process takes a lot of time, which greatly reduces the efficiency of the chip test.

Moreover, during testing, if the test method is slightly changed, the design engineer is required to resample the signal waveform, with little flexibility. Particularly, for some test items, such as memory self-built automatic test (memory self-built automatic test) and mtp self-built automatic test (multiple programming self-built automatic test), as the hardware has designed the self-test process, the test code only needs to enter the test item, and the rest needs to wait for the corresponding test completion time, and finally judge whether the test passes or not through the test completion port; however, if the test code is generated by sampling the signal waveform, the time waiting for the test to be completed is also sampled, which results in a very long test code, which is not easy to run and read for analysis.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a system and a method for transcoding test codes, a testing device and a chip testing method, which are used for solving the problems of easy error, low efficiency, poor flexibility and redundant test codes caused by manual transcoding by a test engineer in the prior art.

To achieve the above and other related objects, the present invention provides a test code transcoding system, comprising at least: the device comprises a transcoding unit, a communication instruction decoding unit, an analyzing unit and a linking unit;

the transcoding unit is used for converting hexadecimal input information into binary data streams, wherein the input information at least comprises HEX data and a host read/write request, and the data streams at least comprise HEX data streams and read/write request data streams;

the communication instruction decoding unit is connected with the output end of the transcoding unit and is used for converting the HEX data stream and the read/write request data stream into communication instructions according to a communication protocol;

the analysis unit is connected with the output end of the communication instruction decoding unit and is used for generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

the link unit is connected with the output end of the analysis unit and is used for converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

Optionally, the test code transcoding system further comprises: an arbitration unit, a delay instruction decoding unit and a combination unit;

the input end of the arbitration unit is connected with the output end of the transcoding unit, the output end of the arbitration unit is connected with the input ends of the communication instruction decoding unit and the delay instruction decoding unit, and the arbitration unit is used for classifying the HEX data stream and the read/write request data stream into communication information and outputting the communication information to the communication instruction decoding unit, classifying the delay data stream and/or the circulation data stream into delay information and outputting the delay information to the delay instruction decoding unit;

the delay instruction decoding unit is connected with the output end of the arbitration unit and is used for converting the delay data stream into a delay instruction according to the communication protocol and/or converting the circulating data stream into a circulating instruction according to the communication protocol;

the input end of the combined unit is connected with the output ends of the analysis unit and the delay instruction decoding unit, and the output end of the combined unit is connected with the input end of the link unit and is used for integrating the complete communication instruction and the delay instruction and/or the circulation instruction into a test instruction;

the link unit is used for converting the test instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

Optionally, the test code transcoding system further comprises: and the storage unit is connected with the output end of the link unit and used for storing the test codes.

Optionally, the parsing unit is further configured to generate an address/data information label in the communication instruction.

The invention also provides a testing device, which at least comprises: the test machine, wherein the test machine is configured with the test code transcoding system according to any one of the above.

The invention also provides a test code transcoding method, which comprises the following steps:

converting hexadecimal input information into a binary data stream, wherein the input information at least comprises HEX data and a host read/write request, and the data stream at least comprises HEX data stream and a read/write request data stream;

converting the HEX data stream and the read/write request data stream into communication instructions according to a communication protocol;

generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

and converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

The invention also provides a test code transcoding method, which comprises the following steps:

converting hexadecimal input information into a binary data stream, wherein the input information at least comprises HEX data, a host read/write request and time-related data, and the data stream at least comprises HEX data stream, read/write request data stream and time-related data stream;

classifying the HEX data stream and the read/write request data stream as communication information, and classifying the time-dependent data stream as delay information;

converting the HEX data stream and the read/write request data stream classified as communication information into communication instructions according to a communication protocol, and converting the time-related data stream classified as delay information into time-related instructions;

generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

integrating the complete communication instruction and the time related instruction into a test instruction;

converting the test instruction into a test code which can be identified by the test machine according to the format standard of the test machine;

wherein the time-dependent data comprises delay data and/or cycle data, the time-dependent data stream comprises delay data stream and/or cycle data stream, and the time-dependent instructions comprise delay instructions and/or cycle instructions.

Optionally, the test code transcoding method further includes: and storing the test code.

Optionally, the method for obtaining the complete communication instruction includes: and generating a starting position mark, an ending position mark and an address/data information mark in the communication instruction to obtain the complete communication instruction.

The invention also provides a chip testing method based on the testing machine, which comprises the following steps:

obtaining test codes by using the test code transcoding method according to any one of the above claims;

inputting a test instruction through a test machine to control a chip to be tested to enter a corresponding test mode;

and carrying out corresponding function test on the chip to be tested based on the test code, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.

The invention also provides a chip testing method based on the testing machine, which comprises the following steps:

obtaining and storing corresponding test codes by using the test code transcoding method;

inputting a test instruction through a test machine to control a chip to be tested to enter a corresponding test mode;

and calling a corresponding test code to perform corresponding function test on the chip to be tested, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.

As described above, the test code transcoding system and method, the test device and the chip test method can automatically generate the test code which can be identified by the test machine during the chip code level simulation verification, the manual transcoding is not needed, the accuracy of the test code is improved, the time spent on the test code in the later test process is reduced, the efficiency of chip test is improved, and the test cost is saved; when the testing machine is changed, a new identifiable testing code of the testing machine can be generated only by updating the format standard; when the testing method is changed, the chip is not required to be subjected to simulation verification again, and the corresponding testing code can be obtained only by updating the input information; the device has the advantages of strong flexibility and high test efficiency. And the length of the test code is optimized through the design of time delay and circulation, so that the test code is simplified and easy to read. In addition, because the test instruction can be generated in the process of automatically generating the identifiable test code of the test machine, the test instruction can be directly provided for system testers to perform chip function verification in the later period, the accuracy of the test instruction is improved, and the system test time is saved.

Drawings

Fig. 1 is a schematic diagram of a test code transcoding system according to a first embodiment of the present invention.

Fig. 2 is a flowchart of a test code transcoding method according to a first embodiment of the present invention.

Fig. 3 is a schematic diagram of a test code transcoding system according to a second embodiment of the present invention.

Fig. 4 is a flowchart of a test code transcoding method according to a second embodiment of the present invention.

Description of element reference numerals

100. Test code transcoding system

101. Transcoding unit

102. Arbitration unit

103. Communication instruction decoding unit

104. Delay instruction decoding unit

105. Analysis unit

106. Combined unit

107. Linking unit

108. Memory cell

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, the present embodiment provides a test code transcoding system 100, where the test code transcoding system 100 at least includes: transcoding unit 101, communication instruction decoding unit 103, parsing unit 105, and linking unit 107; further, the test code transcoding system 100 further comprises: a storage unit 108.

The transcoding unit 101 is configured to convert hexadecimal input information into a binary data stream and output the binary data stream, where the input information includes at least HEX data and a host read/write request, and the data stream includes at least the HEX data stream and the read/write request data stream.

Specifically, the host read/write request includes a host read request or a host write request; when the host read/write request is a host read request, the format of the HEX data is { slave address, register address, read start flag, read instruction }; when the host read/write request is a host write request, the format of HEX data is { Slave address, register address, data to be written }; of course, other HEX data formats suitable for reading or writing are equally applicable to the present embodiment, which has no substantial impact on the present embodiment.

The communication command decoding unit 103 is connected to the output end of the transcoding unit 101, and is configured to convert the HEX data stream and the read/write request data stream into at least one communication command according to a communication protocol and output the at least one communication command. The communication protocol is determined by the type of the communication port of the chip, and when the chip is designed, the type of the communication port is determined, such as an I2C communication port, an SPI communication port, and the like, and corresponds to the I2C communication protocol, the SPI communication protocol, and the like.

The parsing unit 105 is connected to the output end of the communication command decoding unit 103, and is configured to generate at least a start position flag and an end position flag in the communication command to obtain a complete communication command and output the complete communication command. By generating a corresponding start position mark and an end position mark before and after each communication instruction, a subsequent execution subject can distinguish when the corresponding communication instruction starts and ends based on the corresponding start position mark and the corresponding end position mark.

Further, the parsing unit 105 is further configured to generate an address/data information label in the communication command, so as to label and explain the address and/or data related in the communication command, so that the test engineer can more intuitively understand the communication command.

The link unit 107 is connected to the output end of the parsing unit 105, and is configured to convert the complete communication instruction into a test code identifiable by the test machine according to the format standard of the test machine, and output the test code.

Specifically, the test machine itself has a format standard library, and the link unit 107 compares the complete communication instruction with the format standard library of the test machine, and modifies the non-compliant portion thereof according to the standard format in the format standard library, so as to obtain the test code identifiable by the test machine.

The storage unit 108 is connected to the output end of the linking unit 107, and is used for storing the test code. Storing the test code is not only convenient for engineers to check, but also more importantly, the test code can be directly called during subsequent chip testing without regenerating the test code, which greatly improves the efficiency of chip testing.

In practical application, the test code transcoding system 100 can be used alone, for example, when a design engineer performs chip-level simulation verification, the test code transcoding system 100 can be used to obtain a plurality of test codes of the same chip for different functions and provide the test codes to a test engineer, and when the test engineer tests a certain function of the chip, the test engineer can input the corresponding test codes into a test machine to configure related function registers in the chip to complete the test.

Of course, the test code transcoding system 100 may also be directly placed in the test machine, and in this case, the present embodiment further provides a test device, where the test device at least includes: the test machine is provided with the test code transcoding system 100 described above. For the situation that the test code transcoding system 100 is placed in the test machine, the design engineer only needs to provide a plurality of input information for the test engineer when the same chip tests different functions, and the test engineer can directly call the test code transcoding system 100 to obtain corresponding test codes when testing a certain function of the chip, so as to configure related function registers in the chip to complete the test.

As shown in fig. 2, the present embodiment further provides a test code transcoding method, where the test code transcoding method includes: step 11), step 12), step 13) and step 14); further, the test code transcoding method further comprises the following steps: step 15).

Step 11) converting hexadecimal input information into a binary data stream, wherein the input information at least comprises HEX data and a host read/write request, and the data stream at least comprises HEX data stream and a read/write request data stream. It should be noted that any hexadecimal-to-binary information conversion method is applicable to the present embodiment, and is not limited thereto.

Step 12) converting the HEX data stream and the read/write request data stream into at least one communication instruction according to a communication protocol; the communication protocol may be an I2C communication protocol, an SPI communication protocol, etc.

Step 13) generating at least a start position mark and an end position mark in the communication instruction to obtain a complete communication instruction, so that a subsequent execution subject can distinguish when each communication instruction starts and ends based on the complete communication instruction.

Specifically, the method for obtaining the complete communication instruction comprises the following steps: and generating a starting position mark, an ending position mark and an address/data information mark in the communication instruction to obtain the complete communication instruction. The address/data information label is generated in the communication instruction, and the address and/or data related in the communication instruction are labeled and described, so that a test engineer can more intuitively know the communication instruction.

Step 14) converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

Specifically, the method for obtaining the test code comprises the following steps: providing a format standard library of the test machine, comparing the complete communication instruction with the format standard library of the test machine, and modifying the non-compliant part of the complete communication instruction according to the standard format in the format standard library so as to obtain the test code which can be identified by the test machine.

Step 15) storing the test code. Storing the test code is not only convenient for engineers to check, but also more importantly, the test code can be directly called during subsequent chip testing without regenerating the test code, which greatly improves the efficiency of chip testing.

Correspondingly, the embodiment also provides a chip testing method based on the testing machine, which comprises the following steps: step 21), step 22) and step 23).

Step 21) obtaining test codes by using the test code transcoding method described above.

Step 22), inputting a test instruction through a test machine to control the chip to be tested to enter a corresponding test mode.

Step 23) carrying out corresponding function test on the chip to be tested based on the test code, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.

It should be noted that, step 21) may be performed in the test machine, or may be performed outside the test machine; when the test code is executed outside the test machine, the obtained test code is input into the test machine after the test code is obtained. In step 22), when testing is performed for different functions of the same chip, the test modes corresponding to the different functions are different, and the corresponding input test instructions are also different.

When the test code transcoding method further comprises the step 15), the chip test method can be optimized in order to improve the efficiency of chip test; at this time, the chip test method includes: step 31), step 32) and step 33).

Step 31) obtaining and storing the corresponding test codes by using the test code transcoding method described above, for example, storing a plurality of test codes of the same chip for testing different functions.

Step 32) inputting a test instruction through a test machine to control the chip to be tested to enter a corresponding test mode.

Step 33) invoking the corresponding test code to perform corresponding function test on the chip to be tested, and judging whether the corresponding function of the chip to be tested reaches the design expectation according to the test result.

Aiming at different functional tests of the same chip or the same functional test of the same batch of chips, the test codes are stored in advance, so that the step 32) and the step 33) are only needed to be executed in the actual test process; because the test code does not need to be regenerated, the efficiency of chip test can be greatly improved.

It should be noted that, step 31) may be performed in the test machine, or may be performed outside the test machine; when the test code is executed outside the test machine, the obtained test code is input into the test machine after the test code is obtained. In step 32), when testing is performed for different functions of the same chip, the test modes corresponding to the different functions are different, and the corresponding input test instructions are also different.

Example two

As shown in fig. 3, the present embodiment provides a test code transcoding system 100, the test code transcoding system 100 comprising: transcoding unit 101, arbitration unit 102, communication instruction decoding unit 103, delay instruction decoding unit 104, parsing unit 105, combining unit 106, and linking unit 107; further, the test code transcoding system 100 further comprises: a storage unit 108.

Compared with the first embodiment, in this embodiment, by adding the arbitration unit 102, the delay instruction decoding unit 104 and the combining unit 106 to the test code transcoding system 100, not only can delay be added to the instruction, but also the same test instruction can be represented by a loop, so that the length of the test code is greatly reduced, and the test code is simplified and readable.

The transcoding unit 101 is configured to convert hexadecimal input information into a binary data stream and output the binary data stream, where the input information includes delay data and/or cyclic data in addition to the HEX data and the host read/write request, and the data stream includes delay data and/or cyclic data in addition to the HEX data and the read/write request.

Specifically, the host read/write request includes a host read request or a host write request; when the host read/write request is a host read request, the format of the HEX data is { slave address, register address, read start flag, read instruction }; when the host read/write request is a host write request, the format of HEX data is { Slave address, register address, data to be written }; of course, other HEX data formats suitable for reading or writing are equally applicable to the present embodiment, which has no substantial impact on the present embodiment. In addition, the data format of the delay data is { delay flag, delay time }, and the data format of the cycle data is { cycle flag, cycle number }.

The arbitration unit 102 is connected to the output end of the transcoding unit 101, and is configured to classify the HEX data stream and the read/write request data stream into communication information and output the communication information to the communication instruction decoding unit 103, and classify the delayed data stream and/or the cyclic data stream into delay information and output the delay information to the delay instruction decoding unit 104.

Specifically, the arbitration unit 102 classifies each data stream using a unique data type flag, such as a data type flag of a host read request is. RD, a data type flag of a host write request is. WR, etc.

The communication command decoding unit 103 is connected to the output end of the arbitration unit 102, and is configured to convert the HEX data stream and the read/write request data stream classified as communication information into at least one communication command according to a communication protocol and output the at least one communication command. The communication protocol is determined by the type of the communication port of the chip, and when the chip is designed, the type of the communication port is determined, such as an I2C communication port, an SPI communication port, and the like, and corresponds to the I2C communication protocol, the SPI communication protocol, and the like.

The delay instruction decoding unit 104 is connected to the output end of the arbitration unit 102, and is configured to convert the delay data stream classified as delay information into at least one delay instruction according to the communication protocol and output the at least one delay instruction, and/or convert the cyclic data stream classified as delay information into at least one cyclic instruction according to the communication protocol and output the at least one cyclic instruction.

The parsing unit 105 is connected to the output end of the communication command decoding unit 103, and is configured to generate at least a start position flag and an end position flag in the communication command to obtain a complete communication command and output the complete communication command. By generating a corresponding start position mark and an end position mark before and after each communication instruction, a subsequent execution subject can distinguish when the corresponding communication instruction starts and ends based on the corresponding start position mark and the corresponding end position mark.

Further, the parsing unit 105 is further configured to generate an address/data information label in the communication command, so as to label and explain the address and/or data related in the communication command, so that the test engineer can more intuitively understand the communication command.

The combination unit 106 is connected to the output end of the parsing unit and the output end of the delay instruction decoding unit, and is configured to integrate the complete communication instruction with the delay instruction and/or the circulation instruction into a test instruction and output the test instruction, that is, insert the delay instruction and/or the circulation instruction into a corresponding communication instruction in the complete communication instruction to obtain the test instruction and output the test instruction.

The linking unit 107 is connected to the output end of the combining unit 106, and is configured to convert the test instruction into a test code identifiable by the test machine according to the format standard of the test machine, and output the test code.

Specifically, the test machine itself has a format standard library, and the link unit 107 compares the test instruction with the format standard library of the test machine, and modifies the non-compliant portion thereof according to the standard format in the format standard library, so as to obtain the test code identifiable by the test machine.

The storage unit 108 is connected to the output end of the linking unit 107, and is used for storing the test code. Storing the test code is not only convenient for engineers to check, but also more importantly, the test code can be directly called during subsequent chip testing without regenerating the test code, which greatly improves the efficiency of chip testing.

It should be noted that, the test code transcoding system 100 of the present embodiment is applicable to not only the instruction with increased delay and/or cycle, but also the instruction without increased delay and cycle, where the arbitration unit 102 simply classifies the HEX data stream and the read/write request data stream into communication information and outputs the communication information to the communication instruction decoding unit 103, the delay instruction decoding unit 104 does not generate the delay instruction and/or cycle instruction, and the combination unit 106 outputs the complete communication instruction to the link unit 107, which is equivalent to the test code transcoding system 100 of the first embodiment.

In practical application, the test code transcoding system 100 can be used alone, for example, when a design engineer performs chip-level simulation verification, the test code transcoding system 100 can be used to obtain a plurality of test codes of the same chip for different functions and provide the test codes to the test engineer, and when the test engineer tests a certain function of the chip, the test engineer can input the corresponding test codes into a test machine to configure related function registers in the chip to complete the test.

Of course, the test code transcoding system 100 may also be directly placed in the test machine, and in this case, the present embodiment further provides a test device, where the test device at least includes: the test machine is provided with the test code transcoding system 100 described above. For the situation that the test code transcoding system 100 is placed in the test machine, the design engineer only needs to provide a plurality of input information for the test engineer when the same chip tests different functions, and the test engineer can directly call the test code transcoding system 100 to obtain corresponding test codes when testing a certain function of the chip, so as to configure related function registers in the chip to complete the test.

As shown in fig. 4, the present embodiment further provides a test code transcoding method, where the test code transcoding method includes: step 11), step 12), step 13), step 14), step 15), step 16); further, the test code transcoding method further comprises the following steps: step 17).

Step 11) converting hexadecimal input information into binary data streams, wherein the input information at least comprises HEX data, a host read/write request and time-related data, and the data streams at least comprise HEX data streams, read/write request data streams and time-related data streams; wherein the time-dependent data comprises delay data and/or cyclic data and the time-dependent data stream comprises delay data stream and/or cyclic data stream. It should be noted that any hexadecimal-to-binary information conversion method is applicable to the present embodiment, and is not limited thereto.

Step 12) categorizes the HEX data stream and the read/write request data stream as communication information and the time-dependent data stream as delay information. Because different data have different data type flags, such as the data type flag of the host read request is.RD, the data type flag of the host write request is.WR, etc., the data type flags can be directly utilized to categorize each data stream.

Step 13) converting HEX data stream and read/write request data stream classified into communication information into at least one communication instruction according to a communication protocol, and converting time-related data stream classified into delay information into at least one time-related instruction; the time related instruction includes a delay instruction and/or a circulation instruction, and the communication protocol may be an I2C communication protocol, an SPI communication protocol, or the like.

Step 14) generating at least a start position mark and an end position mark in the communication instruction to obtain a complete communication instruction, so that a subsequent execution subject can distinguish when each communication instruction starts and ends based on the complete communication instruction.

Specifically, the method for obtaining the complete communication instruction comprises the following steps: and generating a starting position mark, an ending position mark and an address/data information mark in the communication instruction to obtain the complete communication instruction. The address/data information label is generated in the communication instruction, and the address and/or data related in the communication instruction are labeled and described, so that a test engineer can more intuitively know the communication instruction.

Step 15) integrating the complete communication instruction and the time dependent instruction into a test instruction, i.e. inserting the delay instruction and/or the loop instruction into the corresponding communication instruction in the complete communication instruction to obtain the test instruction.

Step 16) converting the test instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

Specifically, the method for obtaining the test code comprises the following steps: providing a format standard library of the test machine, comparing the test instruction with the format standard library of the test machine, and modifying the non-compliant part of the test instruction according to the standard format in the format standard library so as to obtain the test code which can be identified by the test machine.

Step 17) storing the test code. Storing the test code is not only convenient for engineers to check, but also more importantly, the test code can be directly called during subsequent chip testing without regenerating the test code, which greatly improves the efficiency of chip testing.

Correspondingly, the embodiment also provides a chip testing method based on the testing machine, which comprises the following steps: step 21), step 22) and step 23).

Step 21) obtaining test codes by using the test code transcoding method described above.

Step 22), inputting a test instruction through a test machine to control the chip to be tested to enter a corresponding test mode.

Step 23) carrying out corresponding function test on the chip to be tested based on the test code, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.

It should be noted that, step 21) may be performed in the test machine, or may be performed outside the test machine; when the test code is executed outside the test machine, the obtained test code is input into the test machine after the test code is obtained. In step 22), when testing is performed for different functions of the same chip, the test modes corresponding to the different functions are different, and the corresponding input test instructions are also different.

When the test code transcoding method further comprises the step 17), the chip test method can be optimized in order to improve the efficiency of chip test; at this time, the chip test method includes: step 31), step 32) and step 33).

Step 31) obtaining and storing the corresponding test codes by using the test code transcoding method described above, for example, storing a plurality of test codes of the same chip for testing different functions.

Step 32) inputting a test instruction through a test machine to control the chip to be tested to enter a corresponding test mode.

Step 33) invoking the corresponding test code to perform corresponding function test on the chip to be tested, and judging whether the corresponding function of the chip to be tested reaches the design expectation according to the test result.

Aiming at different functional tests of the same chip or the same functional test of the same batch of chips, the test codes are stored in advance, so that the step 32) and the step 33) are only needed to be executed in the actual test process; because the test code does not need to be regenerated, the efficiency of chip test can be greatly improved.

It should be noted that, step 31) may be performed in the test machine, or may be performed outside the test machine; when the test code is executed outside the test machine, the obtained test code is input into the test machine after the test code is obtained. In step 32), when testing is performed for different functions of the same chip, the test modes corresponding to the different functions are different, and the corresponding input test instructions are also different.

In summary, the test code transcoding system and method, the test device and the chip test method can automatically generate the test code which can be identified by the test machine during chip code level simulation verification, do not need manual transcoding, improve the accuracy of the test code, reduce the time spent on the test code in the later test process, improve the efficiency of chip test and save the test cost; when the testing machine is changed, a new identifiable testing code of the testing machine can be generated only by updating the format standard; when the testing method is changed, the chip is not required to be subjected to simulation verification again, and the corresponding testing code can be obtained only by updating the input information; the device has the advantages of strong flexibility and high test efficiency. And the length of the test code is optimized through the design of time delay and circulation, so that the test code is simplified and easy to read. In addition, because the test instruction can be generated in the process of automatically generating the identifiable test code of the test machine, the test instruction can be directly provided for system testers to perform chip function verification in the later period, the accuracy of the test instruction is improved, and the system test time is saved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (11)

1. A test code transcoding system, said test code transcoding system comprising at least: the device comprises a transcoding unit, a communication instruction decoding unit, an analyzing unit and a linking unit;

the transcoding unit is used for converting hexadecimal input information into binary data streams, wherein the input information at least comprises HEX data and a host read/write request, and the data streams at least comprise HEX data streams and read/write request data streams;

the communication instruction decoding unit is connected with the output end of the transcoding unit and is used for converting the HEX data stream and the read/write request data stream into communication instructions according to a communication protocol;

the analysis unit is connected with the output end of the communication instruction decoding unit and is used for generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

the link unit is connected with the output end of the analysis unit and is used for converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

2. The test code transcoding system of claim 1, further comprising: an arbitration unit, a delay instruction decoding unit and a combination unit;

the input end of the arbitration unit is connected with the output end of the transcoding unit, the output end of the arbitration unit is connected with the input ends of the communication instruction decoding unit and the delay instruction decoding unit, and the arbitration unit is used for classifying the HEX data stream and the read/write request data stream into communication information and outputting the communication information to the communication instruction decoding unit, classifying the delay data stream and/or the circulation data stream into delay information and outputting the delay information to the delay instruction decoding unit;

the delay instruction decoding unit is connected with the output end of the arbitration unit and is used for converting the delay data stream into a delay instruction according to the communication protocol and/or converting the circulating data stream into a circulating instruction according to the communication protocol; the input end of the combined unit is connected with the output ends of the analysis unit and the delay instruction decoding unit, and the output end of the combined unit is connected with the input end of the link unit and is used for integrating the complete communication instruction and the delay instruction and/or the circulation instruction into a test instruction;

the link unit is used for converting the test instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

3. The test code transcoding system of claim 1 or 2, further comprising: and the storage unit is connected with the output end of the link unit and used for storing the test codes.

4. The system of claim 1, wherein the parsing unit is further configured to generate an address/data information tag in the communication instruction.

5. A test device, the test device comprising at least: a test bench, wherein the test bench is configured with the test code transcoding system according to any of claims 1-4.

6. A test code transcoding method, the test code transcoding method comprising:

converting hexadecimal input information into a binary data stream, wherein the input information at least comprises HEX data and a host read/write request, and the data stream at least comprises HEX data stream and a read/write request data stream;

converting the HEX data stream and the read/write request data stream into communication instructions according to a communication protocol;

generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

and converting the complete communication instruction into a test code which can be identified by the test machine according to the format standard of the test machine.

7. A test code transcoding method, the test code transcoding method comprising:

converting hexadecimal input information into a binary data stream, wherein the input information at least comprises HEX data, a host read/write request and time-related data, and the data stream at least comprises HEX data stream, read/write request data stream and time-related data stream;

classifying the HEX data stream and the read/write request data stream as communication information, and classifying the time-dependent data stream as delay information;

converting the HEX data stream and the read/write request data stream classified as communication information into communication instructions according to a communication protocol, and converting the time-related data stream classified as delay information into time-related instructions;

generating at least a starting position mark and an ending position mark in the communication instruction to obtain a complete communication instruction;

integrating the complete communication instruction and the time related instruction into a test instruction;

converting the test instruction into a test code which can be identified by the test machine according to the format standard of the test machine;

wherein the time-dependent data comprises delay data and/or cycle data, the time-dependent data stream comprises delay data stream and/or cycle data stream, and the time-dependent instructions comprise delay instructions and/or cycle instructions.

8. The test code transcoding method according to claim 6 or 7, further comprising: and storing the test code.

9. The method for transcoding test codes according to claim 6 or 7, wherein the method for obtaining the complete communication instruction comprises: and generating a starting position mark, an ending position mark and an address/data information mark in the communication instruction to obtain the complete communication instruction.

10. The chip testing method based on the testing machine is characterized by comprising the following steps of:

obtaining test codes by using the test code transcoding method according to any one of claims 6 to 9;

inputting a test instruction through a test machine to control a chip to be tested to enter a corresponding test mode;

and carrying out corresponding function test on the chip to be tested based on the test code, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.

11. The chip testing method based on the testing machine is characterized by comprising the following steps of:

the corresponding test codes are obtained and stored by using the test code transcoding method as claimed in claim 8 or 9;

inputting a test instruction through a test machine to control a chip to be tested to enter a corresponding test mode;

and calling a corresponding test code to perform corresponding function test on the chip to be tested, and judging whether the corresponding function of the chip to be tested reaches the design expectation or not according to the test result.