CN115656791B

CN115656791B - Test method and test platform for chip testability design

Info

Publication number: CN115656791B
Application number: CN202211701297.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-06-06
Anticipated expiration: 2042-12-29
Also published as: CN115656791A

Abstract

The present disclosure relates to the field of new generation information technology, and provides a method and a platform for testing chip testability design, where the method is applied to the platform and includes: receiving a plurality of test vector fragments and auxiliary information corresponding to an execution file of a test case, wherein different test vector fragments are used for realizing or testing the independent chip functions of a tested chip; testing the tested chip, including controlling the code of the excitation signal corresponding to the test vector segment to be output to the tested chip based on the auxiliary information; acquiring an actual vector value of code output of a chip to be tested; determining a test result according to a comparison result of an expected vector value and an actual vector value included in the test vector segment; the test results are shown through use case execution logs. When the testing method for the design for testability of the chip is applied to the testing platform of the embodiment of the disclosure, the testing of the design for testability DFT can be completed for the chip with large scale before the chip is thrown, so that the testing platform has an enhancement function.

Description

Test method and test platform for chip testability design

Technical Field

The disclosure relates to the field of new generation information technology, and in particular relates to a testing method and a testing platform for chip testability design.

Background

Chip Design for Test (DFT) refers to that various hardware logic for improving chip testability (including controllability and observability) is inserted in the chip original Design stage, and Test vector engine software can generate Test vectors based on the logic, and the Test vectors complete testing on an automatic Test machine, so as to achieve the purpose of testing large-scale chips. If the design for testability DFT itself has some functional problems, resulting in errors in the generated test vectors, when the chip is tested using the test vectors, the time for debugging the test vectors on an Automatic test machine (Automatic TestEquipment, ATE) will be greatly increased, which may affect the reliability of the test results of the chip, increase the cost of chip testing, and even affect the chip functions, resulting in chip flow failure. Therefore, the testing of the design for chip testability DFT is a very important step after the chip is manufactured, and the testing needs to be completed before the chip is put into the chip.

The current mainstream technology is to test the design for chip testability DFT through a software Simulation platform (e.g., simulation). However, with the development of integrated circuits, the scale of the chip is larger and larger, and as the software simulation platform is not good at large-scale chips, the software simulation platform breaks through the front part in the aspects of chip scale and test time, forms an obvious bottleneck, and provides a great challenge for testing the design for testability DFT of the chip before the chip is put into the chip.

Therefore, for chips with larger scale, how to complete the test of design for testability DFT before the chip is put into a chip becomes a research hotspot in the field.

Disclosure of Invention

In view of this, the disclosure provides a method and a platform for testing design for testability of a chip, and when the method for testing design for testability of a chip of the embodiments of the disclosure is applied to the platform for testing the embodiment of the disclosure, the method can complete testing of design for testability DFT of a large-scale chip before the chip is diced, so that the platform for testing has an enhancement function.

According to an aspect of the present disclosure, there is provided a method for testing a chip testability design, the method being applied to a test platform, the method comprising: receiving a plurality of test vector fragments and auxiliary information corresponding to an execution file of a test case, wherein the test vector fragments are fragments identifiable by the test platform, different test vector fragments are used for realizing or testing the independent chip function of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip; testing the tested chip, comprising: based on the auxiliary information, code for controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the plurality of test vector fragments indicate whether the chip functions corresponding to the plurality of test vector fragments are normal or not, and the test results are displayed through an instance execution log.

In one possible implementation manner, the code for controlling the excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information includes: and outputting the excitation signal to the code input interface of the tested chip at the time point indicated by the test period driving parameter in the auxiliary information, and outputting the actual vector value by the code output interface of the tested chip.

In one possible implementation manner, the determining a test result according to a comparison result of an expected vector value included in the test vector segment and the actual vector value includes: when the expected vector value indication included in the test vector segment is compared, whether the expected vector value in the test vector segment is matched with the actual vector value output by the chip pin at the time point indicated by the test period comparison parameter or not is compared; when the comparison result is that the actual vector value and the expected vector value at the time point are not matched, error information is recorded, wherein the error information comprises a test period corresponding to the time point, the actual vector value and the expected vector value at the time point; and determining a test result according to the error information.

In one possible implementation, the test platform is adapted to a software simulation platform and a hardware simulation platform.

According to another aspect of the present disclosure, there is provided a method for generating a test platform, the method including: analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, wherein the plurality of original vector segments are obtained by splitting a plurality of second test vectors, and different original vector segments are used for realizing or testing the independent chip functions of the tested chip, and the second test vectors are original test vectors; analyzing the test vector analysis data corresponding to each original vector segment, and identifying and obtaining the public information of the second test vectors; and generating a test platform according to the public information, wherein the storage space of the test platform is related to the original vector segment with the largest length.

In one possible implementation, the common information includes one or more of a chip pin parameter, a time parameter, and a test cycle time definition of the chip under test.

In one possible implementation, the method further includes: generating a test vector segment corresponding to each original vector segment according to the test vector analysis data corresponding to the original vector segment, wherein the test vector segment is a segment identifiable by the test platform, and is used when the test platform tests the independent chip function of the tested chip.

In one possible implementation, the chip under test includes at least one subsystem, each subsystem including at least one module, and the splitting condition of the plurality of second test vectors includes: for the part of the second test vectors, which is related to the initializing function of the tested chip, a first original vector segment is obtained, wherein the first original vector segment corresponds to each subsystem and each module; obtaining at least one second original vector segment for a part, related to an initializing function, of at least one subsystem of the tested chip, of a plurality of second test vectors, wherein each second original vector segment corresponds to one subsystem; for the part of each second test vector related to the function of at least one module of the tested chip, at least one third initial vector segment is obtained, wherein each third initial vector segment corresponds to at least one module or function belonging to the same subsystem, and the degree of association between a plurality of modules corresponding to the same third initial vector segment is greater than a first threshold.

In one possible implementation, the method further includes: generating at least one execution file according to the plurality of test vector fragments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test case is executed, the plurality of test vector fragments and auxiliary information corresponding to the execution file of the test case are sequentially input to the test platform.

In one possible implementation, the test vector segments of the single execution file are generated, including test vector segments corresponding to the first original vector segment, the second original vector segment, and the third original vector segment, and the combining condition includes at least one of: generating test vector segments of a single execution file and combining the test vector segments according to a preset sequence; generating a test vector segment of a single execution file corresponding to a preset subsystem; and generating test vector fragments of the single execution file, wherein the total number of the test vector fragments corresponding to the third initial vector fragment is larger than or equal to the second threshold value and smaller than or equal to the third threshold value.

In one possible implementation manner, the auxiliary information includes guiding information for controlling the test platform to test the tested chip and difference information of each second test vector.

In one possible implementation, the test vector segment includes expected vector values and stimulus vector values for the unidirectional pins and expected/stimulus vector values for the bidirectional pins of the chip under test for each test period under the test vector segment.

In one possible implementation, the plurality of second test vectors includes test vectors written in different languages, including at least one of a standard test interface language STIL, a waveform generation language WGL, and a test description language TDL.

According to another aspect of the present disclosure, there is provided a test platform comprising: the receiving module is used for receiving a plurality of test vector fragments and auxiliary information corresponding to the execution file of the test case, wherein the test vector fragments are fragments identifiable by the test platform, different test vector fragments are used for realizing or testing the independent chip function of the tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip; the test module is used for testing the tested chip and comprises the following components: based on the auxiliary information, code for controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the plurality of test vector fragments indicate whether the chip functions corresponding to the plurality of test vector fragments are normal or not, and the test results are displayed through an instance execution log.

According to another aspect of the present disclosure, there is provided a generating device of a test platform, including: the first analysis module is used for analyzing a plurality of original vector fragments to obtain test vector analysis data corresponding to each original vector fragment, the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, different original vector fragments are used for realizing or testing the independent chip functions of the tested chip, and the second test vectors are original test vectors; the second analysis module is used for analyzing the test vector analysis data corresponding to each original vector segment and identifying and obtaining the public information of the plurality of second test vectors; and the first generation module is used for generating a test platform according to the public information, and the storage space of the test platform is related to the original vector segment with the largest length.

In one possible implementation, the apparatus further includes: the second generation module is used for generating a test vector segment corresponding to each original vector segment according to the test vector analysis data corresponding to the original vector segment, wherein the test vector segment is a segment identifiable by the test platform, and the test vector segment is used when the test platform tests the independent chip function of the tested chip.

In one possible implementation, the apparatus further includes: and the third generation module is used for generating at least one execution file according to the plurality of test vector fragments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test case is executed, the plurality of test vector fragments and auxiliary information corresponding to the execution file of the test case are sequentially input to the test platform.

According to another aspect of the present disclosure, there is provided a test platform comprising: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the test method for the chip testability design when executing the instructions stored in the memory.

According to another aspect of the present disclosure, there is provided a generating device of a test platform, including: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the method for generating the test platform when executing the instructions stored in the memory.

According to another aspect of the present disclosure, there is provided a non-volatile computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement a test method for the above-described chip design for testability, or implement a method for generating the above-described test platform.

According to another aspect of the present disclosure, there is provided a computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs a test method of the above chip testability design, or a generation method of the above test platform.

According to the testing method for the chip testability design, the test vector segments and the auxiliary information corresponding to the execution files of the test cases are received, the test vector segments are identifiable segments of the test platform, and the auxiliary information comprises guiding information for controlling the test platform to test the tested chip, so that the test platform can acquire necessary information for testing the chip testability design; the method comprises the steps of controlling a code output by an excitation signal corresponding to a test vector segment to a tested chip based on auxiliary information, obtaining an actual vector value output by the code of the tested chip, determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment, and completing the test corresponding to a plurality of test vector segments; different test vector segments are used for realizing or testing the functions of the independent chips of the tested chips, so that the functions of the tested chips which can be tested by the test vector segments corresponding to the execution file can be random, and the test has randomness. Based on the test platform of the embodiment of the disclosure, the test method of the chip testability design of the embodiment of the disclosure provides a set of comprehensive test architecture, and can realize accurate positioning to the test vector segment where the test abnormality is located and the corresponding test cycle number. The test results corresponding to the plurality of test vector segments indicate whether the functions of the chips corresponding to the plurality of test vector segments are normal, and the test results can be displayed through the use case execution log, so that the automation of the test flow of the chip testable design is realized. In the test process, any non-universal self-grinding device, equipment and chip peripheral circuits are not needed, so that the unpredictable problem caused by other hardware is avoided, and the test method for the chip testability design of the embodiment of the disclosure is more accurate in test result. The length of the test vector segment can be far smaller than that of the complete test vector, so that the storage space of the test platform can be set smaller, and the data storage pressure of the test platform is reduced.

According to the test platform generating method, the plurality of original vector fragments are obtained through analyzing the test vector analysis data corresponding to each original vector fragment, the plurality of original vector fragments are obtained through splitting a plurality of second test vectors, and the common information of the plurality of second test vectors can be identified and obtained through analyzing the test vector analysis data corresponding to each original vector fragment; a test platform may be generated from the common information. The storage space of the test platform is related to the original vector segment with the largest length, and compared with the storage of complete test vector data, the storage cost of the test platform is greatly reduced; different original vector segments are used for realizing or testing the independent chip functions of the tested chip, so that the independent chip functions of the tested chip can be tested respectively, and the mode of testing the tested chip by the test platform is more flexible. The process of analyzing the second test vector to generate the test platform can be automated, so that the energy of a user for constructing a test environment is released; the second test vector is an original test vector, and the analysis of the second test vector does not need to be converted into a specific format, so that the distortion degree of the analysis data of the test vector and the common information compared with the second test vector can be reduced; the test platform generated by the test platform generation method of the embodiment of the disclosure can be used for testing the testability design of the chip, and can ensure the completeness of the test of the testability design of the chip. The test platform does not need a specific self-grinding hardware device and a chip peripheral circuit, has little limitation on data storage of test vectors, logic scale of test chips, pin number, pin driving capability and debugging capability after errors, and has strong universality; and can realize the test before throwing the piece, can find the problem at chip item present period, with less cost, release the chip testability design risk to a greater extent, clear away the test vector problem simultaneously, save the test vector debugging time that consumes because of the test vector problem on automatic test equipment ATE to save automatic test equipment ATE's test overhead, reduce the test cost of chip.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a method flowchart of a method of generating a test platform according to an embodiment of the present disclosure.

Fig. 2 shows a method flowchart of a method of generating a test platform according to an embodiment of the present disclosure.

FIG. 3 illustrates examples of test speeds of a test platform in different modes of use on different simulation platforms, according to an embodiment of the present disclosure.

FIG. 4 illustrates an example of multiple test vector segments resulting from splitting a second test vector according to a split condition of an embodiment of the present disclosure.

FIG. 5 illustrates an example of obtaining an execution file according to an embodiment of the present disclosure.

Fig. 6 illustrates an example of a combined conditional get execution file according to an embodiment of the present disclosure.

Fig. 7 shows a method flow diagram of a test method for chip design for testability according to an embodiment of the disclosure.

Fig. 8 shows a method flow diagram of a test method for chip design for testability according to an embodiment of the disclosure.

Fig. 9 shows a method flow diagram of a test method for chip design for testability according to an embodiment of the disclosure.

Fig. 10 shows a block diagram of a test platform according to an embodiment of the present disclosure.

Fig. 11 shows a block diagram of a generating device of a test platform according to an embodiment of the present disclosure.

Fig. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Several prior art methods for testing chip design for testability are described below.

The first prior art proposes a test system for design for chip testability DFT based on Field programmable gate array (Field-Programmable Gate Array, PFGA). The system comprises a file processing device and an automatic testing platform, wherein the automatic testing platform comprises a hardware base plate and a field programmable gate array (PFGA) subplate: the file processing device can only process the test vectors in the waveform generation language (WaveformGeneration Language, WGL) format, the script converts the test vectors in the waveform generation language WGL format into a synthesizable code file, and the synthesizable code file is programmed on the FPGA daughter board after being subjected to synthesis and other processes; after the FPGA daughter board is powered on and reset and started, input/output (IO) excitation information is sent to a tested chip of the hardware base plate through a slot, and the actual return value output by the tested chip is obtained and then compared with a preset ideal return value to verify the correctness of the test vector in the waveform generation language WGL format.

The method has the following defects: the chip to be tested is required to be arranged on the hardware base plate, so that the test before the chip is thrown cannot be realized; only the test vector of the WGL format of the waveform generation language is oriented, and the test vector written in other languages is not suitable; the system requires custom chip peripheral circuits that introduce unpredictable problems; the method is not applicable to other hardware simulation platforms or software simulation platforms except for a field programmable gate array (PFGA); the field programmable gate array FPGA can limit the data storage of test vectors, the logic scale of the tested chip and the pin number; based on the field programmable gate array FPGA test, the debugging capability of the test vector is very limited.

The scheme of the second prior art provides a chip testability design DFT test method based on a general hardware device or a self-grinding hardware device. Aiming at test vectors in various formats, the method respectively provides a corresponding test vector analysis mode to analyze the test vectors into data which can be processed by general hardware equipment or self-grinding hardware devices; and the test environment of the automatic test equipment ATE is simulated by matching with a control flow, a server or a self-grinding hardware device, so that the test of the design for testability DFT of the chip is realized.

The scheme has the following defects: testing before the tablet throwing cannot be realized; the self-grinding hardware device is strongly related to the hardware simulation platform and cannot be adapted to the software simulation platform; customizing a peripheral circuit of the chip after the streaming is completed; the need for hardware emulation platforms to achieve equivalent performance to automated test equipment ATE, such as true clock frequency, signal integrity, etc., would be a significant challenge for large-scale, multiple-input/output chips.

In the third scheme of the prior art, a method for converting a test vector in a format unrecognizable by an automatic test equipment ATE into a format recognizable by a self-grinding hardware device and then testing by using the self-grinding hardware device is provided. The correctness of the format conversion of the test vector is tested on a self-grinding hardware device.

The scheme has the following defects: testing before the tablet throwing cannot be realized; multiple test vector formats cannot be directly supported, and the converted test vector has certain distortion, so that the accuracy of a test result is reduced.

In summary, the test method for chip testability design in the prior art has the following problems:

1. testing before the tablet throwing cannot be realized; after the back-sheet test, the problem is too late to be found, and the test can not be completely replaced by an Automatic Test Equipment (ATE) test;

2. the platform has poor portability and can not be flexibly switched in a software Simulation platform (such as a Simulation and the like) and a hardware Simulation platform (such as a Simulation and a Field Programmable Gate Array (FPGA) and the like);

3. the hardware device can limit data storage of test vectors, logical scale of test chips, pin number, pin driving capability, debugging capability after errors, especially the self-grinding hardware device can bring additional hardware problems to chip test, and the universality in the industry is poor;

4. after the streaming is completed, customizing a peripheral circuit of the chip, wherein the peripheral circuit can introduce unexpected problems;

5. some existing techniques only support inputting a single test vector format, which is too single; some existing technologies support conversion from multiple test vector formats to one format, but cannot directly support multiple test vector formats, and cannot extract data from an originally input test vector without distortion.

In view of this, the disclosure provides a method and a platform for testing design for testability of a chip, and when the method for testing design for testability of a chip of the embodiments of the disclosure is applied to the platform for testing the embodiment of the disclosure, the method can complete testing of design for testability DFT of a chip with a larger scale before the chip is diced, so that the platform for testing has an enhancement function.

Fig. 1 and 2 illustrate a method flow diagram of a method of generating a test platform according to an embodiment of the present disclosure. As shown in fig. 1, the test platform generating method includes steps S11-S13:

step S11, analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, wherein the plurality of original vector segments are obtained by splitting a plurality of second test vectors, and different original vector segments are used for realizing or testing the independent chip functions of the tested chip, and the second test vectors are original test vectors;

step S12, analyzing the test vector analysis data corresponding to each original vector segment, and identifying to obtain the public information of a plurality of second test vectors;

and S13, generating a test platform according to the public information, wherein the storage space of the test platform is related to the original vector segment with the largest length.

For example, as shown in fig. 2, a "test vector parsing engine" may be provided for executing the test platform generating method of the embodiment of the present disclosure. The user may specify a test vector file set (not shown) comprising a second test vector of a plurality of formats, wherein the second test vector is an original test vector, i.e. a test vector not converted in format, may be a test vector of a different format written or generated using a different tool (programming language), and may be tested against the same chip. A complete second test vector is typically used to test various functions of the chip under test, such as the power-on and initialization functions of the chip, the functions of each module of the chip, and so on. Thus, the second test vectors may be decomposed according to functionality, e.g., a user may specify a split condition, splitting each second test vector into a plurality of separate raw vector segments, such that different raw vector segments are used to test separate chip functions of the chip under test, including chip common initialization functions, subsystem initialization functions, test functions of the whole chip or subsystem or module, and so forth. Examples of splitting conditions may be found in the related description below. Alternatively, the user is also supported to specify a fragment set (not shown) comprising original vector fragments in a plurality of formats, which fragments may be fragments capable of composing a complete plurality of second test vectors. In step S11, by analyzing a plurality of original vector segments, identifying the format of each original vector segment, the effective information of each original vector segment can be extracted, and the effective information is stored in the local database in the form of the test vector analysis data corresponding to each original vector segment for use in the subsequent steps. The extracted information can be data common to test vectors in various formats, such as pins, test cycles, and the like.

Optionally, as shown in fig. 2, a "test vector parser" (software module) may be provided in the "test vector parse engine", and when the second test vector is used as an input of the "test vector parser", the "test vector parser" may perform a splitting step of the second test vector and step S11; with the original vector fragment as input to the "test vector parser", the "test vector parser" may perform step S11. Examples of formats of the second test vector and the original vector fragment may be found in the related description below.

In step S12, by analyzing the test vector analysis data corresponding to the original vector segments of the different second test vectors, a portion of the analysis data of the different second test vectors that is not different may be identified, so as to obtain common information of the plurality of second test vectors. Optionally, as shown in fig. 2, the above-mentioned "test vector parser" may further perform step S12. The difference part of each second test vector and other second test vectors can be used as auxiliary information of the second test vector. The test vector parsing data corresponding to each original vector segment may be stored in correspondence with its corresponding auxiliary information. The auxiliary information is used when testing the chip under test. The second test vector corresponding to the test vector analysis data analyzed in this step may be all or part of the test vector file set, which is not limited in this disclosure. Examples of common information and auxiliary information may be found in the related description below.

After identifying the common information, in step S13, a Test Bench (TB) may be generated from the common information. Optionally, as shown in fig. 2, a "test platform generator" (software module) may be set, and public information is used as input of the "test platform generator", where the "test platform generator" performs secondary comprehensive analysis on the public information, so as to generalize functions that the test platform may have in a manner of analysis test, form each module in the test platform, and determine the size of the storage space of the test platform according to the original vector segment with the largest length, thereby automatically generating the test platform. Alternatively, each module in the test platform may be in a software form that is not synthesizable, or may be in a hardware form that is synthesizable into hardware. The test platform can complete the test of the tested chips associated with all the original vector segments analyzed in the step S13. Examples of the various modules of the test platform may be found in the description of the test method section below in which the test platform performs chip testability designs.

The test platform of the embodiment of the disclosure can have the following functions: stimulus driving, vector value comparison, error information (Error Information) recording (storing) and/or outputting (printing, reporting). Examples of each function may be found in the description of the test method section below in which the test platform performs chip testability designs.

In one possible implementation, the plurality of second test vectors includes test vectors written in different languages, including at least one of a standard test interface language (Standard Test Interface Language, STIL), a waveform generation language (WaveformGeneration Language, WGL), a test description language (Test Description Language, TDL).

For example, referring to FIG. 2, the numbers of the second test vectors in the waveform generation language WGL format may be A0-An, the numbers of the second test vectors in the standard test interface language STIL format may be B0-Bn, and the numbers of the second test vectors in other formats may be C0-Cn. It should be noted that references to A0-An, B0-Bn, C0-Cn in this disclosure are merely references to numbers and do not represent the second test vector itself. In fig. 2, the number of second test vectors in each format is the same and n is equal to n, and those skilled in the art will understand that the number of second test vectors in each format may also be different, which is not limited by the present disclosure.

It should be understood by those skilled in the art that the format of the second test vector may be further expanded, so long as the programming language of the test vector that can be used to write the chip testability design in the prior art, the specific format of the second test vector is not limited in this disclosure.

In this way, a diversification of the test vector format can be achieved.

Examples of the common information and the auxiliary information obtained by analyzing the test vector analysis data identification are described below, respectively.

In one possible implementation, the common information includes one or more of chip pin parameters, time parameters, test cycle time definitions of the chip under test.

The chip pin parameter may indicate information about the chip pin used for testing and its input attribute, output attribute, input and output bi-directional attribute, and so on. For example, for the second test vector in the standard test interface language STIL format, the chip pins used for testing may be pins under the sign keywords in the second test vector, and the input attribute, the output attribute, the input and output bidirectional attribute of each pin may be described by In, out, inOut of each pin under the sign keywords in the second test vector; for the second test vector in the WGL format, the chip pins used for testing may be pins under the signal key in the second test vector, and the input attribute, the output attribute, the input and output bidirectional attribute of each pin may be described by each pin input, output, bidi under the signal key in the second test vector. The chip pin parameters may also indicate grouping information of the chip pins, such as for a second test vector in the standard test interface language, STIL, format, which may be described by a plurality of signal groupings under the SignalGroups key in the second test vector.

The time parameter may indicate a test period, and the test of the chip testability design may correspond to a plurality of test periods. For example, for the second test vector in the standard test interface language STIL format, the time parameter may be described by parameter values such as test equipment periods (test_periods), stimulus driving moments (t_time), stimulus driving window lengths (t_width), output observation moments (strob_t), and output observation window lengths (strob_window_tmp) under Spec keywords in the second test vector; for a second test vector in the waveform generation language WGL format, the time parameter may be described by an equencing key in the second test vector.

The test period time definition can indicate the waveform of the excitation signal in the test period and observe the vector value time output by the chip, wherein the excitation signal can be used for outputting codes to the chip to be tested, the codes of the chip to be tested can generate and output vector values according to the excitation signal, and the vector values output by the chip can be used for carrying out vector value comparison. For example, for a second test vector in the standard test interface language STIL format, the waveform of the excitation signal may define, by using the description of Waveforms under waveform keywords in the second test vector and combining with time parameters, the waveform of the excitation signal and the time point of observing the vector value output by the chip in the test period; for a second test vector in the waveform generation language WGL format, the test cycle time definition can be described by excitation and output observation of each pin input under the timeplate key in the second test vector.

For the second test vectors in other formats than the standard test interface language STIL and the waveform generation language WGL, the common information may be extracted based on the specific keywords included in the second test vector, which is not described herein.

The chip pin parameter, the time parameter and the test cycle time definition in the common information can be a common part defined by the chip pin parameter, the time parameter and the test cycle time in the analysis data of each second test vector. In this way, the data processing costs of using the common information to obtain the test platform can be reduced.

In one possible implementation, the auxiliary information includes guiding information for controlling the test platform to test the tested chip and difference information of each second test vector.

For example, first, the auxiliary information may be used to determine a control behavior of the test platform during the test of the testability design of the tested chip by the test platform, for example, to control the test platform to perform a test method of the testability design of the chip described below, so that the auxiliary information may include guiding information for controlling the test platform to test the tested chip, where the guiding information may be obtained by analyzing the test vector analysis data. The instruction information may include test cycle driving parameters for controlling the manner of driving stimulus and test cycle observation comparison parameters for controlling the comparison method, and exemplary use of the instruction information may be found in the related description of the test method section for chip testability design below.

Next, each second test vector is different, and the difference information between each second test vector and the other second test vectors may be stored as a part of the auxiliary information together with the common information. For example, when the test cycle time definition of a certain second test vector is inconsistent with that of other second test vectors, the auxiliary information of the second test vector may include an excitation driving and output observation time definition part input to the chip in the second test vector.

By the method, the second test vectors can be described without distortion by combining the public information and the auxiliary information, the data quantity required to be stored is smaller, and the data storage cost is reduced.

The test platform of the embodiments of the present disclosure may be implemented by a synthesizable hardware description language verilog. In this case, the test platform may be adapted to a hardware simulation platform, such as a hardware accelerator (simulation), so that the test platform may perform the test methods of chip testability designs described below faster. The test platform of the embodiment of the disclosure can also be realized by a synthesizable hardware description language verilog and a non-synthesizable statement, and the non-synthesizable statement can be used for adding functions such as debugging and positioning for the test platform so as to improve the capability of the test platform. The test platform can also be adapted to a software Simulation platform, such as a software Simulation server (Simulation), so that the test platform can be switched between the software Simulation platform and the hardware Simulation platform, and flexibility of application modes of the test platform is improved. Fig. 3 and table 1 show examples of test speeds of a test platform in different modes of use on different simulation platforms according to embodiments of the present disclosure.

TABLE 1

Referring to fig. 3 and table 1, when the test platform of the embodiments of the present disclosure is applied to a software simulation server, a usage mode may include a simulation mode in which the test platform may be applied to a Simulator (Simulator) scenario, and a test speed (simulation speed) is about 10Hz; when the test platform is applied to the hardware accelerator, the use modes can comprise a transaction level verification acceleration (Transaction Based Acceleration, TBA) mode and an internal circuit simulation (In-CircuitEmulation, ICE) mode, wherein the test platform can be applied to an EMU-simulation acceleration scene of the hardware accelerator In the transaction level verification acceleration TBA mode, the test speed (simulation speed) can reach 10 KHz-100 KHz, the test platform can be applied to an EMU-prototype verification scene of the hardware accelerator In the internal circuit simulation ICE mode, and the test speed (simulation speed) can reach 100 KHz-4 MHz. It can be seen that the test speed (simulation speed) of the test platform when applied to the hardware accelerator is greater than the test speed (simulation speed) when applied to the software simulation server. When the test method is applied to a hardware accelerator, the test speed (simulation speed) is the fastest in the internal circuit simulation ICE mode. Moreover, the logic scale of the tested circuit supported by the test platform when applied to the hardware accelerator is far larger than that of the tested circuit when applied to the software simulation server.

Alternatively, the test platform may be applied to other hardware simulation platforms besides a hardware accelerator, such as a field programmable gate array FPGA, etc., and other software simulation platforms besides a software simulation server, which is not limited by the present disclosure.

By the method, the test platform of the embodiment of the disclosure can achieve improvement of simulation speed, is suitable for various platforms, improves flexibility of application modes of the test platform, reduces limited degree of logic scale of a tested chip, and improves capability of the test platform.

An example of the splitting condition of the embodiment of the present disclosure is described below.

In one possible implementation, the chip under test includes at least one subsystem, each subsystem including at least one module, and the splitting condition of the plurality of second test vectors includes:

for the part of the second test vectors, which is related to the initializing function of the tested chip, a first original vector segment is obtained, and the first original vector segment corresponds to each subsystem and each module;

obtaining at least one second original vector segment for a part, related to an initializing function, of at least one subsystem of the tested chip, of the plurality of second test vectors, wherein each second original vector segment corresponds to one subsystem;

For the part of each second test vector related to the function of at least one module of the tested chip, at least one third initial vector segment is obtained, wherein each third initial vector segment corresponds to at least one module or function belonging to the same subsystem, and the degree of association between a plurality of modules corresponding to the same third initial vector segment is greater than a first threshold.

For example, the chip under test may include at least one subsystem, each subsystem may include at least one module. When writing the second test vector, corresponding parts of the module and/or subsystem and/or the function of the whole chip used for testing can be respectively written to form the second test vector together.

The second test vector is written for any part of the chip, and needs to test whether the chip is initialized and checked to be normal or not, so that the second test vector may have a part related to the initializing function of the tested chip (i.e. the above-mentioned chip common initializing function). For a second, different test vector, the parts related to the test of the initialization function of the chip may be the same, as long as the chips concerned are the same. For this, a first original vector segment may be obtained for a portion of the plurality of second test vectors related to the initializing function of the chip under test, where the plurality of second test vectors are used to test the same type of chip under test, and the first original vector segment may correspond to each subsystem and each module of the chip under test. In this case, the first original vector segment corresponds to a segment for the initialization function of the test chip split by each second test vector.

At least one subsystem and/or at least one module of the chip under test needs to be tested for power-on initialization and checking whether the function is normal when the second test vector is written, so the second test vector may have a portion related to the initialization function (i.e., the above-mentioned subsystem initialization function) of the at least one subsystem of the chip under test. For a second, different test vector, the portion of the subsystem relevant to the test for the initialization function may be the same for the same subsystem. For this purpose, at least one second original vector segment can be obtained for a portion of the plurality of second test vectors that is related to the initialization function of at least one subsystem of the chip under test, wherein each second original vector segment corresponds to one subsystem. In this case, the second original vector segment corresponding to a certain subsystem corresponds to a segment split from each second test vector written for that subsystem for testing the initialization function of that subsystem.

When the second test vector is written for at least one module of the chip under test (i.e. the second test vector is used for implementing or testing the combined function of one module or a plurality of modules), it is necessary to test whether the at least one module functions normally, so that the second test vector may be provided with a part related to the function of the at least one module of the chip under test (i.e. the above-mentioned test function of the whole chip or subsystem or module). If the second test vector is written for only one module, for example, when the second test vector is written for a plurality of modules, when the association degree between the modules is weaker, the functions completed by each module can be considered to be independent, the splitting according to the functions of each module can not have adverse effects on the function test of the module of the chip, otherwise, when the association degree between the modules is stronger, each module can be considered to be a coupled module group, and each module is used for completing the functions of the module group together while also being used for completing the functions of the module group. In order to ensure the independence and the integrity of functions, the plurality of coupled modules can be split as units to realize the function test of the module group.

In this regard, the embodiment of the present disclosure proposes setting a first threshold, and may obtain at least one third initial vector segment for a portion of the plurality of second test vectors related to a function of at least one module of the tested chip, so that each third initial vector segment corresponds to at least one module belonging to the same subsystem, and a degree of association between a plurality of modules corresponding to the same third initial vector segment is greater than the first threshold, so that a portion corresponding to a module with a stronger degree of association is not split.

For a second, different test vector, the portion of the test related to the function of the module may be the same for the same module. In this case, the third initial vector segment corresponding to a certain module (or a certain number of modules) corresponds to a segment for testing the function of the certain module (or a certain number of modules) split from each second test vector written for the certain module (or a certain number of modules).

As described above, the splitting step may be performed by a "test vector parser" included by a "test vector parse engine". When the resolution is performed based on the resolution conditions, the resolution modes can be as follows:

1. When the second test vector is written, keywords used for different functions of the module, the subsystem and the chip are different, so that a user can provide the keywords, and when the test vector analyzer determines that the second test vector has the keywords matched with the designated keywords, the segment corresponding to the complete module or subsystem or the chip function, to which the determined keywords belong, is split.

2. The second test vector may include a vector value (Tester Cycle Vector) of pins of the tested chip in each test period, and the user may specify a vector value of a specific pin group (pin group) of the chip in the second test vector in the specific test period, and when the "test vector analyzer" determines that the vector value of the specific pin group in the second test vector in the specific test period matches the vector value specified by the user, the determined vector value of the specific pin group in the specific test period is split into segments corresponding to complete modules or subsystems or chip functions.

3. The second test vector may include vector values (Tester Cycle Vector) for pins of the chip under test at each test period, and the vector values for pins may form a sequence within each test period. The user can specify a sequence of vector values in a specific period, and when the test vector analyzer determines that the vector value sequence of the specific test period in the second test vector is matched with the vector value sequence specified by the user, the segment corresponding to the complete module or subsystem or chip function to which the determined vector value sequence of the specific test period belongs is split.

4. The second test vector may include timing of pins of the chip under test. The user can specify the time sequence of the specific pin, and when the "test vector analyzer" determines that the time sequence of the specific pin in the second test vector is matched with the time sequence specified by the user, the segment corresponding to the complete module or subsystem or chip function to which the determined time sequence of the specific pin belongs is split.

Those skilled in the art will appreciate that the manner of splitting should not be limited to the examples described above, as may combinations of the various ways described above, and so forth.

The "test vector parser" may store relevant information (such as length, etc.) of the split original vector segments in a database, where the length information of the original vector segment with the largest length may be used by the "test platform generator" to calculate the storage space of the test platform, and other information may be used by the "test platform generator" to determine the control logic of the test platform, etc.

Further, reasonable grouping management can be carried out on the split original vector segments, and the method is convenient for subsequent procedures to use. For example, the original vector segments may be stored as a segment set. For example, the first original vector segment may be used as a segment set related to the initializing function of the chip under test, the second original vector segment corresponding to each subsystem may be used as a segment set related to the initializing function of the subsystem, and the third original vector segment corresponding to each subsystem may be used as a functional segment set of the subsystem.

After the multiple fragments are split based on the splitting conditions specified by the user, the splitting conditions met by each fragment can be identified, or the fragment set to which each fragment belongs can be identified, so that the relation among the fragments can be defined.

In one possible implementation, the method further includes:

step S14, generating a test vector segment corresponding to each original vector segment according to the test vector analysis data corresponding to the original vector segment, wherein the test vector segment is a segment identifiable by a test platform, and is used when the test platform tests the independent chip function of the tested chip.

For example, the original second test vector is a vector unrecognizable by the test platform, so that the original vector segment obtained by splitting the second test vector is also a segment unrecognizable by the test platform, and cannot be used when the test platform tests the tested chip. In contrast, when analyzing the test vector analysis data corresponding to the original vector segment, in step S14, the vector value (Tester Cycle Vector) of the original vector segment in each test period may be obtained by extracting and converting the vector value based on the test period (tester cycle), that is, the excitation vector value input by each pin and the expected vector value output by each pin in each test period of the original vector segment may be stored in a data format identifiable by the test platform, so as to obtain the test vector segment corresponding to each original vector segment one by one. The test vector segment can be a segment which can be identified by the test platform and can be used when the test platform tests the tested chip. FIG. 4 illustrates an example of multiple test vector segments resulting from splitting a second test vector according to a split condition of an embodiment of the present disclosure. In the example of fig. 4, for the second test vector numbered A0, a segment for the initialization function of the test chip, a segment for the initialization function of the test subsystem D, and a segment for the functions of the respective modules of the test subsystem D (numbered a00-A0 a) may be correspondingly obtained.

Alternatively, as shown in fig. 2, a "test vector segment generator" (software module) may be provided, and the test vector parsing data corresponding to each original vector segment is used as an input of the "test vector segment generator", which performs step S14. The test vector analysis data corresponding to each original vector segment can be serially input into a test vector segment generator. Because the test vector analysis data corresponding to each second test vector also corresponds to the auxiliary information of the second test vector, the auxiliary information corresponding to the same original vector segment and the test vector segment can also correspond to each other and can be output by a test vector segment generator together. The test vector segment obtained from the original vector segments in the same segment set can also be used as a segment set. In the example of fig. 2, the "test vector segment generator" output may be a set of segments related to the initialization function of the chip under test (including segments for the initialization function of the test chip), a set of segments related to the initialization function of subsystem D (including segments for the initialization function of test subsystem D), a set of segments related to the initialization function of subsystem E (including segments for the initialization function of test subsystem E), a set of segments related to the module function in subsystem D (including segments a00-A0a, … …, segments Am 0-Amb), a set of segments related to the module function in subsystem E, and so forth. Wherein the segments A00-A0a can be derived from the second test vector numbered A0 and the segments Am0-Amb can be derived from the second test vector numbered Am.

In this way, the test vector segment which can be identified by the test platform can be obtained, and the auxiliary information corresponding to the test vector segment can be obtained, so that the test of the tested chip by using the test platform is possible.

In one possible implementation, the test vector segment includes expected vector values and stimulus vector values for the unidirectional pins and expected/stimulus vector values for the bidirectional pins of the chip under test for each test cycle under the test vector segment.

For example, the length of a test vector segment is related to the number of cycles under the test vector segment, with longer lengths having larger numbers of cycles and shorter lengths having smaller numbers of cycles. The format of the test Vector segment recognizable by the test platform may be a two-dimensional array, where each row of the two-dimensional array stores Vector (Vector) data of a single test period, for example, the array has m rows, the first row may store Vector data of test period (Tester cycle) 0, and so on, the m-th row may store Vector data of test period m-1, i.e., the test period number of the test Vector segment is equal to the depth (number of rows) of the two-dimensional array. The two-dimensional array may be a binary array such that test vector segments may be directly loaded into a memory region of the test platform. Those skilled in the art will appreciate that the two-dimensional array may be an array in other formats that are recognizable by the test platform memory space, as this disclosure is not limited in this regard.

Based on this, the data for each test cycle can be analyzed first for the test vector parse data for the test vector segment. For example, for the basic grammar, the part corresponding to each test period in the test vector analysis data can be directly extracted in units of test periods, and for the test vector analysis data of the test vector segment in the standard test interface language STIL format, the part under the V key can be analyzed; for test vector segment test vector parsing data in the waveform generation language WGL format, the portion under the vector key can be parsed.

For the Loop syntax, the Loop description for the test vector in the parsed data may be expanded into data for each test cycle, e.g., for test vector parsed data for test vector segments in the standard test interface language, STIL, the portion under the Loop key may be expanded.

For scan chain syntax, scan chain definitions and some macro definitions may be obtained at parsing time. The scan chain definition may be a statement of a scan unit in the scan chain, and a structural description, a state description, etc. of the scan chain, for example, test vector analysis data of a test vector segment in a standard test interface language STIL format, and the structural description of the scan chain may be recorded under ScanStructures key words, including descriptions of chain lengths, inverse times, input pins, output pins, and scan clocks of each scan chain; for test vector parsing data of test vector segments in waveform generation language WGL format, the structural description of the scan chain may be described under scancell, scanchain key, and the state description of the scan chain may be described under scan state key. The macro definition may include a macro definition template of test vectors, such as test vector parsing data for test vector fragments in the standard test interface language, STIL, format, which may be described under MacroDefs keywords. The data of each test period can be obtained by analyzing the scan chain definition and the macro definition.

It should be understood that the example of analyzing the test vector analysis data to obtain the data of each test period should not be limited to the above manner, so long as the analysis manner can be implemented in the prior art, and the embodiments of the present disclosure are not limited thereto.

After the data of each test period is obtained, vector data (Vector) of a row in the test Vector segment can be correspondingly obtained based on the data of each test period. The vector data for each row may include the following portions: the excitation vector value and the expected vector value of a unidirectional pin of the chip to be tested, namely the input/output attribute of the pin is not changed in the whole test process, and the input/output attribute occupies 2 bits respectively; the expected/excitation vector value of the bi-directional pin of the chip under test, i.e. the input/output properties of the pin will change throughout the test, accounting for a total of 3 bits. Optionally, the method may further include a test cycle number, that is, a test cycle number of the vector data in the entire first test vector, where the test cycle number may be used when debugging the first test vector, and may occupy 32 bits. Optionally, other information can be expanded and added, and the bit width is defined by itself. Examples of the excitation vector values of the unidirectional pins and the expected vector values of the unidirectional pins may be found in tables 2 and 3, respectively. Examples of expected/excitation vector values for the bi-directional pins can be seen in table 4.

TABLE 2

Unidirectional pin excitation vector value (2 bit)	Description of the invention
		2’b00	Chip pin input stimulus of 0
2’b01	Chip pin input stimulus 1
		2’b10	-
2’b11	Chip pin input excitation is in high resistance state Z

TABLE 3 Table 3

Unidirectional pin expected vector value (2 bit)	Description of the invention
		2’b00	Chip pin out is expected to be 0
2’b01	The chip pin out is expected to be 1
		2’b10	-
2’b11	The chip pin-out is expected to be X, i.e. unexpected

TABLE 4 Table 4

Bidirectional pin excitation/expected vector value (3 bit)	Description of the invention
		3’b000	Chip pin input stimulus of 0
3’b001	Chip pin input stimulus 1
		3’b010	-
3’b011	Chip pin input excitation is in high resistance state Z
		3’b100	Chip pin out is expected to be 0
3’b101	The chip pin out is expected to be 1
		3’b110	-
3’b111	The chip pin-out is expected to be X, i.e. unexpected

Referring to table 2, when the input excitation of the unidirectional pin of the chip is determined to be 0 according to the test vector analysis data, an excitation vector value 2' b00 of the unidirectional pin can be obtained; when the input excitation of the unidirectional pin of the chip is determined to be 1, an excitation vector value 2' b01 of the unidirectional pin can be obtained; when the input excitation of the unidirectional pin of the chip is determined to be in a high resistance state Z, the excitation vector value 11 of the unidirectional pin can be obtained. Where "2' b" is used to describe that the excitation vector value of the unidirectional pin occupies a bit width of 2 and the value is binary.

Referring to table 3, when it is determined that the unidirectional pin output of the chip is expected to be 0 according to the test vector analysis data, an expected vector value 2' b00 of the unidirectional pin can be obtained; when the unidirectional pin output expectation of the chip is determined to be 1, an expected vector value 2' b01 of the unidirectional pin can be obtained; when it is determined that the unidirectional pin output of the chip is expected to be X, i.e., unexpected, the expected vector value 11 of the unidirectional pin can be obtained.

Referring to Table 4, when the input excitation of the bidirectional pin of the chip is determined to be 0 according to the test vector analysis data, the excitation vector value 3' b000 of the bidirectional pin can be obtained; when the input excitation of the chip pin is determined to be 1, an excitation vector value 3' b001 of the bidirectional pin can be obtained; when the input excitation of the chip pin is determined to be in a high-impedance state Z, an excitation vector value 3' b011 of the bidirectional pin can be obtained; when the bidirectional pin output expectation of the chip is 0, an expected vector value 3' b100 of the bidirectional pin can be obtained; when the bidirectional pin output expectation of the chip is 1, an expected vector value 3' b101 of the bidirectional pin can be obtained; when the bidirectional pin output of the chip is determined to be expected as X, namely unexpected, the expected vector value 3' b111 of the bidirectional pin can be obtained. Where "3' b" is used to describe that the expected/drive vector value of the bi-directional pin occupies a bit width of 3 and the value is binary.

After each row of vector data of the test vector segment is determined, the position of each row of vector data in the two-dimensional array can be determined according to the sequence from small to large of the test period sequence number, and the test vector segment in the two-dimensional array format can be obtained. Table 5 shows an example of a format of a test vector segment according to an embodiment of the present disclosure.

TABLE 5

Chip pin a (unidirectional excitation)

…

Chip pin b (unidirectional expectation)

…

Chip pin c (two-way)

…

Test cycle number

2’b00

…

2’b11

…

3’b000

…

32’h0000_0000

2’b01

…

2’b11

…

3’b001

…

32’h0000_0001

2’b00

…

2’b11

…

3’b111

…

32’h0000_0002

…

As shown in table 5, each pin in each test cycle may have a different stimulus/expected vector value. In the example of table 5, the chip under test may include 3 or more test cycles (test cycle numbers 32' h0000_0000, 32' h0000_0001, 32' h0000_0002, … …) and 2 or more unidirectional pins (chip pin a, chip pin b, … …) and 1 or more bidirectional pins (chip pins c, … …). Taking the test period with the test period serial number of 32'h0000_0000 as an example, in the test period, the input stimulus of the chip pin a may be 0 (stimulus vector value 2' b 00), the output stimulus of the chip pin b may be expected to be 1 (expected vector value 2'b 11), and the input stimulus of the chip pin c may be 0 (stimulus/expected vector value 3' b 000). "32' h" means that the bit width occupied by the test period number is 32 and the value is hexadecimal.

It should be understood that the binary form of the corresponding relationship between the excitation/expected vector values and the input excitation/output expected of the pins shown in tables 2-4 is only an example, for example, the corresponding relationship between the two may be that the input excitation of the corresponding unidirectional pins is in a high resistance state when the excitation vector value 2' b10 is the same, so long as the excitation/expected vector values and the input/output states of the pins are in one-to-one correspondence, and the excitation/expected vector values corresponding to different states of the pins are different, which is not limited in the present disclosure. Alternatively, the bit width of the excitation/desired vector value may also be varied, etc., as this disclosure is not limited in this regard. The format of the first test vector shown in table 5 is merely an example, and the first test vector may further include more information, such as control information, debug information, etc. for chips other than the expected/stimulus vector values of pins, which is not limited by the present disclosure.

It should be understood by those skilled in the art that the "test vector analyzer" may also obtain a complete vector and auxiliary information identifiable by the test platform according to the analysis data of the complete second test vector without using a splitting condition, and use the complete vector and auxiliary information when the test platform tests the tested chip.

In one possible implementation, the method further includes:

step S15, at least one execution file is generated according to the plurality of test vector segments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test case is executed, the plurality of test vector segments and auxiliary information corresponding to the execution file of the test case are sequentially input to the test platform.

The number of execution files can be different according to different requirements of users. FIG. 5 illustrates an example of obtaining an execution file according to an embodiment of the present disclosure.

For example, as shown in fig. 5, when the user requirement is single use case simulation, a use case execution file (single random use case execution file) for single use case execution may be generated based on the test vector segment; when the user demand is multi-use case regression, a plurality of use case executives (random use case R0 executives-random use case Rn executives) for multi-use case regression and regression executives may be generated based on the test vector segments. Alternatively, as shown in fig. 2 and 5, an "execution file generator" (software module) may be provided, and the test vector segment set and the combination condition are used as inputs of the "execution file generator", which performs step S15, and may generate a compiling/comprehensive execution file, a use case execution file, and a regression execution file.

Wherein the combination condition may indicate a combination manner of the fragments in the fragment set of the test vector fragment. Examples of combining conditions and generating at least one execution file from a plurality of test vector segments and combining conditions may be found in the related description below.

Executing the test case corresponding to a certain execution file may be running a corresponding command line in the execution file, so that a plurality of test vector segments corresponding to the execution file are sequentially input to the test platform, and the test platform generates a case execution log. The use case execution log may be a log corresponding to a single test case for the use case execution file; for the regression execution file, the use case execution log may be a log corresponding to a plurality of test cases. Various uses of the execution file may be found in the description of the test methods section of chip testability design below.

By the method, the execution file can be automatically generated, and the execution file can correspond to at least one test case, so that single case simulation and multi-case regression can be realized when the test case corresponding to the execution file is executed, and the convenience of executing the test case is improved.

In one possible implementation, a test vector segment of a single execution file is generated, including test vector segments corresponding to a first original vector segment, a second original vector segment, and a third original vector segment, with a combination condition including at least one of:

Generating test vector segments of a single execution file and combining the test vector segments according to a preset sequence;

generating a test vector segment of a single execution file corresponding to a preset subsystem;

and generating test vector fragments of the single execution file, wherein the total number of the test vector fragments corresponding to the third initial vector fragment is larger than or equal to the second threshold value and smaller than or equal to the third threshold value.

For example, in the prior art, one test case typically covers all subsystems of the entire chip, in which case the results obtained from each execution of the test case are typically the same, lacking randomness. In this regard, in the embodiment of the present disclosure, it is proposed that a user designates a random combination condition, and based on all the test vector segments obtained in the above steps, the segments are combined to obtain an execution file of one or more random test cases (hereinafter also referred to as random cases), so that the test platform can execute the one or more random cases.

Any random use case may be a complete use case, that is, may be used to test the initialization function of the tested chip, the initialization function of one or more subsystems of the tested chip, and the functions of some or all modules included in the one or more subsystems, so first, a test vector segment of a single execution file is generated, and may include test vector segments corresponding to the first original vector segment, the second original vector segment, and the third original vector segment. On this basis, the combination condition may include at least one of:

1. The combination condition of the vector segment order in combination is defined, so that the test vector segments generating the single execution file are combined according to the preset order. For example: the test vector segment corresponding to the first original vector segment is the forefront, the second original vector segment is the second original vector segment, and the test vector segment corresponding to the third original vector segment is the last.

2. The range of segment sets to which the vector segments belong when combined is defined such that the test vector segments that generate a single execution file correspond to a preset subsystem, such as: the user wants to test the functionality of subsystem D of the chip under test, it can be defined that the second original vector segment at the time of combining belongs to the segment set related to the initialization function of subsystem D, and the third original vector segment belongs to the segment set related to the module function in subsystem D.

3. The number of test vector segments at the time of combination is defined so that, among the test vector segments that generate a single execution file, the total number of test vector segments corresponding to the third initial vector segment is greater than or equal to the second threshold value and less than or equal to the third threshold value, for example, the second threshold value may be set to 1, the third threshold value may be set to 6, and then the total number of test vector segments corresponding to the third initial vector segment may be defined as a random integer between [1:6 ].

As shown in fig. 6, the user requirement may be to obtain an execution file for the functions of any 1 to 6 modules of the test subsystem D, for example, a random use case R0 execution file. The combination conditions may be: the method comprises the steps of generating test vector segments of a single execution file to be combined according to a preset sequence, wherein the preset sequence is that the test vector segment corresponding to a first original vector segment is the forefront, the second original vector segment is the second original vector segment, and the test vector segment corresponding to a third original vector segment is the last; generating a test vector segment of a single execution file corresponding to subsystem D; and generating test vector segments of the single execution file, wherein the total number of the test vector segments corresponding to the third initial vector segment is greater than or equal to 1 and less than or equal to 6. According to the combination condition, the first test vector segment of the sequence of test vector segments may be an index of segments for the initialization function of the test chip, and the second test vector segment may be an index of segments for the initialization function of the test subsystem D, followed by an index of 1 to 6 test vector segments related to the random 1 to 6 module functions in the subsystem D, such as an index of test vector segments R00-R0n, in turn. When the random use case R0 is executed according to the generated execution file, firstly, the test of the initialization function of the tested chip is finished, secondly, the test of the initialization function of the subsystem D is finished, and finally, the test of the functions of 1-6 modules in the subsystem D corresponding to the test vector segment is finished in sequence.

Alternatively, in the execution file, only the index of the test vector segment may be recorded, and specific information of the test vector segment does not have to be recorded.

It should be understood by those skilled in the art that the combination conditions supportable by the embodiments of the present disclosure should not be the examples described above, as long as the combination of test vector segments can be enabled to have a certain randomness, for example, a user may also be supported to specify a case random seed, that is, the random results of the same seed are consistent under the same verification environment; supporting the regression times of the appointed use cases; support specifying multiple sets of random constraints, specifying the number of use case regressions under each set of constraints, etc., which is not limiting in this disclosure.

According to the test requirement of the user, the 'execution file generator' can obtain an application execution file corresponding to a random application for single-application simulation, and can obtain a plurality of application execution files corresponding to a plurality of random applications (R0-Rn) and regression execution files for multi-application regression. Further, the "test vector parse engine" may automatically execute a single random use case or multiple random use cases. Optionally, embodiments of the present disclosure also support a user manually executing a single random use case or multiple random use cases. The following describes a method for implementing execution of random use cases in the embodiments of the present disclosure, that is, a method for testing chip testability design in the embodiments of the present disclosure.

Fig. 7-9 illustrate method flowcharts of a test method for chip design for testability according to embodiments of the disclosure. As shown in fig. 7, the method is applied to a test platform, and the method includes:

step S21, receiving a plurality of test vector segments and auxiliary information corresponding to execution files of test cases, wherein the test vector segments are segments identifiable by a test platform, different test vector segments are used for realizing or testing the independent chip functions of the tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

step S22, testing the tested chip, including: based on the auxiliary information, controlling the excitation signal corresponding to the test vector segment to be output to the code of the tested chip; acquiring an actual vector value of code output of a chip to be tested; and determining a test result according to the comparison result of the expected vector value and the actual vector value included in the test vector segment, wherein the test result corresponding to the plurality of test vector segments indicates whether the chip function of the tested chip corresponding to the plurality of test vector segments is normal or not, and the test result is displayed through an instance execution log.

For example, the whole chip is usually very large in size, and the code of the chip is generally compiled/integrated in the process before the test is performed. As shown in fig. 8, based on the test platform, the prior art can be used to generate a "compile/synthesize file" to package a series of command operations into a compact command, which is convenient for the user to operate. In this case, when executing the test case, the user only needs to input the file of the test platform and the code of the tested chip. The user modifies a small amount of necessary information (e.g., test data storage path, which test case or cases are executed, etc.), runs the command, and can complete execution of the test case, and the results of the execution (i.e., test results, case logs, etc.) can be stored in a database (database).

According to the combination conditions given by the user, the test case to be executed (namely, the random case, which is described above, may be a single random case or a multiple case) can be determined, and the test case is executed. As shown in fig. 9, the test platform may include the following modules: memory space, drive, control logic, vector value comparator. When executing test cases, under the control of a processor (not shown), the execution files (the single test case corresponds to the case execution file, and the multiple test cases correspond to the case execution file and the regression execution file) of the test cases stored in the test vector segment set can be sequentially loaded into the storage space of the test platform, and for the test platform, the control logic can have a counter function for calculating the number of test vector segments received by the test platform, and the counter count can be initialized to 0 before receiving the test vector segments and the auxiliary information; the method comprises the steps of receiving a plurality of test vector fragments and auxiliary information corresponding to an execution file of a test case, namely, each time one test vector fragment is received, adding 1 to the counter count, determining that the plurality of test vector fragments are received completely when the counter count reaches the total number of the test vector fragments corresponding to the execution file, and not receiving new test vector fragments any more, otherwise, continuing to receive the next test vector fragment. Examples of the test vector segments and the acquisition methods may be referred to the related descriptions of tables 2 to 5 above, examples of the acquisition methods of the auxiliary information may be referred to step S12 above, and examples of the acquisition methods of the test vector segments may be referred to step S14 above.

In step S22, when the chip under test is tested, the test of the test vector segment can be completed after receiving a test vector segment and auxiliary information. Based on the auxiliary information, the code of the excitation signal corresponding to the test vector segment is controlled to be output to the tested chip, the actual vector value of the code output of the tested chip is obtained, the test result is determined according to the comparison result of the expected vector value and the actual vector value included in the test vector segment, the data in the storage space can be read by the test platform first, the test vector segment and the auxiliary information are distinguished, the auxiliary information comprises the guide information for controlling the test platform to test the tested chip, when the use case is executed, the auxiliary information is loaded into the control logic according to the flow indicated by the execution file, and the execution of the control logic can control the execution of the step S22 to complete the following functions: based on the auxiliary information, the transmission timing of the excitation signal, the comparison of vector values, the storage of the comparison result, and the like are controlled. All test platform behavior control related processing can be generalized into this module. For example, the control logic may drive the excitation driver to output the code of the excitation signal to the chip according to the auxiliary information, control the vector value comparator to obtain the expected vector value included in the test vector segment from the storage space, control the vector value comparator to obtain the actual vector value from the code of the chip according to the expected vector value, and control the vector value comparator to compare the expected vector value included in the test vector segment with the actual vector value, so as to obtain the comparison result corresponding to the test vector segment. For a specific implementation, see the further description of step S22 below. After the test platform finishes the comparison of the expected vector value and the actual vector value included in the current test vector segment, the current test vector segment can be considered to finish the test, the next test vector segment can be continuously received, and the next test vector segment is continuously used for testing the chip until the last test vector segment corresponding to the execution file finishes the test. When the tests of all the test vector segments are determined to be completed, test results can be determined according to comparison results of expected vector values and actual vector values included by the plurality of test vector segments, and the test results can be displayed through use case execution logs.

The current test vector segment can be cleared after the test is completed, and the next test vector segment is received to continue the test, so that the storage space only needs to store one test vector segment.

As shown in fig. 8, assuming that each second test vector corresponds to one test case, for example, the second test of the number A0 corresponds to the test case of the number A0, for the test case simulated by a single case (for example, the test case of the number A0/the number An/the number Cn), one case execution log (for example, the case execution log of the number A0/the number An/the number Cn) may be obtained, and the log may be further analyzed by the execution case call log analysis function to determine whether the current test case passes or fails.

For a plurality of test cases (for example, test cases with numbers A0, an and Cn) of multi-case regression, for each test case corresponding case execution file or regression execution file corresponding to all cases, a plurality of case execution logs (for example, case execution logs with numbers A0, an and Cn) corresponding to the plurality of test cases can be obtained respectively, and then the plurality of case execution logs can be analyzed uniformly to obtain a regression analysis report of the chip testability test.

Wherein A0, an and Cn represent numbers, and do not represent test cases per se.

In a possible implementation manner, in step S22, a code for controlling, based on the auxiliary information, the output of the excitation signal corresponding to the test vector segment to the chip under test includes:

and outputting an excitation signal to the code input interface of the tested chip at the time point indicated by the test period driving parameter in the auxiliary information, and outputting an actual vector value by the code output interface of the tested chip.

For example, referring to the above, the auxiliary information may include a test period driving parameter for indicating at which time points the stimulus signal is output to start one test period, and the like. In this regard, as shown in fig. 8, each test case may have a corresponding excitation signal (i.e., a case Waveform of number A0/number An/number Cn in fig. 8, etc.), and the "control logic" may control the "excitation driver" to output the excitation signal to the input interface of the code of the chip under test at a correct time point based on the test cycle driving parameter in the auxiliary information to complete driving, and the Waveform of the excitation signal may be set based on various Waveform templates (Waveform tables), which is not limited in this disclosure. The code of the tested chip simulates the signal processing process of the actual chip according to the excitation signal to obtain the actual vector value of each pin of the tested chip, and if no error occurs in the testability design of the chip, the actual vector value of each pin and the expected vector value (embodied in the test vector segment) of the pin can be the same. The actual vector value may be output by an output interface of the code of the chip under test.

In this way, the excitation driving of the chip under test can be completed. The excitation signal used for driving supports various waveforms, so that the flexibility of an excitation driving mode can be improved.

In a possible implementation manner, in step S22, determining a test result according to a comparison result of an expected vector value and an actual vector value included in the test vector segment includes:

when the expected vector value included in the test vector segment indicates comparison, comparing whether the expected vector value in the test vector segment is matched with the actual vector value output by the chip pin at the time point indicated by the test period comparison parameter;

when the comparison result is that the actual vector value at the time point is not matched with the expected vector value, error information is recorded, wherein the error information comprises a test period corresponding to the time point, the actual vector value at the time point and the expected vector value;

and determining a test result corresponding to the current test vector segment according to the error information.

For example, as shown in fig. 9, the "control logic" may control the "vector value comparator" to read the expected vector value from the "memory space" which may determine whether the vector values of the pins in the test period need to be compared. For example, if the expected vector value is "2'b01" or "3' b101", the comparison is indicated, the interface pin output 1 of the chip code in the test period is expected, if the interface pin of the chip code actually outputs 1, the matching is performed, otherwise, the comparison fails; the expected vector value is '2' b00 'or' 3'b 100', the comparison is indicated, the output 0 of the interface pin of the chip code in the test period is expected, if the actual output 0 of the interface pin of the chip code is matched, otherwise, the comparison fails; similarly, if the expected vector value is "2'b11" or "3' b111", then no alignment is indicated and the actual output vector value of the interface pin of the chip code in this test period is not considered. The test period comparison parameter in the auxiliary information is used for indicating a time point for acquiring the pin output actual vector value of the tested chip code in the test period. When determining that the expected vector value of the pins in the test period indicates comparison, the output interface of the code of the tested chip can be used for acquiring the actual vector value output at the time point indicated by the test period comparison parameter and comparing whether the actual vector value and the expected vector value at the time point are matched. If the comparison results in a mismatch between the actual vector value and the expected vector value at the time point, the comparison may be considered to fail, error information may be recorded, and the error information may include the test period corresponding to the time point, the actual vector value and the expected vector value at the time point, and the like. The depth of storage of the error information may be specified by the user.

When the test platform is completely realized by the synthesizable hardware description language verilog, the storage space can support the storage of the earliest error information and the refreshing of the latest error information. For example, in the internal circuit emulation ICE mode described above, the "control logic" may trigger a test pause and notify the user to perform vector debugging operations when an error message is generated. The error information can be printed into a use case execution log according to the user requirement or stored by using a storage space so as to be used for the user to analyze the test condition.

When the test platform is realized by the synthesizable hardware description language verilog and comprises the non-synthesizable statement, the non-synthesizable statement can be used for directly displaying the error information through the printing grammar corresponding to the non-synthesizable statement when the error information is generated, so that the user can debug more conveniently. For example, using a hardware accelerator EMU platform of Candence, the test platform uses "$display" statement in the ICE mode described above, enables Acceleration Test (ATB) characteristics of the test platform, and simulates testing in Logic Analyzer (LA) mode; or a direct acceleration COMpiler (IXCOM) may be used directly.

In this way, the testing method for the testability design of the chip supports the comparison of the output and the expectation of the pins of the chip; when the comparison error is found, error information can be recorded and printed, and the positioning is efficient.

Examples of software simulation platforms and hardware simulation platforms have been described above and are not described in detail herein.

The embodiment of the disclosure also provides a test platform, and fig. 10 shows a structural diagram of the test platform according to the embodiment of the disclosure.

As shown in fig. 10, the test platform includes:

the receiving module 101 is configured to receive a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, where the test vector segments are segments identifiable by the test platform, different test vector segments are used to implement or test an independent chip function of a tested chip, and the auxiliary information includes instruction information for controlling the test platform to test the tested chip;

a test module 102, configured to test the chip under test, including: based on the auxiliary information, code for controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the plurality of test vector fragments indicate whether the chip functions corresponding to the plurality of test vector fragments are normal or not, and the test results are displayed through an instance execution log.

The function of the receiving module may be implemented by the storage space shown in fig. 9 and the function of the testing module may be implemented by the excitation driver, the control logic and the vector value comparator shown in fig. 9 and the foregoing.

The embodiment of the disclosure also provides a generating device of the test platform, and fig. 11 shows a structural diagram of the generating device of the test platform according to the embodiment of the disclosure.

As shown in fig. 11, the test platform generating device includes: the first analysis module 111 is configured to analyze a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, where the plurality of original vector segments are obtained by splitting a plurality of second test vectors, and different original vector segments are used to implement or test an independent chip function of a tested chip, and the second test vectors are original test vectors; a second analysis module 112, configured to analyze the test vector analysis data corresponding to each original vector segment, and identify common information of the plurality of second test vectors; the first generating module 113 is configured to generate a test platform according to the common information, where a storage space of the test platform is related to an original vector segment with a maximum length.

The functions of the first analysis module and the second analysis module may be implemented by the test vector analyzer shown in fig. 2 and the functions of the first generation module may be implemented by the test platform generator shown in fig. 2 and the test platform generator shown in fig. 2.

The function of the second generating module may be implemented by the test vector segment generator shown in fig. 2 and described above.

The function of the third generating module may be implemented by the execution file generator shown in fig. 2 and described above.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The embodiment of the disclosure also provides a computer readable storage medium, on which computer program instructions are stored, wherein the computer program instructions realize the test method of the chip testability design or the generation method of the test platform when being executed by a processor. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

The embodiment of the disclosure also provides a test platform, which comprises: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the test method for the chip testability design when executing the instructions stored in the memory.

The embodiment of the disclosure also provides a generating device of the test platform, which comprises: a processor; a memory for storing processor-executable instructions; the processor is configured to implement the method for generating the test platform when executing the instructions stored in the memory.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

Fig. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure. The apparatus 1900 may be the test platform or a generating apparatus of the test platform, and the apparatus 1900 may be provided as a server or a terminal device. Referring to fig. 12, the apparatus 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that are executable by the processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, processing component 1922 is configured to execute instructions to perform the test methods of chip testability designs or the generation methods of test platforms described above.

The apparatus 1900 may further comprise a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input/output interface 1958 (I/O interface). The apparatus 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server ^TM ，Mac OS X ^TM ，Unix ^TM , Linux ^TM ，FreeBSD ^TM Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, comprising computer program instructions executable by processing component 1922 of apparatus 1900 to perform the test method of chip testability design or the generation method of a test platform described above.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for testing design for testability of a chip, the method being applied to a test platform, the method comprising:

receiving a plurality of test vector fragments and auxiliary information corresponding to an execution file of a test case, wherein the test vector fragments are fragments identifiable by the test platform, different test vector fragments are used for realizing or testing the independent chip function of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

testing the tested chip, comprising: based on the auxiliary information, code for controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the plurality of test vector fragments indicate whether the chip functions corresponding to the plurality of test vector fragments are normal or not, and the test results are displayed through an instance execution log.

2. The method according to claim 1, wherein the code for controlling the excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information comprises:

and outputting the excitation signal to the code input interface of the tested chip at the time point indicated by the test period driving parameter in the auxiliary information, and outputting the actual vector value by the code output interface of the tested chip.

3. The method of claim 2, wherein the determining the test result from the comparison of the expected vector value and the actual vector value included in the test vector segment comprises:

when the expected vector value indication included in the test vector segment is compared, whether the expected vector value in the test vector segment is matched with the actual vector value output by the chip pin at the time point indicated by the test period comparison parameter or not is compared;

when the comparison result is that the actual vector value and the expected vector value at the time point are not matched, error information is recorded, wherein the error information comprises a test period corresponding to the time point, the actual vector value and the expected vector value at the time point;

And determining a test result according to the error information.

4. A method according to any of claims 1-3, characterized in that the test platform is adapted to a software simulation platform and a hardware simulation platform.

5. A method for generating a test platform, the method comprising:

analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, wherein the plurality of original vector segments are obtained by splitting a plurality of second test vectors, and different original vector segments are used for realizing or testing the independent chip functions of the tested chip, and the second test vectors are original test vectors;

analyzing the test vector analysis data corresponding to each original vector segment, and identifying and obtaining common information of the second test vectors, wherein the common information comprises one or more of chip pin parameters, time parameters and test period time definitions of a chip to be tested;

generating a test platform according to the public information, wherein the storage space of the test platform is related to an original vector segment with the largest length;

the tested chip comprises at least one subsystem, each subsystem comprises at least one module, and the splitting condition of the plurality of second test vectors comprises at least one of the following components:

For the part of the second test vectors, which is related to the initializing function of the tested chip, a first original vector segment is obtained, wherein the first original vector segment corresponds to each subsystem and each module;

obtaining at least one second original vector segment for a part, related to an initializing function, of at least one subsystem of the tested chip, of a plurality of second test vectors, wherein each second original vector segment corresponds to one subsystem;

for the portion of each second test vector that is relevant to the function of at least one module of the chip under test, at least one third starting vector segment is obtained, wherein each third starting vector segment corresponds to at least one module or function belonging to the same subsystem.

6. The method of claim 5, wherein the method further comprises:

generating a test vector segment corresponding to each original vector segment according to the test vector analysis data corresponding to the original vector segment, wherein the test vector segment is a segment identifiable by the test platform, and is used when the test platform tests the independent chip function of the tested chip.

7. The method of claim 6, wherein the split condition of the plurality of second test vectors further comprises:

the degree of association between the plurality of modules corresponding to the same third initial vector segment is greater than a first threshold.

8. The method of claim 7, wherein the method further comprises:

generating at least one execution file according to the plurality of test vector fragments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test case is executed, the plurality of test vector fragments and auxiliary information corresponding to the execution file of the test case are sequentially input to the test platform.

9. The method of claim 8, wherein generating test vector segments for a single execution file includes test vector segments corresponding to a first original vector segment, a second original vector segment, and a third original vector segment, the combining condition including at least one of:

10. The method according to claim 8 or 9, wherein the auxiliary information includes guide information for controlling the test platform to test the chip under test and difference information of each second test vector.

11. The method of claim 10, wherein the test vector segment includes expected vector values and stimulus vector values for unidirectional pins and expected/stimulus vector values for bidirectional pins of the chip under test for each test period under the test vector segment.

12. The method of claim 11, wherein the plurality of second test vectors comprises test vectors written in different languages, including at least one of a standard test interface language STIL, a waveform generation language WGL, and a test description language TDL.

13. The method of claim 12, wherein the test platform is adapted to a software simulation platform and a hardware simulation platform.

14. A test platform, comprising:

the first receiving module is used for receiving a plurality of test vector fragments and auxiliary information corresponding to an execution file of a test case, wherein the test vector fragments are fragments which can be identified by the test platform, different test vector fragments are used for realizing or testing the independent chip function of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

The test module is used for testing the tested chip and comprises the following components: based on the auxiliary information, code for controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the plurality of test vector fragments indicate whether the chip functions corresponding to the plurality of test vector fragments are normal or not, and the test results are displayed through an instance execution log.

15. A test platform generation device, comprising:

the first analysis module is used for analyzing a plurality of original vector fragments to obtain test vector analysis data corresponding to each original vector fragment, the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, different original vector fragments are used for realizing or testing the independent chip functions of the tested chip, and the second test vectors are original test vectors;

the second analysis module is used for analyzing the test vector analysis data corresponding to each original vector segment, and identifying and obtaining the common information of the plurality of second test vectors, wherein the common information comprises one or more of chip pin parameters, time parameters and test period time definitions of the tested chip;

The first generation module is used for generating a test platform according to the public information, and the storage space of the test platform is related to the original vector segment with the largest length;

16. A test platform, comprising:

A processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1 to 4 when executing the instructions stored by the memory.

17. A test platform generation device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 5 to 13 when executing the instructions stored by the memory.

18. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 4 or the method of any of claims 5 to 13.