CN117669440B

CN117669440B - Test method and test system for digital-analog hybrid micro module

Info

Publication number: CN117669440B
Application number: CN202410132308.5A
Authority: CN
Inventors: 曾仕鹏; 陈小波
Original assignee: Beijing Zhongtian Xingkong Science & Technology Development Co ltd
Current assignee: Beijing Zhongtian Xingkong Science & Technology Development Co ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-04-05
Anticipated expiration: 2044-01-31
Also published as: CN117669440A

Abstract

The invention discloses a testing method and a testing system for a digital-analog hybrid micro module, which relate to the technical field of system testing and comprise the following steps: acquiring a functional program used for machine test; programming a functional program into the programmable memory unit; after the micro module is electrified, loading the functional program into a programmable logic unit of the micro module; establishing communication between a preset test machine and a programmable logic unit and monitoring a communication state in real time; judging whether the communication state is normal, if so, capturing data by an analog/digital conversion unit in the micro module to obtain a capturing result and transmitting data by a digital/analog conversion unit to obtain a transmitting result, otherwise, stopping the operation; based on functional parameters, grabbing results and sending results of each component of the micro module, combining a preset test machine and a functional program to perform static test and dynamic test on the micro module. The invention solves the problem that the existing miniaturized and precise analog-digital hybrid micro-module lacks a test scheme.

Description

Test method and test system for digital-analog hybrid micro module

Technical Field

The invention relates to the technical field of system testing, in particular to a testing method and a testing system for a digital-analog hybrid micro module.

Background

Along with the high-speed development of the technical fields of domestic microelectronics and sensing signal processing, the complexity and the integration level of a signal processing system are higher and higher. Especially in the navigation system, the miniaturization and the precision of the optical fiber gyro signal processing system have higher and higher requirements on the performance of the internal integrated device, so that the testing method and the testing requirement of the integrated system also have higher and higher requirements.

Currently, a single chip test system and a test method based on an analog/digital platform are more, but a test scheme for an analog-digital hybrid system similar to a fiber optic gyro signal processing micro system is still in a blank period, so that a test scheme and a test system for a miniaturized and precise analog-digital hybrid system are needed.

Disclosure of Invention

In order to solve the problem that the existing miniaturized and precise analog-digital hybrid system lacks a test scheme, the invention provides a test method for a digital-analog hybrid micro module, which comprises the following steps:

acquiring a functional program which is used for communication and calling through an IO port during machine testing;

programming the functional program into a programmable memory unit of the micro module;

after the micro-module is powered on, loading the functional program in the programmable memory unit into a programmable logic unit of the micro-module;

establishing communication between a preset test machine and the programmable logic unit and monitoring the communication state in real time;

judging whether the communication state is normal, if so, capturing data by an analog/digital conversion unit in the micro module to obtain a capturing result and transmitting data by a digital/analog conversion unit to obtain a transmitting result, otherwise, stopping the operation;

based on the functional parameters of each component of the micro module, the grabbing result and the sending result, and combining the preset test machine and the functional program, static test and dynamic test are carried out on the micro module.

The invention is realized by the following technical scheme: firstly, according to test requirements and needs, developing a functional program for communication call through an IO port in the process of machine test based on an FPGA (programmable logic device), programming the FPGA program into a PROM (programmable memory unit) of a micro module through a JTAG interface before the machine test, loading the program into the FPGA of the micro module after the micro module is electrified, and calling by the FPGA, wherein the functional program is also the basis for realizing functions and measuring parameters. And establishing communication between a preset test machine and a programmable logic unit, wherein the preset test machine is a T800 test machine, capturing data through an analog-to-digital conversion unit and transmitting data through a digital-to-analog conversion unit under the condition that the communication state is normal, and verifying and testing and screening the functional performance of the micro-module system according to the functional parameters, capturing results and transmitting results of each component part in the micro-module by combining the T800 test machine and a developed functional program, wherein the functions realized by calling the performance of the test micro-module through the T800 test machine and the functional program include but are not limited to voltage and current setting, voltage and current detection, relay control, ADC (analog-to-digital conversion) signal input, DAC (digital-to-analog conversion) signal acquisition and FPGA communication. The invention solves the problem that the existing analog-digital hybrid system similar to the fiber-optic gyroscope signal processing micro-system lacks a test scheme.

In order to solve the problem that the existing miniaturized and precise analog-digital hybrid system lacks a test scheme, the invention provides a test system for a digital-analog hybrid micro module, which comprises: the device comprises a preset test machine table and a hardware resource configuration test unit, wherein the hardware resource configuration test unit is used for connecting each pin of the micro module to a resource board of the preset test machine table, and the resource board comprises a digital test channel board card, an analog test channel board card, a power channel board card and a control board card.

The one or more technical schemes provided by the invention have at least the following technical effects or advantages:

the invention provides a testing system and a testing method for a digital-analog hybrid micro-module aiming at an analog-digital hybrid system similar to a fiber-optic gyroscope signal processing micro-system, and solves the problem that the existing miniaturized and precise analog-digital hybrid micro-module lacks a testing scheme.

The invention provides a simple communication protocol between a T800 test machine and a micro-module programmable logic unit, and provides a thought for the interactive communication between a test platform and a modularized programmable logic unit.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;

FIG. 1 is a schematic flow chart of a testing method for a digital-analog hybrid micro-module according to the present invention;

FIG. 2 is a schematic diagram of a write data communication in the communication protocol of the present invention;

FIG. 3 is a schematic diagram of read data communication in the communication protocol of the present invention;

FIG. 4 is a schematic diagram of a connection between a micro-module and a T800 test machine in the present invention;

FIG. 5 is a schematic diagram of a T800 resource board according to the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than within the scope of the description, and the scope of the invention is therefore not limited to the specific embodiments disclosed below.

Example 1

Referring to fig. 1, fig. 1 is a flow chart of a testing method for a digital-analog hybrid micro module according to the present invention, which includes the following steps:

The specific embodiment of the invention is as follows: according to the test requirement and the need, based on FPGA (programmable logic device), developing the function program for communication call through IO port when testing the machine, programming the FPGA program into PROM (programmable memory unit) of the micro module through JTAG interface before testing the machine, loading the program into FPGA of the micro module after powering up the micro module, waiting for the FPGA call, this part is also the basis of realizing each function and measuring each parameter. And establishing communication between a preset test machine and a programmable logic unit, wherein the preset test machine is a T800 test machine, capturing data through an analog-to-digital conversion unit and transmitting data through a digital-to-analog conversion unit under the condition that the communication state is normal, and verifying and testing and screening the functional performance of the micro-module system according to the functional parameters, capturing results and transmitting results of each component part in the micro-module by combining the T800 test machine and a developed functional program, wherein the functions realized by calling the performance of the test micro-module through the T800 test machine and the functional program include but are not limited to voltage and current setting, voltage and current detection, relay control, ADC (analog-to-digital conversion) signal input, DAC (digital-to-analog conversion) signal acquisition and FPGA communication. The invention solves the problem that the existing analog-digital hybrid system similar to the fiber-optic gyroscope signal processing micro-system lacks a test scheme.

The invention can obtain the test thought and test method of each functional parameter based on the micro module composed of the programmable logic unit and the analog-to-digital conversion unit.

Referring to fig. 2 and 3, fig. 2 is a schematic diagram of data writing communication in the communication protocol of the present invention, and fig. 3 is a schematic diagram of data reading communication in the communication protocol of the present invention, where the method for establishing communication between the T800 test machine and the programmable logic unit includes:

defining a communication protocol between the T800 test machine and the programmable logic unit;

the communication protocol comprises 4-bit logic control bits, 1-bit data response bits and 14-bit data/address data bits, wherein the 4-bit logic control bits are respectively a first logic control bit, a second logic control bit, a third logic control bit and a fourth logic control bit;

detecting and acquiring the first level states of the first logic control bit and the second logic control bit, judging whether communication is started between the T800 test machine and the programmable logic unit or not based on the first level states, if so, detecting and acquiring the second level states of the third logic control bit and the fourth logic control bit, and if not, continuing to detect;

judging the communication type between the T800 test machine and the programmable logic unit based on the second level state, and judging the communication type as data writing if the level of the third logic control bit and the level of the fourth logic control bit in the second level state are pulled down; if the level of the third logic control bit is unchanged in the second level state and the level of the fourth logic control bit is pulled down, judging that the communication type is read data;

when the communication type is judged to be writing data, sequentially sending first address data and first data in a first preset period, detecting and obtaining a third level state of the data response bit and writing data corresponding to the data/address data bit, judging whether the third level state is high or not and whether the writing data is consistent with the first data or not, and judging that the writing data operation is successful if the third level state is high and the writing data is consistent with the first data;

and when the communication type is judged to be the read data, sequentially sending second address data and second data in a second preset period, detecting and acquiring a fourth level state of the data response bit, judging whether the fourth level state is high, if so, judging that the read data operation is successful, and if not, judging that the read data operation fails.

The system only needs to operate through the FPGA of the programmable logic unit to read and write the self-defined address so as to achieve the purposes of calling the corresponding FPGA program and checking whether the call is successful, so that standard 12C or serial port communication is not used, but a simple communication protocol is self-defined, and because for a T800 test machine, the bottom layer lacks the serial port communication protocol, the self-defined communication protocol not only realizes the communication between the T800 test machine and the FPGA, but also has the advantages of simplicity and convenience, and provides a thought for the interactive communication between the existing test platform and the modularized programmable logic unit. The protocol includes 4 bits of logic control bits (CLK, trig, CS, WEN), 1 bit of FPGA response bits (Valid) and 14 bits of data/address data (bits 0-13). The machine realizes the communication between the machine and the FPGA by setting a test vector (pattern) and running the pattern.

The logic control bit is held high until communication begins, with the other bits being in a high impedance state. From the Trig bit pulling low, the communication formally starts. Trig is pulled high after one CLK is pulled down at the falling edge of CLK, after waiting for 3 CLKs, CS and WEN are simultaneously pulled down at the falling edge of low CLK, at the moment, the machine starts to send address data to the FPGA, the machine is completed in 1 CLK, and then the next CLK machine starts to send data. After the steps are completed and 3 CLKs are waited, if the response bit Valid of the FPGA is pulled high after the communication is successful, the FPGA keeps sending a fixed data state, and the data is consistent with the writing. Therefore, the Valid bit and bit 0-bit 13 can be detected and judged at the rising edge of the 4 th CLK in the program, so as to judge whether the register writing operation is successful or not, and if the Valid level of the data response bit is high and the data corresponding to the bit 0-bit 13 is consistent with the transmitted data, the register writing operation is judged to be successful.

The logic control bit is held high until communication begins, with the other bits being in a high impedance state. From the trig bit pulling low, the communication formally begins. Trig is pulled high after one CLK is pulled down on the falling edge of CLK, after waiting for 3 CLK, CS is pulled down on the falling edge of low CLK as well, WEN is kept at high level, at this time, the machine starts to send address data to FPGA, and is completed in 1 CLK. After the steps are completed and 3 CLKs are waited, if the communication success FPGA response bit Valid is pulled high, the FPGA keeps sending a fixed data state. Therefore, the Valid bit can be detected and judged at the rising edge of the 4 th CLK in the program, so as to judge whether the read register operation is successful or not, and if the Valid level of the data response bit is high, the read register operation is judged to be successful, and bit 0-bit 13 is the read data.

The method comprises the steps of grabbing a packet by an analog-to-digital conversion unit:

s1: sending write address 0X11 and data 0X01 commands to the programmable logic unit, and entering an analog-to-digital conversion test mode after successful communication;

s2: sending a write address 0X1B, data 0X01 command to the programmable logic unit, and grabbing output data of the analog-to-digital conversion unit by the programmable logic unit after successful communication;

s3: the T800 test machine station sends a read address 0X1D command to the programmable logic unit, and after successful communication, the programmable logic unit sends a 0X01 command to the T800 test machine station;

s4: the T800 test machine station sends write address 0X10 and data 0X0 commands to the programmable logic unit, and the programmable logic unit stops grabbing data operation after receiving the commands;

s5: the T800 test machine station sends a write address 0X1C, data 0X 0-0X 3FFFF command to the programmable logic unit, the T800 test machine station sends a read address 0X1E command to the programmable logic unit after communication is successful, and the programmable logic unit stores the captured data to the T800 test machine station after communication is successful.

The analog-to-digital conversion unit ADC packet capturing step specifically comprises the following steps:

s1: and sending write address 0X11 and data 0X01 commands to the FPGA, and entering an ADC test mode after communication is successful (the FPGA returns high Valid after receiving the command and sends the same data to the machine station, and the machine station judges whether the communication command is normally executed according to the Valid and the high and low data level).

S2: and sending a write address 0X1B, data X01 command to the FPGA, starting the FPGA to grasp ADC output data after successful communication, wherein the data amount grasped at one time can be configured in the FPGA according to requirements and is limited by the memory capacity of the FPGA (16384 data amounts are used for carrying out subsequent method description).

S3: the machine station sends a reading address 0X1D command to the FPGA, and after the communication is successful, the FPGA sends data 0X01 to the machine station, which indicates that the data quantity grabbed by the FPGA reaches a set value at the moment, and the package grabbing is completed.

S4: after the packet grabbing is finished, the machine station sends commands of writing address 0X10 and data 0X0 to the FPGA, and the FPGA stops the packet grabbing operation after receiving the commands.

S5: the machine station sends a write address 0X1C, data 0X 0-0X 3FFFF command to the FPGA, and then sends a read address 0X1E command to the FPGA, and after the write address 0X1E command is successful, the FPGA stores 0-16383 data into a machine station memory for subsequent data processing. Because the machine station sends an instruction and runs a pattern (test vector), and because the data volume is large, the pattern can only be written manually, the data bit is set to be dynamic, and the pattern value of a fixed row in the same pattern can be changed according to a given data value in the T800 program, so that the workload of writing the pattern is greatly reduced.

The method comprises the following steps of data transmission of a digital-to-analog conversion unit:

m1: sending write address 0X11 and data 0X02 commands to the programmable logic unit, and entering a digital-to-analog conversion test mode after successful communication;

m2: sending write address 0X12 and data 0X 0-0X 3 commands to the programmable logic unit, and entering an input signal selection mode after communication is successful;

m3: and sending write address 0X10 and data 0X1 commands to the programmable logic unit, and sending data by the programmable logic unit to the digital-to-analog conversion unit after successful communication.

The data transmission step of the digital-to-analog conversion unit specifically comprises the following steps:

m1: and sending write address 0X11 and data 0X02 commands to the FPGA, and entering a DAC test mode after communication is successful.

M2: sending write address 0X12 and data 0X 0-0X 3 commands to the FPGA to enter different input signal selection modes, wherein data 0X0 represents that the transmission data is 0X0, and 0X1 represents that the transmission data is 0X3FFFF;0X2 represents that the transmitted data is a step wave, the step value, the dotting number of each step and the dotting frequency can be configured by increasing from 0X0 to 0X3FFF by a step X, and before a signal is transmitted, a command is transmitted to the FPGA, and the FPGA can automatically perform configuration; data 0X3 represents a transmission 1M sine wave.

M3: and sending write address 0X10 and data 0X1 commands to the FPGA, entering the mode, and starting the FPGA to send data to the DAC.

Wherein performing a static test on the micro-module comprises:

after the micro module is powered on, a first IO interface used for testing vector communication between the preset test machine and the programmable logic unit is obtained;

setting an input high-level voltage of the first IO interface as a specified lower limit value, setting an input low-level voltage as a specified upper limit value, setting an output high-level threshold voltage as a specified lower limit value, and setting an output low-level threshold voltage as a specified upper limit value;

setting the input high-level voltage of other IO interfaces as a specified lower limit value based on the preset test machine;

the preset test machine sends write address 0X30 and data 0X02 commands to the programmable logic unit, the programmable logic unit judges whether the input voltage values of other IO interfaces are high level after communication is successful, if yes, the preset test machine sends read address 0X30 commands to the programmable logic unit, monitors whether the data response bit level is raised, and if yes, judges that the input high level voltage of the programmable logic unit is set to be effective.

The static test of the micro module is specifically as follows:

FPGA inputs high level Voltage (VIH): VCC is increased by 5V, VIH of the platform and FPGA communication pattern is set as a lower limit value specified by a data manual, VIL is set as a upper limit value specified by a data manual, VOH threshold is set as a lower limit value specified by the data manual, and VOL threshold is set as an upper limit value specified by the data manual. Other IO ports apply a lower limit voltage value regulated by VIH through a machine, the machine sends write address 0X30 and data 0X02 commands to the FPGA, after communication is successful, the FPGA judges input voltages of other IO ports, whether the voltage values are high level is detected, if the voltage values are high level, the machine waits for 5 CLK and then sends read address 0X30 commands to the FPGA, and then 3 CLK and then monitors whether Valid is pulled high, if so, the FPGA judges that VIH is set to be effective.

The following static tests were also performed on the micromodules:

FPGA outputs a high level Voltage (VOH): VCC is increased by 5V, the VOH threshold value of the pattern corresponding to the machine and the FPGA communication pin is set to be a lower limit value specified by a data manual, the VOL threshold value is set to be a upper limit value specified by the data manual, and the VIH is set to VCC and the VIL is set to be 0V. The machine station sends a write address 0X30 and a data 0X01 command to the FPGA, and the FPGA calls a VOH test program to enter a VOH test mode. The FPGA configures an IO port to be tested into an LVTTL (low voltage logic) output mode, pulls up a specified load current at the tested IO port at the moment, and then measures the voltage value at the moment to be VOH.

FPGA outputs a low level Voltage (VOL): VCC is increased by 5V, the VOH threshold value of the pattern corresponding to the machine and the FPGA communication pin is set to be a lower limit value specified by a data manual, the VOL threshold value is set to be a upper limit value specified by the data manual, and the VIH is set to VCC and the VIL is set to be 0V. The machine station sends address 0X30 and data 0X00 to the FPGA, and the FPGA calls a VOL test program to enter a VOL test mode. The FPGA configures an IO port to be tested into an LVTTL (Low Voltage logic) output mode, a specified load current is poured on the tested IO port at the moment, and then the voltage value at the moment is measured to be VOL.

FPGA inputs a low level Voltage (VIL): VCC is increased by 5V, VIH of the platform and FPGA communication pattern is set as a lower limit value specified by a data manual, VIL is set as a upper limit value specified by a data manual, VOH threshold is set as a lower limit value specified by the data manual, and VOL threshold is set as an upper limit value specified by the data manual. Other IO ports apply VIL regulated upper limit voltage values through a machine, the machine sends write address 0X30 and data 0X03 commands to the FPGA, after communication is successful, the FPGA judges input voltages of other IO ports, whether the voltage values are low level is detected, if yes, the machine waits for 5 CLK to send read address 0X30 commands to the FPGA, and then 3 CLK to monitor whether Valid is pulled up, if yes, the FPGA judges that VIL is Valid, and therefore the VIL voltage value is verified.

Built-in LDO outputs 1.5V: VCC is added with 5V, and the voltage value of the output end of the LDO 1.5V is measured.

Built-in LDO outputs 3.3V: VCC is added with 5V, and the voltage value of the 3.3V output end of the LDO is measured.

The RS485 driver inputs high (VIH): VCC is added with 5V, the voltage of the input end of the RS485 is increased from 0.78V to 2.03V in a step by 10mV, the voltage OUT of the output end is monitored on each step, and when the OUT is changed from low to high, the input voltage value at the moment is recorded to be VIH.

The RS485 driver inputs low (VIL): VCC is added with 5V, the voltage of the input end of the RS485 is reduced to 0.78V from 2.03V by taking 10mV as one step, meanwhile, the voltage OUT of the output end is monitored on each step, and when the OUT is changed from high to low, the input voltage value at the moment is recorded to be VIL.

RS485 driver differential output Voltage (VOD): the load resistor is connected between the positive electrode and the negative electrode of the differential output of the driver through the relay, VCC is added with 5V, the input end of the RS485 driver is added with 3V voltage, and the differential voltage difference between the positive electrode and the negative electrode of the differential output at the moment is measured to be VOD.

RS485 driver common mode output Voltage (VOC): the other end of the load resistor is connected with an HDM resource in parallel. VCC adds 5V, and RS485 driver input adds 3V voltage, and the voltage value on this HDM resource is the VOC at this moment of measurement test.

RS485 receiver positive differential threshold voltage (vth+): VCC is added with 5V, the input positive electrode of the receiver is gradually increased to 0.13V from-0.13V in steps of 1mV, meanwhile, the negative electrode is gradually decreased to-0.13V in steps of 1mV from 0.13V, the voltage value of the output end of the receiver is monitored on each step in real time, and when the output voltage is changed from low to high, the voltage difference between the positive electrode and the negative electrode is recorded as VTH+.

RS485 receiver negative differential threshold voltage (VTH-): VCC is added with 5V, the input positive electrode of the receiver is gradually decreased from 0.13V to-0.13V in a step of 1mV, meanwhile, the negative electrode is gradually increased from-0.13V to 0.13V in a step of 1mV, the voltage value of the output end of the receiver is monitored on each step in real time, and when the output voltage is changed from high to low, the voltage difference between the positive electrode and the negative electrode is VTH-.

The RS485 receiver outputs a high Voltage (VOH): VCC is added with 5V, a voltage value with the voltage difference of 0.2V is applied between the positive electrode and the negative electrode of the receiver input, and the voltage of the output end of the receiver at the moment is measured to be VOH.

The RS485 receiver outputs a low Voltage (VOL): VCC is added with 5V, a voltage value with the voltage difference of-0.2V is applied between the positive electrode and the negative electrode of the receiver input, and the voltage of the output end of the receiver at the moment is measured to be VOL.

ADC reference output Voltage (VREFADC): VCC is added with 5V, an ADC SENSE (monitoring power supply output voltage) pin is connected with 0V to adopt an internal 1V reference, a MODE pin is connected with 0V, and the voltage on an ADC VREF pin is measured to be VREFADC.

ADC zero error/offset error (E0 ADC): VCC adds 5V, the benchmark selects an internal 1V benchmark, 0V voltage is added at the input end of the ADC, the machine station sends a packet grabbing instruction to the FPGA, and after the grabbed 2-system data are converted into 10-system data, the E0ADC can be obtained by the formula E0= (max (data) -16384)/16384 by 100%.

ADC fullness Error (EGADC): VCC adds 5V, the benchmark selects an internal 1V benchmark, span voltage 2V is added at the input end of the ADC, the machine station sends a packet grabbing instruction to the FPGA, and after the grabbed 2-system data are converted into 10-system data, the EGADC can be obtained by the formula E0= (max (data) -16384)/16384 x 100%.

ADC differential nonlinear error (DNLADC): VCC adds 5V, the benchmark selects the internal 1V benchmark, the ADC differential input end is connected with ADU board card AWG resource, a zero-to-full range oblique wave is created by setting parameters such as AWG initial level, dotting frequency, common mode voltage value and the like through T800 program, T800 repeatedly transmits the oblique wave with fixed frequency until the oblique wave is actively closed, in the process, a machine station transmits a packet grabbing instruction to the FPGA, and after the grabbed data is converted into 10 scale, DNL calculation is started. Here, 2 manners of calculating DNL are provided, the first is to directly make a difference between the front data and the rear data and then subtract the theoretical difference value, and the maximum value of the absolute value of the value is DNL; the second is to directly process the data by using a T800 packing function and calculate DNL by adopting a code density mode, but the method needs to acquire the data quantity of multiple periods as much as possible. The appropriate calculation mode can be selected according to actual requirements, and the invention is not particularly limited.

ADC integral nonlinear error (INLADC): the INL is based on a DNL calculation method, which comprises 2 calculation methods, wherein the first calculation method is that after DNL is obtained by taking difference between front and rear data, the INL is obtained by adopting an integral summation method, and the value with the largest absolute value is the wanted value; the second is to directly process the data by using a T800 packing function, and calculate INL by adopting a code density mode. The appropriate calculation mode can be selected according to actual requirements, and the invention is not particularly limited.

DAC zero error/offset error (E0 DAC): VCC adds 5V, enters into DAC test mode, selects FPGA to send 0X0, and measures voltage value of DAC output end at this time.

DAC fullness Error (EGDAC): VCC adds 5V, enters into DAC test mode, selects FPGA to send 0X3FFF, and measures voltage value of DAC output end at this time.

DAC differential/integral nonlinear error (DNLDAC/INLDAC): VCC is added with 5V, a DAC test mode is entered, the FPGA is selected to send 0X 0-0X 3FF ladder waves, an ADU DGT board card is adopted to collect DAC differential output voltage, and the DAC differential output voltage is stored in a memory for subsequent testing. The dotting frequency of the FPGA is set to be 10MHz, and the steps are 0X1; the dotting frequency is set to be 100MHz when the DAC output is acquired, and the sampling point number is 163840 points. After the data are acquired, the average value of every 10 points is calculated, 16384 data are finally obtained, and INL and DNL values are directly obtained by processing the data through a T800 function.

Wherein dynamically testing the micro-module comprises:

after the micro module is powered up, entering the analog/digital conversion test mode;

the T800 test machine station sends a first preset sine wave, grabs first output data of the analog-to-digital conversion unit and stores the first output data in a memory;

and calling a corresponding first packing function in the T800 test machine, and calculating the values of the signal-to-noise ratio, the signal-to-noise ratio distortion, the total ramp distortion and the spurious-free dynamic range of the analog-to-digital conversion unit based on the first packing function and the first output data.

The dynamic test of the micro module is specifically as follows:

ADC signal-to-noise ratio (SNRAD), signal-to-noise ratio distortion (SINAD), total ramp distortion (THDAD), spurious Free Dynamic Range (SFDRAD): VCC is added with 5V, an ADC test mode is entered, T800 sends 0-2V sine wave, ADC output data is grabbed and stored in a memory, T800 has corresponding packing functions for dynamic parameter tests of the ADC and the DAC, and SNRAD, SINAD, THDAD, SFDRAD can be calculated by directly calling a program.

Wherein dynamically testing the micro-module further comprises:

after the micro module is powered up, entering a digital-to-analog conversion test mode;

the programmable logic unit selects and inputs a second preset sine wave and collects second output data in a third preset number period of the digital-analog conversion unit;

and calling a second packing function corresponding to the T800 test machine, and calculating the values of the signal-to-noise ratio, the signal-to-noise ratio distortion, the total ramp distortion and the spurious-free dynamic range of the digital-to-analog conversion unit based on the second packing function and the second output data.

The dynamic test of the micro module is specifically as follows:

DAC signal-to-noise ratio (SNRDA), signal-to-noise ratio distortion (SINDA), total ramp distortion (THDDA), spurious free dynamic range (SFDTDA): VCC is added with 5V, a DAC test mode is entered, an ADC input waveform is selected to be a 1MHz sine wave, 20 cycles of ADC output data are collected, and a value of SNRDA, SINDA, THDDA, SFDRDA is directly calculated through a T800 packing function.

Example two

Referring to fig. 4 and 5, fig. 4 is a schematic diagram of connection between a micro module and a T800 test machine in the present invention, and fig. 5 is a schematic diagram of a T800 resource board in the present invention, where the micro module includes a programmable logic unit FPGA, a programmable memory unit PROM, an erasable programmable memory unit EEPROM, an analog/digital conversion unit ADC, a digital/analog conversion unit DAC, a data interface unit RS485, and a power supply unit LDO, the test system includes a T800 test machine and a hardware resource configuration test unit, and the hardware resource configuration test unit is configured to connect each pin of the micro module to a resource board of the T800 test machine, where the resource board includes a digital test channel board HDM, an analog test channel board ADU, a power supply channel board SMU, and a control board UTP.

The power supply unit input end is connected with the resources of the power supply channel board card, the analog/digital conversion unit data input end is connected with the waveform generator resources of the analog test channel board card, the digital/analog conversion unit data output end is connected with the waveform collector resources of the analog test channel board card, the data interface unit input end is connected with the resources of the digital test channel board card, and the programmable logic unit is connected with the resources of the digital test channel board card.

The micro module is specifically connected with the T800 resource as follows:

LDO (Low dropout regulator): the 5V power input end is connected with SMU board card resources, and because all part of power-on power supplies in the micro-module are provided by LDO, the maximum current capacity of the SMU board card under single channel 5V is considered to be 250mA, the maximum power supply current required in the testing process is obtained when the resources are distributed, and if the maximum power supply current exceeds the range, a plurality of continuous channel SMU resources on the same board card are required to be used in parallel so as to improve the maximum current capacity.

ADC: the data input terminal is connected with ADU board card AWG (Arbitrary waveform generator) resource, and various desired waveforms are added into the input terminal by AWG setting, and single-ended or differential signals can be provided. The signal frequency ranges from 8KSPS to 200MSPS in the 16-bit mode and from 128KSPS to 192KSPS in the 24-bit mode, and a proper mode can be selected according to the needs. Besides the power supply pins are powered by the internal LDO, other pins have no large current and large voltage, and can be directly connected with HDM board card resources. The HDM board card has a voltage range of-1.5V to 6.5V and a current range of 50mA, and can provide and monitor voltage and current. Each HDM board card has 64 channel resources, the number of the boards can be increased according to the requirement, and the system is built based on a 512 channel HDM resource platform.

DAC: the data output end is connected with ADU board DGT (waveform collector) resource, can collect DAC output end voltage value in real time, can collect single-ended or differential signal equally, the dotting effective digit and frequency range are identical with AWG resource. Pins on the remaining periphery that need to be powered up or detect voltage and current are also directly connected to the HDM board resources.

RS485: because the part of pins have no large current or voltage, the driving/receiving input end can be directly connected to the HDM board card resource, and the driving/receiving output end can be connected to the corresponding resistor and capacitor according to the test requirement and then connected to the HDM board card resource.

And (3) FPGA: CLK is provided by an external active crystal oscillator, and may also be generated using an ADU board, with other IO ports connected to the HDM board. The FPGA and the machine can communicate through the FPGA IO port and HDM board card resource, the communication protocol can be defined according to the requirement, and the IO port is not limited by quantity, so that the method is very convenient.

The testing system further comprises a relay unit, wherein the relay unit is used for switching a plurality of circuits connected with a single pin in the micro module, and the relay unit is connected with the resource of the control board card.

In the system, a single pin is connected with various peripheral circuits, all the peripheral circuits are switched by a relay, relay control resources are connected to UTP board card resources, 5V resources are directly provided by T800 5V resources, and a disposable fuse is connected in series to prevent short circuit.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A test method for a digital-analog hybrid micro-module, comprising the steps of:

based on the functional parameters of each component part of the micro module, the grabbing result and the sending result, combining the preset test machine and the functional program to perform static test and dynamic test on the micro module;

establishing communication between the preset test machine and the programmable logic unit comprises:

defining a communication protocol between the preset test machine and the programmable logic unit;

detecting and acquiring the first level states of the first logic control bit and the second logic control bit, judging whether communication is started between the preset test machine and the programmable logic unit or not based on the first level states, if so, detecting and acquiring the second level states of the third logic control bit and the fourth logic control bit, and if not, continuing to detect;

judging the communication type between the preset test machine and the programmable logic unit based on the second level state, and judging the communication type as write data if the level of the third logic control bit and the level of the fourth logic control bit in the second level state are pulled down; if the level of the third logic control bit is unchanged in the second level state and the level of the fourth logic control bit is pulled down, judging that the communication type is read data;

2. The method for testing a digital-analog hybrid micro-module according to claim 1, wherein the method comprises the steps of an analog-to-digital conversion unit packet capturing:

s3: the preset test machine station sends a read address 0X1D command to the programmable logic unit, and after successful communication, the programmable logic unit sends a 0X01 command to the preset test machine station;

s4: the preset test machine station sends write address 0X10 and data 0X0 commands to the programmable logic unit, and the programmable logic unit stops grabbing data operation after receiving the commands;

s5: the preset test machine station sends a write address 0X1C, data 0X 0-0X 3FFFF command to the programmable logic unit, the preset test machine station sends a read address 0X1E command to the programmable logic unit after communication is successful, and the programmable logic unit stores the captured data to the preset test machine station after communication is successful.

3. The method for testing a digital-analog hybrid micro module according to claim 1, wherein the method comprises the step of transmitting the data of the digital-analog conversion unit:

4. The method of claim 1, wherein performing static testing on the micro-module comprises:

5. The method of testing a digital-analog hybrid micro-module of claim 2, wherein dynamically testing the micro-module comprises:

the preset test machine station sends a first preset sine wave, grabs first output data of the analog-to-digital conversion unit and stores the first output data in a memory;

and calling a corresponding first packing function in the preset test machine, and calculating the values of the signal-to-noise ratio, the signal-to-noise ratio distortion, the total ramp distortion and the spurious-free dynamic range of the analog-to-digital conversion unit based on the first packing function and the first output data.

6. A test method for a digital-analog hybrid micro-module according to claim 3, wherein dynamically testing the micro-module further comprises:

the programmable logic unit selects and inputs a second preset sine wave and collects second output data in a first preset number period of the digital-analog conversion unit;

and calling a second packing function corresponding to the preset test machine, and calculating the values of the signal-to-noise ratio, the signal-to-noise ratio distortion, the total ramp distortion and the spurious-free dynamic range of the digital-to-analog conversion unit based on the second packing function and the second output data.

7. A test system for a digital-analog hybrid micro-module, the micro-module comprising a programmable logic unit, a programmable memory unit, an erasable programmable memory unit, an analog-to-digital conversion unit, a digital-to-analog conversion unit, a data interface unit and a power supply unit, characterized in that the test system comprises a pre-set test station and a hardware resource configuration test unit for connecting individual pins of the micro-module to a resource board of the pre-set test station, the resource board comprising a digital test channel board, an analog test channel board, a power channel board and a control board, the test system implementing the steps of the test method for a digital-analog hybrid micro-module as claimed in any one of claims 1-6 when performing the test.

8. The test system for a digital-analog hybrid micro-module of claim 7, wherein the power supply unit input is connected to the resources of the power channel board, the analog-to-digital conversion unit data input is connected to the waveform generator resources of the analog test channel board, the digital-to-analog conversion unit data output is connected to the waveform collector resources of the analog test channel board, the data interface unit input is connected to the resources of the digital test channel board, and the programmable logic unit is connected to the resources of the digital test channel board.

9. The test system for a digital-to-analog hybrid micro-module of claim 7, further comprising a relay unit for switching a plurality of circuits connected by a single pin in the micro-module, the relay unit being connected to a resource of the control board card.