CN113488101B - System for testing drive capability of NOR Flash chip and electronic equipment - Google Patents
System for testing drive capability of NOR Flash chip and electronic equipment Download PDFInfo
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Abstract
The present disclosure provides a testing system and an electronic device for NOR Flash chip driving capability, wherein the testing system for NOR Flash chip driving capability includes: the device comprises a processor module, a data storage module, a program-controlled voltage module, a DUT module, a positive and negative pressure module and a DC measurement module, wherein the processor module comprises an MCU chip and an FPGA chip, the MCU chip is respectively connected with the data storage module, the FPGA chip, the program-controlled voltage module, the DUT module and the positive and negative pressure module, and the FPGA chip is connected with the DC measurement module; the DUT module is respectively connected with the DC measurement module, the program control voltage module and the positive and negative pressure module. Therefore, the drive capability of the NOR Flash chip port can be quantitatively tested, and the adaptability of the NOR Flash chip to different board level environments is improved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a system for testing driving capability of a NOR Flash chip and an electronic device.
Background
With the continuous development of internet of things devices, data storage is becoming more and more important at present. A NOR Flash (nonvolatile Flash technology) chip is a nonvolatile memory using a charge and discharge mechanism, has a lifetime of 10 years or more, is very suitable as a storage medium for a start-up program, and is widely used in embedded devices.
For a NOR Flash chip, the same driving capability of a chip port may have different effects under different board-level environments and different usage environments. The driving capability is too small, and the board-level main control chip may not collect effective signals, so that communication abnormity is caused. The driving capability is too large, crosstalk may occur between adjacent signal lines, which causes abnormal inversion of the level and generates abnormal signals.
Disclosure of Invention
The present disclosure is directed to solving, at least to some extent, one of the technical problems in the above-described technology.
Therefore, an object of the present disclosure is to provide a NOR Flash chip driving capability testing system, which can perform a quantitative test on the driving capability of a NOR Flash chip port, and is helpful for improving the adaptability of the NOR Flash chip to different board level environments.
A second object of the present disclosure is to provide an electronic device.
In order to achieve the above object, an embodiment of the first aspect of the present disclosure provides a testing system for NOR Flash chip driving capability, including a processor module, a data storage module, a program-controlled voltage module, a DUT module, a positive/negative voltage module, and a DC measurement module, where the processor module includes an MCU chip and an FPGA chip, the MCU chip is connected to the data storage module, the FPGA chip, the program-controlled voltage module, the DUT module, and the positive/negative voltage module, respectively, and the FPGA chip is connected to the DC measurement module; the DUT module is respectively connected with the DC measurement module, the program-controlled voltage module and the positive and negative pressure module; the data storage module is used for storing first configuration information and first test information of the tested NOR Flash chip; the MCU chip is used for receiving a test command sent by a user, acquiring the first configuration information and the first test information from the data storage module according to the test command, and generating a voltage adjustment instruction and a positive and negative voltage control instruction according to the first configuration information and the first test information; the DUT module is used for loading the tested NOR Flash chip; the program-controlled voltage module is used for adjusting the test voltage of the NOR Flash chip to be tested according to the voltage adjusting instruction; the positive and negative pressure module is used for simulating different input and output states of a port of the NOR Flash chip to be tested according to the positive and negative pressure control instruction so as to construct a test environment; the DC measuring module is used for collecting a voltage signal of the port of the NOR Flash chip to be measured; and the FPGA chip is used for processing the voltage signal to generate a test result.
The testing system for the driving capability of the NOR Flash chip disclosed by the embodiment of the disclosure can be used for carrying out quantitative testing on the driving capability of the NOR Flash chip port, and is beneficial to improving the adaptability of the NOR Flash chip to different board-level environments.
In addition, the NOR Flash chip driving capability test system proposed according to the above embodiment of the present disclosure may further have the following additional technical features:
according to an embodiment of the present disclosure, the MCU chip is further configured to generate a first test instruction and a second test instruction according to the first configuration information and the first test information; the DUT module is further used for controlling the port of the NOR Flash chip to be tested to enter a state to be tested according to the first test instruction; and the FPGA chip is also used for controlling the FPGA chip to enter a test state according to the second test instruction.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: and the load module is connected with the program control voltage module and used for simulating load conditions under different circuits so as to construct an actual circuit environment of the port of the tested NOR Flash chip.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: and the display module is connected with the MCU chip, wherein the MCU chip is also used for sending the test result to the display module so as to provide the test result for a user through the display module.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: and the function selection module is connected with the MCU chip and used for sending the second configuration information and the second test information of the tested NOR Flash chip to the MCU chip.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: and the online module is connected with the MCU chip and is used for connecting other test systems.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: and the separator communication module is connected with the MCU chip and is used for communicating with a separator so as to place the tested NOR Flash chip into the test seat of the DUT module through the separator.
According to an embodiment of the present disclosure, the testing system for NOR Flash chip driving capability further includes: the upper computer communication module is connected with the MCU chip and is used for communicating with an upper computer; the MCU chip is also used for sending the voltage signal and the test result to the upper computer through the upper computer communication module.
In order to achieve the above object, a second aspect embodiment of the present disclosure provides an electronic device, which includes the NOR Flash chip driving capability test system of the first aspect embodiment of the present disclosure.
According to the electronic equipment provided by the embodiment of the disclosure, the drive capability of the NOR Flash chip port can be quantitatively tested through the test system of the drive capability of the NOR Flash chip, and the improvement of the adaptability of the NOR Flash chip to different board-level environments is facilitated.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
The foregoing and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to one embodiment of the present disclosure.
FIG. 2 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
FIG. 3 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
FIG. 4 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
FIG. 5 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
FIG. 6 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
FIG. 7 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to another embodiment of the present disclosure.
Fig. 8 is a block schematic diagram of an electronic device according to one embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.
A system for testing driving capability of a NOR Flash chip according to an embodiment of the present disclosure is described below with reference to the drawings.
FIG. 1 is a block diagram of a system for testing the driving capability of a NOR Flash chip according to an embodiment of the present disclosure.
As shown in fig. 1, a NOR Flash chip driving capability Test system 10000 according to an embodiment of the present disclosure includes a processor module 100, a data storage module 200, a program-controlled voltage module 300, a Device Under Test (DUT) module 400, a positive/negative voltage module 500, and a Direct Current (DC) measurement module 600.
The processor module 100 may include an MCU (Micro Control Unit) chip 110 and an FPGA (Field Programmable Gate Array) chip 120, wherein the MCU chip 110 is connected to the data storage module 200, the FPGA chip 120, the program-controlled voltage module 300, the DUT module 400 and the positive/negative voltage module 500, the FPGA chip 120 is connected to the DC measurement module 600, and the DUT module 400 is connected to the DC measurement module 600, the program-controlled voltage module 300 and the positive/negative voltage module 500.
In the embodiment of the present disclosure, the data storage module 200 is configured to store first configuration information and first test information of the NOR Flash chip to be tested. The data storage module 200 may be composed of a large-capacity NOR Flash chip and its accessory circuits.
Specifically, in the testing process, the data storage module 200 may receive first configuration information and first testing information (i.e., configuration and testing information of the tested NOR Flash chip) of the tested NOR Flash chip sent by a relevant worker, and store the first configuration information and the first testing information, so as to call the tested NOR Flash chip for use when testing the NOR Flash chip.
In the embodiment of the present disclosure, the DUT module 400 is used to load the tested NOR Flash chip.
The DUT module 400 may be a signal-group low-loss adapter socket for connecting test sockets of multiple packages, so as to achieve the purpose of compatibly testing IO (Input and Output) ports of multiple packages of NOR Flash.
Specifically, the NOR Flash chip under test may be loaded through the DUT module 400 before testing, e.g., the NOR Flash chip under test may be placed in a test socket to which the DUT module 400 is connected.
In the embodiment of the present disclosure, the MCU chip 110 is configured to receive a test command sent by a user, acquire first configuration information and first test information from the data storage module 200 according to the test command, and generate a voltage adjustment instruction and a positive/negative voltage control instruction according to the first configuration information and the first test information.
Specifically, during testing, a user may send a test command to the MCU chip 110 through the upper computer, and after receiving the test command, the MCU chip 110 may obtain first configuration information and first test information from the data storage module 200 according to the test command, generate a voltage adjustment command and a positive/negative voltage control command according to the first configuration information and the first test information, and then send the voltage adjustment command and the positive/negative voltage control command to the program-controlled voltage module 300 and the positive/negative voltage module 500, respectively.
Note that the upper Computer described in this embodiment may be a PC (Personal Computer) Computer, a server, or the like. In the embodiment of the present disclosure, the program-controlled voltage module 300 is configured to adjust a test voltage of the NOR Flash chip under test according to the voltage adjustment instruction.
The program-controlled voltage module 300 may be composed of a plurality of DC-DC chips, an operational amplifier, and an 8-bit MCU, and is mainly used to provide a stable voltage for the test system 10000 for the NOR Flash chip driving capability, and to provide a linear controllable operating voltage (i.e., a test voltage) for the tested NOR Flash chip in the DUT module 400.
Specifically, during the testing process, the MCU chip 110 may send a voltage adjustment command to the program-controlled voltage module 300, and after receiving the voltage adjustment command, the program-controlled voltage module 300 may perform linear adjustment on the test voltage of the NOR Flash chip to be tested according to the voltage adjustment command.
In the embodiment of the present disclosure, the positive/negative voltage module 500 is configured to simulate different input/output states of the tested NOR Flash chip port according to the positive/negative voltage control instruction, so as to construct a test environment.
The positive/negative voltage module 500 may be composed of a plurality of LDOs (Low Dropout regulators) to generate positive and negative voltages, and may implement the operations of current sinking and discharging to the tested NOR Flash chip during the test process to create actual test conditions.
Specifically, in the testing process, the MCU chip 110 may send a positive/negative voltage control instruction to the positive/negative voltage module 500, and the positive/negative voltage module 500 may generate a positive voltage or a negative voltage according to the positive/negative voltage control instruction after receiving the positive/negative voltage control instruction, so as to realize current sinking or discharging of the NOR Flash chip in the testing process, thereby simulating different input/output states of the tested NOR Flash chip port to construct a testing environment.
In the embodiment of the present disclosure, the DC measurement module 600 is configured to collect a voltage signal of a port of a NOR Flash chip to be tested. The DC measurement module 600 may be composed of an AD (Analog to Digital) conversion chip and an operational amplifier.
Specifically, during the test process, the DC measurement module 600 may collect a voltage signal of the port of the NOR Flash chip to be tested and send the voltage signal to the FFGA chip 120 for processing.
In the embodiment of the present disclosure, the FPGA chip 120 is configured to process the voltage signal to generate a test result.
Specifically, in the testing process, the DC measurement module 600 may send the collected voltage signal to the FPGA chip 120, and the FPGA chip 120 may process the voltage signal after receiving the voltage signal to generate a test result, and send the voltage signal and the test result to the MCU chip 110.
Further, in an embodiment of the present disclosure, the MCU chip 110 is further configured to generate a first test instruction and a second test instruction according to the first configuration information and the first test information, the DUT module 400 is further configured to control a port of the tested NOR Flash chip to enter a state to be tested according to the first test instruction, and the FPGA chip 120 is further configured to control the FPGA chip to enter a test state according to the second test instruction.
Specifically, during testing, the MCU chip 110 may generate the voltage adjustment instruction and the positive/negative voltage control instruction according to the first configuration information and the first test information, and simultaneously generate a first test instruction and a second test instruction, and send the first test instruction and the second test instruction to the DUT module 400 and the FPGA chip 120, respectively, after the DUT module 400 receives the first test instruction, the DUT module may control the port of the NOR Flash chip to be tested to enter the state to be tested according to the first test instruction, and after the FPGA chip 120 receives the second test information, the FPGA chip 120 may control the FPGA chip 120 to enter the test state according to the second test instruction.
In an embodiment of the disclosure, as shown in fig. 2, a NOR Flash chip driving capability test system 10000 may further include: and a load module 700, wherein the load module 700 is connected to the program-controlled voltage module 300, and the load module 700 is used for simulating load conditions under different circuits to construct an actual circuit environment of the tested NOR Flash chip port. The load module 700 may be composed of multiple sets of capacitors and resistors.
Specifically, in the test process, the load module 700 can be used to change the circuit load of the test system 10000 for the NOR Flash chip driving capability, so as to simulate the load conditions under different circuits, construct the actual circuit environment of the tested NOR Flash chip port, and achieve better test effect.
In an embodiment of the disclosure, as shown in fig. 3, a NOR Flash chip driving capability test system 10000 may further include: and a display module 800, wherein the display module 800 is connected to the MCU chip 110, and wherein the MCU chip 110 is further configured to transmit the test result to the display module 800, so as to provide the test result to the user through the display module 800.
The display module 800 may include an LED (Light Emitting Diode) screen and an auxiliary circuit for displaying the related test information.
Specifically, after the NOR Flash chip is tested by the NOR Flash chip driving capability testing system 10000, the testing result can be sent to the display module 800 through the MCU chip 110, and the testing result is displayed on the LED screen of the display module 800.
In an embodiment of the disclosure, as shown in fig. 4, a NOR Flash chip driving capability test system 10000 may further include: and the function selection module 900, wherein the function selection module 900 is connected to the MCU chip 110, and is configured to send the second configuration information and the second test information of the tested NOR Flash chip to the MCU chip 110.
The function selection module 900 may be composed of a plurality of dial switches, and is mainly used for performing manual testing when the upper computer is not controlled.
Specifically, under the condition that the test system 10000 for the driving capability of the NOR Flash chip is out of the control of the upper computer, the second configuration information and the second test information of the NOR Flash chip to be tested can be manually set through the function selection module 900, and can be sent to the MCU chip 110, and after receiving the second configuration information and the second test information, the MCU chip 110 can generate a related instruction according to the second configuration information and the second test information to test the progress of the driving capability of the port of the NOR Flash chip to be tested.
In an embodiment of the disclosure, as shown in fig. 5, a NOR Flash chip driving capability test system 10000 may further include: and the online module 1000, wherein the online module 1000 is connected to the MCU chip 110 and is used for connecting to other test systems. The online module 1000 may be composed of a set of chip selection interfaces and communication interfaces.
Specifically, the NOR Flash chip driving capability test system 10000 can be connected to other test systems through a connection interface and a communication interface in the online module 1000 for expansion, so as to realize multi-system linkage test or batch test.
In an embodiment of the disclosure, as shown in fig. 6, a NOR Flash chip driving capability test system 10000 may further include: a sorter communication module 1100, wherein the sorter communication module 1100 is connected to the MCU chip 110 for communicating with a sorter to place the tested NOR Flash chip into the test socket of the DUT module 400 through the sorter.
The sorter communication module 1100 may include a plurality of level shifter chips, and is mainly used for communicating with a sorter through TTL (Transistor Logic level) signals to perform a batch test.
Specifically, in the test preparation stage, the MCU chip 110 can send a sorting control command to the sorter through the sorter communication module 1100, and after receiving the sorting control command, the sorter can put the tested NOR Flash chip into the test socket of the DUT module 400 according to the sorting control command for subsequent testing.
In an embodiment of the disclosure, as shown in fig. 7, a NOR Flash chip driving capability test system 10000 may further include: and the upper computer communication module 1200, wherein the upper computer communication module 1200 is connected with the MCU chip 110 and used for communicating with an upper computer. The MCU chip 110 is further configured to send the voltage signal and the test result to an upper computer through the upper computer communication module 1200.
Specifically, after the test is finished, the MCU chip 110 may send a voltage signal and a test result to the upper computer through the upper computer communication module 1200, and the upper computer may perform related analysis and processing according to the voltage signal and the test result after receiving the voltage signal and the test result.
In summary, the NOR Flash chip driving capability test system of the embodiment of the present disclosure may have the following beneficial effects: the driving capability of NOR Flash chip port can be tested high-efficiently to different circuit environment, can quantify the actual drive effect of chip, acquire the accurate driving capability data of chip, this driving capability data can assist chip design and volume production, promote the practical compatibility of chip, avoid design emulation data and actual circuit environmental deviation too big, cause negative effects for in-service use.
The testing process of the testing system for the driving capability of the NOR Flash chip of the embodiment of the disclosure is as follows: before the test is started, a NOR Flash chip is loaded through a DUT module, after the loading is finished, a user can send a test command to an MCU chip through an upper computer, the MCU chip receives the test command, acquires first configuration information and first test information from a data storage module according to the test command, generates a voltage regulation instruction and a positive and negative voltage control instruction according to the first configuration information and the first test information, respectively sends the voltage regulation instruction and the positive and negative voltage control instruction to a program control voltage module and a positive and negative pressure module, then the program control voltage module regulates output voltage according to the voltage regulation instruction, the positive and negative pressure modules generate positive pressure or negative pressure according to the positive and negative pressure control instruction to construct a test environment, at the moment, a DC measurement module can collect a voltage signal of a port of the tested NOR Flash chip and send the voltage signal to the FPGA chip, the FPGA chip processes the voltage signal to generate a test result, and sends the voltage signal and the test result to the MCU chip, and then the MCU chip sends the test result to a display module for displaying, and simultaneously sends the voltage signal and the test result to an upper computer through an upper computer communication module for analysis and processing, and the test is finished. Therefore, the testing system for the driving capability of the NOR Flash chip can carry out quantitative testing on the driving capability of the NOR Flash chip port, and is beneficial to improving the adaptability of the NOR Flash chip to different board level environments.
In order to implement the above embodiments, as shown in fig. 8, the present disclosure also proposes an electronic device 11000, which includes the above-mentioned test system 10000 for NOR Flash chip driving capability.
The electronic device 11000 of the embodiment of the present disclosure can perform a quantitative test on the driving capability of the NOR Flash chip port through the above-mentioned test system 10000 of the driving capability of the NOR Flash chip, which is helpful for improving the adaptability of the NOR Flash chip to different board-level environments.
In the description of the present specification, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure.
Claims (7)
1. A testing system for the driving capability of a NOR Flash chip is characterized by comprising a processor module, a data storage module, a program control voltage module, a DUT module, a positive and negative voltage module and a DC measuring module, wherein,
the processor module comprises an MCU chip and an FPGA chip, wherein the MCU chip is respectively connected with the data storage module, the FPGA chip, the program-controlled voltage module, the DUT module and the positive and negative pressure module, and the FPGA chip is connected with the DC measurement module;
the DUT module is respectively connected with the DC measurement module, the program-controlled voltage module and the positive and negative pressure module;
the data storage module is used for storing first configuration information and first test information of the tested NOR Flash chip;
the MCU chip is used for receiving a test command sent by a user, acquiring the first configuration information and the first test information from the data storage module according to the test command, and generating a voltage adjustment instruction and a positive and negative voltage control instruction according to the first configuration information and the first test information;
the DUT module is used for loading the tested NOR Flash chip;
the program-controlled voltage module is used for adjusting the test voltage of the NOR Flash chip to be tested according to the voltage adjusting instruction;
the positive and negative pressure module is used for simulating different input and output states of a port of the NOR Flash chip to be tested according to the positive and negative pressure control instruction so as to construct a test environment;
the DC measuring module is used for collecting a voltage signal of the port of the NOR Flash chip to be measured;
the FPGA chip is used for processing the voltage signal to generate a test result;
the MCU chip is also used for generating a first test instruction and a second test instruction according to the first configuration information and the first test information;
the DUT module is further used for controlling the port of the NOR Flash chip to be tested to enter a state to be tested according to the first test instruction;
the FPGA chip is also used for controlling the FPGA chip to enter a test state according to the second test instruction;
the function selection module is connected with the MCU chip and used for sending second configuration information and second test information of the tested NOR Flash chip to the MCU chip when the test system of the drive capability of the NOR Flash chip is separated from the control of an upper computer, wherein the second configuration information and the second test information are manually set;
and the MCU chip is also used for generating a related test instruction according to the second configuration information and the second test information.
2. The NOR Flash chip driving capability test system of claim 1, further comprising:
and the load module is connected with the program control voltage module and used for simulating load conditions under different circuits so as to construct an actual circuit environment of the port of the tested NOR Flash chip.
3. The NOR Flash chip driving capability test system of claim 1, further comprising:
and the display module is connected with the MCU chip, wherein the MCU chip is also used for sending the test result to the display module so as to provide the test result for a user through the display module.
4. The NOR Flash chip driving capability test system of claim 1, further comprising:
and the online module is connected with the MCU chip and is used for connecting other test systems.
5. The NOR Flash chip driving capability test system of claim 1, further comprising:
and the separator communication module is connected with the MCU chip and is used for communicating with a separator so as to place the tested NOR Flash chip into the test seat of the DUT module through the separator.
6. The NOR Flash chip driving capability test system of claim 1, further comprising:
the upper computer communication module is connected with the MCU chip and is used for communicating with an upper computer; wherein the content of the first and second substances,
the MCU chip is also used for sending the voltage signal and the test result to the upper computer through the upper computer communication module.
7. An electronic device characterized by comprising the NOR Flash chip driving capability test system according to any of claims 1 to 6.
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| CN112582015A (en) * | 2020-12-30 | 2021-03-30 | 普冉半导体(上海)股份有限公司 | Method and system for NOR Flash reliability test |
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