CN117595873A - Column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
In the method, in a single calibration period, the lowest bit of each column capacitor array is calibrated by using column shared slope voltage, the rest capacitors are calibrated by adopting slope voltage and calibrated capacitors one by one from low to high, and the offset of each capacitor corresponding to a digital code is stored in a column register after calibration for calibrating the quantization result of the normally working ADC. The invention provides a column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method, which provides a high-efficiency and accurate calibration method for two-step SAR/SS ADC errors, and the calibration is completed at a minimum cost by adding a small number of digital control circuits and registers and not greatly increasing the power consumption and the area depending on the original circuit of an ADC architecture.
Description
Technical Field
The invention belongs to the technical field of read-out conversion circuits of CMOS (complementary metal oxide semiconductor) image sensors, and particularly relates to a shared shift calibration method in front of a column parallel SAR/SS ADC (analog to digital converter)/Jing Xiepo.
Background
With the increasing application demands of CMOS image sensors, the performance of Analog-to-Digital Converter (ADC) which is a key module of CMOS image sensors is continuously improved, and the CMOS image sensors are continuously developed towards high speed, high precision and low power consumption. Among the numerous ADC architectures, the column-parallel two-step SAR/SS ADC has become a popular architecture for CMOS image sensors by virtue of its excellent overall performance. However, with the improvement of the resolution, the problem of single-column errors is more and more remarkable, the dynamic performance of the ADC is affected, the problem of errors among columns is more and more affected on the final imaging quality of the CMOS image sensor, and the search of an efficient, simple and low-cost calibration method becomes a new direction for promoting the development of the two-step SAR/SS ADC.
In the existing calibration scheme, the split ADC calibration based on equalization is suitable for background or foreground calibration due to rapid convergence, but the technology needs to divide the original ADC into two sub ADCs, so that single-column power is greatly increased, and the design difficulty of the ADC is increased under the condition of limited column width; the disturbance-based calibration requires only one ADC, but requires one peak-to-peak over half full scale period input to calibrate all bits, which limits the frequency of the ADC input signal. In many methods, a strategy for better solving the errors among columns does not appear, and meanwhile, errors introduced during the switching of SS quantization and SAR quantization are not calibrated.
Aiming at the defects of the prior method, the front Jing Xiepo of the column parallel SAR/SS ADC provided by the invention shares a shift calibration method, the prior structure of the SAR/SS ADC is utilized to calibrate the multi-column ADC at the same time, only part of control circuits are added, and the errors in the columns and among the columns are calibrated at the same time at minimum cost.
Disclosure of Invention
The invention aims to provide a column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method, which solves the problem of error calibration in the columns and among the columns of a two-step SAR/SS ADC.
The technical scheme adopted by the invention is as follows: in an independent calibration period, the column-parallel SAR/SS ADC front Jing Xiepo shares a shift calibration method, the lowest bit of each column capacitor array is calibrated by using column-shared ramp voltage, other capacitors are calibrated by adopting ramp voltage and calibrated capacitors one by one from low to high, and after calibration, the offset of each capacitor corresponding to a digital code is stored in a column register for calibration of a quantization result of an ADC which normally works.
The invention is also characterized in that the column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method comprises the following steps:
step 1, starting a calibration period, calibrating each column capacitor array from the lowest-order capacitor bit by using column sharing slope voltage, wherein each column ADC input end, each capacitor upper plate of the capacitor array and a capacitor lower plate except for the ith capacitor are connected with a reference voltage V CM 。
Step 2, the ith capacitor lower electrode plate is connected with a reference voltage V ref1 Then the upper polar plate of the capacitor is disconnected from the other lower polar plates of the capacitor and the reference voltage V CM Is connected with the reference voltage V by the lower polar plate of the ith capacitor CM 。
Step 3, starting calibration and quantization, if the ith capacitor is the lowest capacitor of the capacitor array, directly performing SS calibration and quantization by adopting a slope voltage, wherein other capacitors of the capacitor array do not participate in the calibration and quantization to obtain a P+1 bit (the digital code corresponding to SS full scale quantization in the calibration period is greater than or equal to the digital code corresponding to the lowest capacitor of the capacitor array participating in the quantization), and if the ith capacitor is not the lowest capacitor, starting the calibration and quantization by the ith-1 bit capacitor until the SS calibration and quantization is finished, and the high capacitor of the capacitor array does not participate in the calibration and quantization to obtain a P+i bit calibration and quantization result, wherein the recording result is D i,0 Temporary stores into the post calibration quantization register.
Step 4, the ith capacitor lower polar plate is changed into V ref2 Repeating the steps 1 to 3 to obtain D i,1 Stored in a post calibration quantization register.
Step 5, under the control of the calibration processing circuit, for D i,0 And D i,1 Performing operation to obtain the offset value between the actual digital code of the ith capacitor and the ideal digital code, and finally storingIn the calibration quantization register, the calibration of the ith capacitor is completed, and the calibration of the i+1 capacitor is continued; the method specifically comprises the following steps:
step 5.1, under the control of the calibration processing circuit, calculatingTemporarily stored in a calibration quantization register;
step 5.2, pair W i,cal If the first bit is 1, the sign bit is 0, calculate W i ＝W i,cal -W i,ideal If the first bit is 0, the sign bit is 1, calculate W i ＝W i,ideal -W i,cal ；
Step 5.3, storing a P+2 bit value in the calibration quantization register as the offset value between the calibration capacitor and its ideal digital code, the first bit being the sign bit and the remainder being W i Lower p+1 bits of (c).
Step 6, after all the capacitors are calibrated, each capacitor digital code offset value of each column of capacitor array is stored in a calibration quantization register of the column, the calibration period is ended, the ADC enters a normal working period, the quantization result is stored in the ADC quantization register, and the calibrated quantization result is calculated by combining the digital code offset values stored in the calibration quantization register under the control of the digital processing circuit; the method specifically comprises the following steps:
step 6.1, entering a normal working period of the ADC, ending one quantization period, storing each column of quantization results in an ADC quantization register, processing each column of data by a digital processing circuit, firstly reading the quantization results in the ADC quantization register, and searching a digital code offset value corresponding to a bit with the quantization result of 1 in a calibration quantization register according to the quantization results;
step 6.2, corresponding calculation is carried out according to the positive and negative values represented by the sign bit, and each offset is accumulated and temporarily stored in a calibration quantization register;
and 6.3, calculating (adding or subtracting) the offset accumulated value and the quantized result to finally obtain a calibrated quantized result which is used as the quantized output of the ADC.
The beneficial effects of the invention are as follows: the invention provides a column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method, which provides a high-efficiency and accurate calibration method for two-step SAR/SS ADC errors, and the calibration is completed at a minimum cost by adding a small number of digital control circuits and registers and not greatly increasing the power consumption and the area depending on the original circuit of an ADC architecture.
Drawings
FIG. 1 is a schematic diagram of a column-parallel SAR/SS ADC pre-Jing Xiepo shared shift calibration method of the present disclosure for a ADC to be calibrated;
FIG. 2 is a schematic diagram of the capacitive array calibration logic in the column parallel SAR/SS ADC pre-Jing Xiepo shared shift calibration method of the present invention;
FIG. 3 is a schematic diagram of the calibration process flow in the column-parallel SAR/SS ADC pre-Jing Xiepo shared shift calibration method of the present invention;
fig. 4 is a schematic diagram of a digital processing flow in a column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method of the present invention.
In the figure, 1 is a column sharing voltage reference circuit, 2 is a column sharing slope generator, 3 is a capacitor array, 4 is a sampling switch, 5 is a comparator, 6 is a counter, 7 is an SAR logic control circuit, 8 is an ADC quantization register, 9 is a calibration quantization register, 10 is a digital processing circuit, 11 is a calibration logic control circuit, and 12 is a calibration processing control circuit.
Detailed Description
The invention will be described in detail with reference to the accompanying drawings and detailed description.
Example 1
The invention provides a shared shift calibration method before a column parallel SAR/SS ADC Jing Xiepo, which is characterized in that in an independent calibration period, the lowest bit of each column capacitor array is calibrated by using column shared slope voltage, other capacitors are calibrated by adopting slope voltage and calibrated capacitors one by one from low to high, and errors among columns can be calibrated due to the fact that calibration references of the columns are the same slope voltage while errors in the columns are calibrated. After calibration, the offset of each capacitor corresponding to the digital code is stored in an in-column register for calibration of the quantization result of the ADC which works normally.
Through the mode, the column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method provided by the invention provides an efficient and accurate calibration method for the errors of the two-step SAR/SS ADC, and the calibration is completed at low cost by adding a small number of digital control circuits and registers and not adding a large amount of power consumption and area depending on the original circuit of the ADC architecture.
Example 2
The core idea of the invention is to perform foreground slope sharing shift calibration on a multi-column capacitor array by using column sharing slope voltage, and the overall structure of a two-step SAR/SS ADC to be calibrated is shown in figure 1. When the ADC works normally, the quantization generates an N-bit binary code, wherein high Q bits are quantized by the SAR ADC, and low P bits are quantized by the SS ADC. The reference voltage is generated by a column common voltage reference circuit 1 and is respectively connected to the ADC input end and the V of the capacitor array by a calibration period CM V representing a weight of 0 REF1 And V representing a weight of 1 REF2 . Ramp voltage V generated by column common ramp generator 2 ramp The dummy capacitors are connected to the lower plates of the capacitor arrays 3 of each column, and the weights of the dummy capacitors are the same as the lowest-order capacitors of the capacitor arrays. The column shared ramp generator 2 generates a ramp voltage corresponding to a low P bit for quantization when the ADC is in normal operation, and generates a ramp voltage corresponding to a p+1 bit for calibration of the capacitor array 3 in a calibration stage. Each column of capacitor array 3 generates successive approximation output voltage under the control of SAR logic control circuit 7 to quantize the ADC high M bits. One end of two input ends of the comparator 5 is connected with an upper polar plate of the capacitor array 3, the other end is connected with the sampling switch 4, and the ADC normal quantization stage obtains a quantized code value by comparing the input voltage of the ADC with the output voltage of the capacitor array 3. The output end of the comparator 5 is connected with the SAR logic control circuit 7 and the counter 6.SAR logic controls the reference voltage connected with the lower polar plate of the capacitor array 3 according to each bit comparison result, and the quantization result is also stored in the switch control signal; the counter 6 counts from the SS ADC quantization, and when the comparison result of the comparator 5 is inverted, the counter 6 terminates the counting. The overall quantization result of the ADC is stored in the ADC quantization register 8. The calibration logic control circuit 11 performs calibration for each column of the capacitive array in a calibration periodColumn 3 has control and timing control for the calibration process control circuit 12. The calibration processing control circuit 12 can control the calibration quantization register 9 on each column and store the digital code offset value after calibration quantization. After all calibration is completed and the ADC enters a normal working period, under the control of the digital processing circuit 10, the calibrated quantized result is calculated by combining the digital code offset value stored in the calibration quantization register 9 and the quantized result stored in the ADC quantization register 8.
Example 3
The invention relates to a column parallel SAR/SS ADC front Jing Xiepo shared shift calibration method, which is implemented according to the following steps:
under control of the calibration signal, the ADC enters a calibration cycle, as shown in fig. 2. First, under the control of the calibration logic 11, the sampling switch 4 pairs of columns V CM Sampling, each column of ADC input end, upper polar plate of capacitor array 3 and C removing 0 The lower polar plate of the outer capacitor is connected with a reference voltage V CM 。C 0 Lower polar plate is connected with V ref1 Maintaining the voltage connection, disconnecting the upper plate in the capacitor array 3 from the capacitor array 0 And an outer lower plate. Re-disconnect C 0 Lower polar plate and V ref1 Change reference voltage V CM 。C d The lower polar plate is connected with the slope voltage to start to conduct the operation of C 0 The sampled voltage is quantized, because the sampled voltage is the lowest-order capacitor of the capacitor array 3, no higher-order capacitor participates in quantization, only the slope voltage participates in quantization, and after the quantization is completed, a P+1-order digital code is generated and marked as D 0,0 Temporary stored in the post calibration quantization register 9 of each column.
Again, the upper electrode plate in each row of capacitor arrays 3 is divided by C 0 The lower polar plate outside is connected with V CM 。C 0 Lower polar plate is connected with V ref2 Repeating the above operation to obtain quantized value D 0,1 Temporary stored in the post calibration quantization register 9 of each column. As shown in the calibration processing flow of fig. 3, under the control of the calibration processing control circuit 12, calculation is performedTemporarily stored in a calibration quantization register 9. For W 0,cal If the first bit is 1, the sign bit is 0, calculate W 0 ＝W 0,cal -W 0,ideal The method comprises the steps of carrying out a first treatment on the surface of the If the first bit is 0, the sign bit is 1, calculate W 0 ＝W 0,ideal -W 0,cal . Finally, based on the calculation result, a P+2 bit value is stored in the calibration quantization register 9 as C 0 Offset from its ideal digital code by a first sign bit and the remainder of W 0 . For C 0 Is completed.
Under the control of the calibration logic 11, each column starts to run for C 1 Calibration is performed, the sampling switch 4 is still for V CM Sampling, namely, upper polar plate and C-division in each column of capacitor array 3 1 The lower polar plate outside is connected with V CM 。C 1 Lower polar plate is connected with V ref1 Maintaining the voltage connection, disconnecting the upper plate in the capacitor array 3 from the capacitor array 1 Outer lower polar plate, then disconnect C 1 Lower polar plate and V ref1 Is connected with the reference voltage V CM 。C d The lower polar plate is connected with the slope voltage to start to conduct the operation of C 1 The sampled voltage is quantized, firstly enters into the SAR quantization stage, is quantized only by a capacitor lower than the calibration bit, and finally is quantized finally by SS. Obtaining P+2 bit calibrated quantized digital code, and marking as D 1,0 Temporary stored in the post calibration quantization register 9 of each column.
Again, the upper electrode plate in each row of capacitor arrays 3 is divided by C 1 The lower polar plate outside is connected with V CM 。C 1 Lower polar plate is connected with V ref2 Repeating the above operation to obtain quantized value D 1,1 Temporary stored in the post calibration quantization register 9 of each column. Under the control of the calibration process control circuit 12, the flow is calculated as shown in FIG. 3Temporarily stored in a calibration quantization register 9. For W 1,cal If the first bit is 1, the sign bit is 0, calculate W 1 ＝W 1,cal -W 1,ideal The method comprises the steps of carrying out a first treatment on the surface of the If the first bit is 0, the sign bit is 1, calculate W 1 ＝W 1,ideal -W 1,cal . Finally, according to the result of the calculation,storing a p+2 bit value as C in the calibration quantization register 9 0 Calibrating the offset value of quantized digital code and its ideal digital code, the first bit is sign bit, the rest value is W 1 Lower p+1 bits of (c). To this end, for C 1 Is completed.
The above steps are repeated until all capacitance calibrations are completed. The digital code offset values of the capacitor arrays 3 on the respective columns are stored in the calibration quantization register 9, and the calibration period ends.
The ADC enters a normal operating period, one quantization period ends, and each column of quantization results is stored in the ADC quantization register 8. As shown in fig. 4, the digital processing circuit 10 processes each column of data, reads the quantization result in the ADC quantization register 8 first, and searches the digital code offset value corresponding to the bit with the quantization result of 1 in the calibration quantization register 9 according to the quantization result.
And corresponding calculation is carried out according to the positive and negative values represented by the sign bits, and each offset is accumulated and temporarily stored in the calibration quantization register 9. And (3) calculating (summing) the offset accumulated value and the quantized result to finally obtain a calibrated quantized result which is used as the final quantized output of the ADC.
Claims (5)
1. The shared shift calibration method for the front Jing Xiepo of the column parallel SAR/SS ADC is characterized in that in an independent calibration period, the lowest bit of each column capacitor array is calibrated by using column shared slope voltage, other capacitors are calibrated by adopting slope voltage and calibrated capacitors one by one from low to high, and after calibration, the offset of each capacitor corresponding to a digital code is stored in a column register for calibration of a quantization result of the ADC which works normally.
2. The column-parallel SAR/SS pre-ADC Jing Xiepo shared shift calibration method of claim 1, comprising the steps of:
step 1, starting a calibration period, calibrating each column capacitor array from the lowest-order capacitor by using column sharing slope voltage, and performing bit-by-bit calibration on each column ADC input end, each capacitor upper plate of the capacitor array and the ith-order capacitorThe lower polar plate of the capacitor is connected with the reference voltage V CM ；
Step 2, the ith capacitor lower electrode plate is connected with a reference voltage V ref1 Then the upper polar plate of the capacitor is disconnected from the other lower polar plates of the capacitor and the reference voltage V CM Is connected with the reference voltage V by the lower polar plate of the ith capacitor CM ；
Step 3, starting calibration and quantization, if the ith capacitor is the lowest capacitor of the capacitor array, directly performing SS calibration and quantization by adopting a slope voltage, wherein other capacitors of the capacitor array do not participate in the calibration and quantization to obtain a P+1 bit calibration and quantization result, if the ith capacitor is not the lowest capacitor, starting the calibration and quantization by the ith-1 bit capacitor until the SS calibration and quantization is finished, and the high capacitor of the capacitor array does not participate in the calibration and quantization to obtain a P+i bit calibration and quantization result, wherein the result is D i,0 Temporary storage is carried out in a post-stage calibration quantization register;
step 4, the ith capacitor lower polar plate is changed into V ref2 Repeating the steps 1 to 3 to obtain D i,1 Storing the data into a later calibration quantization register;
step 5, under the control of the calibration processing circuit, for D i,0 And D i,1 Performing operation processing to obtain the offset value of the actual digital code of the ith capacitor and the ideal digital code of the ith capacitor, finally storing the offset value in a calibration quantization register, and continuously calibrating the (i+1) th capacitor after the ith capacitor is calibrated;
and 6, after all the capacitors are calibrated, storing the digital code offset value of each capacitor of each row of capacitor array in a calibration quantization register of the row, ending the calibration period, enabling the ADC to enter a normal working period, storing the quantization result in the ADC quantization register, and calculating the calibrated quantization result under the control of the digital processing circuit by combining the digital code offset values stored in the calibration quantization register.
3. The method for calibrating the shared shift of the column-parallel SAR/SS ADC front Jing Xiepo according to claim 2, wherein the digital code corresponding to the full scale quantization of the SS in the calibration period of step 3 is greater than or equal to the digital code corresponding to the participation quantization of the lowest-order capacitors of the capacitor array.
4. The column-parallel SAR/SS pre-ADC Jing Xiepo shared shift calibration method of claim 2, wherein said step 5 comprises the steps of:
step 5.1, under the control of the calibration processing circuit, calculatingTemporarily stored in a calibration quantization register;
step 5.2, pair W i,cal If the first bit is 1, the sign bit is 0, calculate W i ＝W i,cal -W i,ideal If the first bit is 0, the sign bit is 1, calculate W i ＝W i,ideal -W i,cal ；
Step 5.3, storing a P+2 bit value in the calibration quantization register as the offset value between the calibration capacitor and its ideal digital code, the first bit being the sign bit and the remainder being W i Lower p+1 bits of (c).
5. The column-parallel SAR/SS pre-ADC Jing Xiepo shared shift calibration method of claim 2, wherein said step 6 specifically comprises the steps of:
step 6.1, entering a normal working period of the ADC, ending one quantization period, storing each column of quantization results in an ADC quantization register, processing each column of data by a digital processing circuit, firstly reading the quantization results in the ADC quantization register, and searching a digital code offset value corresponding to a bit with the quantization result of 1 in a calibration quantization register according to the quantization results;
step 6.2, corresponding calculation is carried out according to the positive and negative values represented by the sign bit, and each offset is accumulated and temporarily stored in a calibration quantization register;
and 6.3, performing addition or subtraction operation on the offset accumulated value and the quantized result to finally obtain a calibrated quantized result which is used as the quantized output of the ADC.
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