CN117498865A - Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization - Google Patents
Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization Download PDFInfo
- Publication number
- CN117498865A CN117498865A CN202311493418.6A CN202311493418A CN117498865A CN 117498865 A CN117498865 A CN 117498865A CN 202311493418 A CN202311493418 A CN 202311493418A CN 117498865 A CN117498865 A CN 117498865A
- Authority
- CN
- China
- Prior art keywords
- digital converter
- clock
- stage analog
- asynchronous
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 56
- 238000013139 quantization Methods 0.000 title claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims abstract description 69
- 238000004364 calculation method Methods 0.000 claims abstract description 11
- 238000005070 sampling Methods 0.000 claims description 18
- 230000007306 turnover Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization, which is characterized in that: a two-stage analog-to-digital converter including an asynchronous control clock, a synchronous control clock, a residual voltage amplifier, and a quantized input signal; the two-stage analog-to-digital converter is controlled by an asynchronous control clock when quantizing respective input signals; the two-stage analog-to-digital converter is synchronously controlled by a control clock when calibrating the capacitance; thus, the reliability and accuracy of capacitance calibration are ensured to a great extent, and the quantization speed of the analog-to-digital converter is also ensured; the frequency-adjustable oscillator is used as a synchronous control clock, the establishment time of each capacitor and the calculation time of the capacitor weight are flexibly adjusted, and the establishment time of the capacitor and the calculation time of the capacitor weight can be changed according to requirements.
Description
Technical Field
The present invention relates to the field of analog-to-digital converters, and in particular, to a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization.
Background
With the rapid development of modern communication technology, the demand for analog-to-digital converters in the communication field is continuously increasing, and the speed and the accuracy of the analog-to-digital converters all present new challenges. In order to increase the quantization rate of the analog-to-digital converter, asynchronous control logic is generally used at present, and asynchronous control can automatically enter the quantization of the capacitor of the next bit after the quantization of the capacitor of each bit is completed, so that the quantization time is greatly saved. However, in the design of the second-stage analog-to-digital converter, a problem that is unavoidable is a mismatch of capacitance generated during the process, so that in the design of the second-stage analog-to-digital converter, capacitance calibration is generally required. In the process of capacitance calibration, if a certain capacitor is calculated deviation caused by asynchronous control logic, the whole calibration accuracy is reduced, so that the conventional asynchronous analog-to-digital converter has certain defects in the aspect of capacitance calibration.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention provides a two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization. The synchronous clock is used for calibration in the process of capacitance calibration, and asynchronous use is adopted for control when the analog-to-digital converter works normally, so that the reliability of capacitance calibration is ensured to a great extent, and the quantization speed of the analog-to-digital converter is also ensured.
The technical scheme is as follows: to achieve the above object, a two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization according to the present invention is characterized in that: a two-stage analog-to-digital converter including an asynchronous control clock, a synchronous control clock, and a quantized VIN input signal; the two-stage analog-to-digital converter is controlled by an asynchronous control clock when quantizing VIN input signals; the two-stage analog-to-digital converter is synchronously controlled by a control clock when calibrating the capacitance.
Further, the synchronous control clock is an oscillator with adjustable frequency.
Further, in the asynchronous control clock logic, the signal of ending the sampling is used as the signal of starting the quantization; after sampling is finished, the effective signal is pulled down, a comparator of the two-stage analog-to-digital converter enters a first comparison period, the effective signal is used for a certain delay and then is provided for the comparator to be used as a comparison clock of the comparator, and after each capacitor is compared, the next capacitor is automatically entered for comparison; the VALID signal is generated using the comparison result of the comparator as nand logic.
Further, when the comparator is in a reset state, the VALID signal is pulled high, and after the comparator compares the result once, the VALID signal can turn over automatically; the VALID signal may indicate whether the comparator has completed the comparison.
Furthermore, during capacitor calibration, capacitors in the two-stage analog-to-digital converter are calibrated by adopting a synchronous control clock, the frequency of the synchronous control clock is controlled, and the establishment time of each capacitor and the calculation time of the capacitor weight are flexibly adjusted; after the capacitor calibration is completed, the calibration completion signal is pulled up to mark the two-stage analog-to-digital converter to enter a normal quantization mode.
Further, the two-stage analog-to-digital converter comprises a first-stage analog-to-digital converter, a second-stage analog-to-digital converter and an amplifier; the first-stage analog-to-digital converter quantizes an input signal, the amplifier amplifies a residual voltage signal generated after the first-stage analog-to-digital converter quantizes a VIN signal, and the second-stage analog-to-digital converter quantizes the amplified residual voltage signal.
Further, the asynchronous control clock respectively controls the first-stage analog-to-digital converter and the second-stage analog-to-digital converter of the two-stage analog-to-digital converter to quantize an input signal through a third digital control circuit and a fourth digital control circuit; the synchronous control clock is used for respectively controlling capacitance calibration in a first-stage analog-to-digital converter and a second-stage analog-to-digital converter of the two-stage analog-to-digital converter through a first digital control circuit and a second digital control circuit.
Further, the asynchronous control clock and the synchronous control clock are electrically connected with the synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the asynchronous control clock and the synchronous control clock to be output alternately, and outputs a signal of the synchronous control clock to the two-stage analog-digital converter when the capacitance of the two-stage analog-digital converter is calibrated; when the two-stage analog-to-digital converter quantizes the VIN input signal, the synchronous-asynchronous alternating control circuit outputs a signal of an asynchronous control clock to the two-stage analog-to-digital converter.
The beneficial effects are that: according to the two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization, the synchronous clock is used for calibration in the process of capacitance calibration, and when the analog-to-digital converter works normally, asynchronous use is used for controlling signal quantization, so that reliability and accuracy of capacitance calibration are guaranteed to a great extent, and the quantization speed of the analog-to-digital converter is also guaranteed; the setting time of each capacitor and the calculation time of the capacitor weight are flexibly adjusted by using the oscillator with adjustable frequency as a synchronous control clock, and the setting time of the capacitor and the calculation time of the capacitor weight can be changed according to requirements.
Drawings
FIG. 1 is a schematic diagram of a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization;
FIG. 2 is a schematic diagram of a single capacitor connection;
FIG. 3 is an asynchronous control clock timing diagram;
FIG. 4 is a schematic diagram of the basic architecture of the analog-to-digital converter;
FIG. 5 is a timing diagram of a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization;
fig. 6 is a diagram of a synchronous-asynchronous alternating control circuit.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, a two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization comprises an asynchronous control clock 1, a synchronous control clock 2 and a two-stage analog-to-digital converter 3 for quantizing a VIN input signal; when the two-stage analog-to-digital converter 3 quantizes the VIN input signal, the VIN input signal is controlled by the asynchronous control clock 1; the two-stage analog-to-digital converter 3 is controlled by a synchronous control clock 2 when calibrating the capacitance.
As shown in fig. 1, the two-stage analog-to-digital converter 3 includes a first-stage analog-to-digital converter 31, a second-stage analog-to-digital converter 32, and an amplifier 33; the first-stage analog-to-digital converter 31 quantizes the VIN input signal, the amplifier 33 amplifies a residual voltage signal generated after the first-stage analog-to-digital converter 31 quantizes the VIN signal, and the second-stage analog-to-digital converter 32 quantizes the amplified residual voltage signal.
The amplifier 33 is a fixed gain amplifier;
the synchronous control clock 2 is an oscillator with adjustable frequency.
As shown in fig. 1, in the asynchronous control clock (1) logic, a signal of ending sampling is used as a signal of starting quantization; after sampling is finished, the effective signal is pulled down, a comparator of the two-stage analog-to-digital converter (3) enters a first comparison period, the effective signal is used for a certain delay and then is provided for the comparator to be used as a comparison clock of the comparator, and after each capacitor comparison is finished, the next capacitor comparison is automatically carried out; the VALID signal is generated using the comparison result of the comparator as nand logic.
As shown in fig. 1, the asynchronous control clock 1 controls the quantization of the input signal by the first-stage analog-to-digital converter 31 and the second-stage analog-to-digital converter 32 of the two-stage analog-to-digital converter 3 through the third digital control circuit 6 and the fourth digital control circuit 7, respectively; the synchronous control clock 2 controls the capacitance calibration in the first stage analog-to-digital converter 31 and the second stage analog-to-digital converter 32 of the two stage analog-to-digital converter 3 via the first digital control circuit 4 and the second digital control circuit 5, respectively.
As shown in fig. 1, when the first-stage analog-to-digital converter 1 samples an input signal, a positive-end voltage signal of a VIN signal is input to one side plate of the first upper capacitor array through a sampling switch, a negative-end voltage signal of the VIN signal is input to one side plate of the first lower capacitor array through a sampling switch, and the other plate of the first upper capacitor array and the other plate of the first lower capacitor array are electrically connected with the third digital control circuit 6; the positive and negative voltage signals of the VIN signal are respectively input to the positive and negative input terminals of the first comparator, and the output terminal of the first comparator outputs a signal to the third digital control circuit 6, where the positive and negative input terminals of the first comparator are respectively electrically connected to the positive and negative input terminals of the amplifier 33.
When the second-stage analog-to-digital converter 2 receives the residual voltage signal, the positive-end voltage signal of the residual voltage signal amplified by the amplifier 33 is input to one side plate of the second upper capacitor array through the sampling switch, the negative-end voltage signal of the residual voltage signal amplified by the amplifier 33 is input to one side plate of the second lower capacitor array through the sampling switch, and the other plate of the second upper capacitor array and the other plate of the second lower capacitor array are electrically connected with the fourth digital control circuit 7; the positive and negative end voltage signals of the residual voltage signal amplified by the amplifier 3 are respectively input to the positive and negative input ends of a second comparator, and the output end of the second comparator outputs signals to a fourth digital control circuit 7.
As shown in fig. 1, the first comparator compares the positive voltage signal and the negative voltage signal of the VIN signal, when the positive voltage signal is greater than the negative voltage signal, the first comparator outputs 1, and when the positive voltage signal is less than or equal to the negative voltage signal, the first comparator outputs 0; the second comparator compares the positive terminal voltage signal and the negative terminal voltage signal of the residual voltage signal amplified by the amplifier 33, when the positive terminal voltage signal is greater than the negative terminal voltage signal, the second comparator outputs 1, and when the positive terminal voltage signal is less than or equal to the negative terminal voltage signal, the second comparator outputs 0;
as shown in fig. 2, during sampling, the upper plate of the capacitor is connected to VIN signal through sampling switch S0, and the lower plate of the capacitor is connected to VREFP reference high voltage, VREFN reference low voltage and VCM common voltage through first set switch S1, second set switch S2 and third set switch S3, respectively.
As shown in fig. 3, in the asynchronous control clock 1 logic, a signal of ending the sampling is used as a signal of starting the quantization; after the sampling is finished, the effective signal is pulled down, the comparator of the two-stage analog-to-digital converter 3 enters a first comparison period, the effective signal is used for a certain delay and then is provided for the comparator to be used as a comparison clock of the comparator, and after the comparison of each capacitor is finished, the comparison of the next capacitor is automatically carried out; the VALID signal is generated by NAND logic using the comparison result of the comparator; when the comparator is in a reset state, the VALID signal is pulled high, and after the comparator compares a result once, the VALID signal can turn over automatically; the VALID signal may indicate whether the comparator has completed the comparison; the amount of time that the capacitor is established is therefore dependent on the comparison speed of the comparator and the delay provided in the circuit.
Asynchronous control clock 1 logic is used in the normal quantization mode to increase the quantization speed of the analog-to-digital converter.
The calibration concept is to use the low-order capacitor and the comparator as a small analog-to-digital converter to quantify the actual size of the high-order capacitor.
As shown in fig. 4, assume that in the calibration process, taking the calibration of the C1 capacitor as an example, in the sampling stage, the upper plate switch of the C1 capacitor is short-circuited to VCM common mode voltage, and the lower plate switches of all the other capacitors except the lower plate switch of the C1P capacitor are connected to VIN signal positive terminal voltage signal are all connected to VCM common mode voltage; after sampling is finished, the lower-stage plate switch of the C1P capacitor is connected to the VCM common-mode voltage, and the other switches are still connected to the VCM common-mode voltage; at this time, the positive terminal voltage of the comparator is the voltage value of the C1P capacitor inversion, and the C0 capacitor is used for quantizing the voltage of the C1P capacitor inversion, namely the quantized result of the capacitor weight of the C0 capacitor; the actual capacitance of the C1P capacitor can be obtained at this time. Similarly, the true weights of other capacitors can be obtained through calculation.
Therefore, the three processes of sampling time, time of capacitor establishment and weight calculation are controlled by time, delay time in the asynchronous control logic is relatively fixed, and flexible control cannot be carried out on the time of capacitor establishment and the time of weight calculation, so that the capacitance calibration effect in the complete asynchronous control clock 1 logic is not ideal; the capacitance in the two-stage analog-to-digital converter 3 is thus calibrated with the synchronous control clock 2.
As shown in fig. 1-5, during capacitor calibration, capacitors in the two-stage analog-to-digital converter 3 are calibrated by adopting a synchronous control clock 2, the frequency of the synchronous control clock 2 is controlled, and the establishment time of each capacitor and the calculation time of the capacitor weight are flexibly adjusted; after the capacitor calibration is completed, the calibration completion signal is pulled high to mark the two-stage analog-digital converter 3 to enter the normal quantization mode.
As shown in fig. 6, the asynchronous control clock 1 and the synchronous control clock 2 are electrically connected with a synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the asynchronous control clock 1 and the synchronous control clock 2 to be output alternately, and outputs a signal of the synchronous control clock 2 to the two-stage analog-digital converter 3 when the capacitance of the two-stage analog-digital converter 3 is calibrated; when the two-stage analog-to-digital converter 3 quantizes the VIN input signal, the synchronous-asynchronous alternate control circuit outputs a signal of the asynchronous control clock 1 to the two-stage analog-to-digital converter 3.
As shown in fig. 6, the synchronous-asynchronous alternative control circuit is composed of a MOD_CALI controlled controller and a group of D triggers not less than five, the MOD_CALI controls whether the analog-digital converter is in a calibration state or a quantization state, CLK_CALI is a synchronous control clock 2 used for calibration, CLK_ASCY is a VALID asynchronous control clock 1 used for quantization, and the circuit can be used for efficiently solving the problem of synchronous-asynchronous clock switching, thereby realizing capacitance calibration by using the synchronous clock and normal quantization by using the asynchronous clock.
Examples
As shown in fig. 1-5, before the two-stage analog-to-digital converter 3 quantizes the VIN signal, the frequency-adjustable oscillator is used as the synchronous control clock 2 to calibrate the capacitor in the two-stage analog-to-digital converter 3, so as to flexibly adjust the setup time of each capacitor and the calculation time of the capacitor weight; the frequency of the synchronous control clock 2 is changed to achieve the time for establishing the capacitor and the time for calculating the weight of the capacitor, and the time for establishing the capacitor and the time for calculating the weight of the capacitor can be changed according to the requirement;
after the capacitance calibration in the two-stage analog-to-digital converter 3 is completed, the two-stage analog-to-digital converter 3 samples the electric signal, and after the sampling is completed, the two-stage analog-to-digital converter 3 is controlled by the asynchronous control clock 1 to quantize the sampled signal;
after the quantization of the input signal is completed, the capacitance in the two-stage analog-to-digital converter 3 can be calibrated by the synchronous control clock 2, so as to facilitate the next quantization of the sampled signal by the two-stage analog-to-digital converter 3.
As shown in fig. 1-6, when the capacitance of the two-stage analog-to-digital converter 3 is calibrated, the mod_cali controller in the synchronous-asynchronous alternating control circuit controls the signal output by the clk_cali synchronous control clock 2 to be input into the two-stage analog-to-digital converter 3 through a group of D flip-flops for capacitance calibration; when the two-stage analog-to-digital converter 3 quantizes the electric signal, the mod_cali controller in the synchronous-asynchronous alternating control circuit controls the signal output by the clk_ascy asynchronous control clock 1 to be input to the two-stage analog-to-digital converter 3 through a group of D flip-flops to quantize the input signal.
The foregoing is a description of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that several modifications and variations can be made without departing from the principles of the invention, and such modifications and variations should also be considered to be within the scope of the invention.
Claims (8)
1. A two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization, characterized by: a two-stage analog-to-digital converter (3) comprising an asynchronous control clock (1), a synchronous control clock (2) and a quantized VIN input signal; the two-stage analog-to-digital converter (3) is controlled by an asynchronous control clock (1) when quantizing VIN input signals; the two-stage analog-to-digital converter (3) is controlled by a synchronous control clock (2) when calibrating the capacitance.
2. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 1 wherein: the synchronous control clock (2) is an oscillator with adjustable frequency.
3. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 1 wherein: in the asynchronous control clock (1) logic, a signal of ending sampling is taken as a signal of starting quantization; after sampling is finished, the effective signal is pulled down, a comparator of the two-stage analog-to-digital converter (3) enters a first comparison period, the effective signal is used for a certain delay and then is provided for the comparator to be used as a comparison clock of the comparator, and after each capacitor comparison is finished, the next capacitor comparison is automatically carried out; the VALID signal is generated using the comparison result of the comparator as nand logic.
4. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 3 wherein: when the comparator is in a reset state, the VALID signal is pulled high, and after the comparator compares a result once, the VALID signal can turn over automatically; the VALID signal may indicate whether the comparator has completed the comparison.
5. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 2 wherein: when the capacitors are calibrated, the capacitors in the two-stage analog-to-digital converter (3) are calibrated by adopting the synchronous control clock (2), the frequency of the synchronous control clock (2) is controlled, and the establishment time of each capacitor and the calculation time of the capacitor weight are flexibly adjusted; after the capacitor calibration is completed, the calibration completion signal is pulled up to mark the two-stage analog-digital converter (3) to enter a normal quantization mode.
6. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 1 wherein: the two-stage analog-to-digital converter (3) comprises a first-stage analog-to-digital converter (31), a second-stage analog-to-digital converter (32) and an amplifier (33); the first-stage analog-to-digital converter (31) quantizes an input signal, the amplifier (33) amplifies a residual voltage signal generated after the first-stage analog-to-digital converter (31) quantizes a VIN signal, and the second-stage analog-to-digital converter (32) quantizes the amplified residual voltage signal.
7. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 6 wherein: the asynchronous control clock (1) respectively controls the quantization of the input signals by a first-stage analog-to-digital converter (31) and a second-stage analog-to-digital converter (32) of the two-stage analog-to-digital converter (3) through a third digital control circuit (6) and a fourth digital control circuit (7); the synchronous control clock (2) respectively controls the capacitance calibration in a first-stage analog-to-digital converter (31) and a second-stage analog-to-digital converter (32) of the two-stage analog-to-digital converter (3) through a first digital control circuit (4) and a second digital control circuit (5).
8. A synchronous clock calibrated and asynchronous clock quantized two-stage analog to digital converter according to claim 7 wherein: the asynchronous control clock (1) and the synchronous control clock (2) are electrically connected with the synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the asynchronous control clock (1) and the synchronous control clock (2) to output alternately, and when the capacitance of the two-stage analog-digital converter (3) is calibrated, the synchronous-asynchronous alternating control circuit outputs a signal of the synchronous control clock (2) to the two-stage analog-digital converter (3); when the two-stage analog-to-digital converter (3) quantizes the VIN input signal, the synchronous-asynchronous alternating control circuit outputs the signal of the asynchronous control clock (1) to the two-stage analog-to-digital converter (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311493418.6A CN117498865B (en) | 2023-11-10 | 2023-11-10 | Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311493418.6A CN117498865B (en) | 2023-11-10 | 2023-11-10 | Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117498865A true CN117498865A (en) | 2024-02-02 |
| CN117498865B CN117498865B (en) | 2024-06-28 |
Family
ID=89682468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311493418.6A Active CN117498865B (en) | 2023-11-10 | 2023-11-10 | Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117498865B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277112A (en) * | 2008-05-15 | 2008-10-01 | 复旦大学 | Low-power consumption assembly line a/d converter by sharing operation amplifier |
| US20100201552A1 (en) * | 2009-02-09 | 2010-08-12 | Prolific Technology Inc. | Self-calibration circuit and method for capacitors |
| CN104242942A (en) * | 2014-09-29 | 2014-12-24 | 清华大学 | Six-bit asynchronous successive approximation analog-digital converter with comparator offset calibration function |
| CN107911117A (en) * | 2017-11-22 | 2018-04-13 | 成都九芯微科技有限公司 | A kind of high position settling time dynamic calibration circuit |
| CN213585748U (en) * | 2019-09-05 | 2021-06-29 | 半导体元件工业有限责任公司 | Multistage analog-to-digital converter and analog-to-digital converter stage for multistage analog-to-digital converter |
| US20210359696A1 (en) * | 2020-05-13 | 2021-11-18 | Ciena Corporation | High resolution analog to digital converter with factoring and background clock calibration |
| CN115733493A (en) * | 2022-11-18 | 2023-03-03 | 江苏谷泰微电子有限公司 | Asynchronous and synchronous coexisting two-stage analog-to-digital converter and working method thereof |
| KR20230108188A (en) * | 2022-01-10 | 2023-07-18 | 삼성전자주식회사 | Analog-to-digital converter and analog-to-digital conversion method using the same |
-
2023
- 2023-11-10 CN CN202311493418.6A patent/CN117498865B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277112A (en) * | 2008-05-15 | 2008-10-01 | 复旦大学 | Low-power consumption assembly line a/d converter by sharing operation amplifier |
| US20100201552A1 (en) * | 2009-02-09 | 2010-08-12 | Prolific Technology Inc. | Self-calibration circuit and method for capacitors |
| CN104242942A (en) * | 2014-09-29 | 2014-12-24 | 清华大学 | Six-bit asynchronous successive approximation analog-digital converter with comparator offset calibration function |
| CN107911117A (en) * | 2017-11-22 | 2018-04-13 | 成都九芯微科技有限公司 | A kind of high position settling time dynamic calibration circuit |
| CN213585748U (en) * | 2019-09-05 | 2021-06-29 | 半导体元件工业有限责任公司 | Multistage analog-to-digital converter and analog-to-digital converter stage for multistage analog-to-digital converter |
| US20210359696A1 (en) * | 2020-05-13 | 2021-11-18 | Ciena Corporation | High resolution analog to digital converter with factoring and background clock calibration |
| KR20230108188A (en) * | 2022-01-10 | 2023-07-18 | 삼성전자주식회사 | Analog-to-digital converter and analog-to-digital conversion method using the same |
| CN115733493A (en) * | 2022-11-18 | 2023-03-03 | 江苏谷泰微电子有限公司 | Asynchronous and synchronous coexisting two-stage analog-to-digital converter and working method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117498865B (en) | 2024-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6967611B2 (en) | Optimized reference voltage generation using switched capacitor scaling for data converters | |
| CN109120268B (en) | Dynamic comparator offset voltage calibration method | |
| CN107994903B (en) | Analog-to-digital conversion circuit and pipeline analog-to-digital converter | |
| US10862498B1 (en) | Calibration circuit and calibration method for ADC | |
| US8860600B1 (en) | Successive-approximation-register analog-to-digital converter for programmably amplifying amplitude of input signal and method thereof | |
| US8922402B2 (en) | Offset correction device of comparator | |
| US8174423B2 (en) | Pipelined analog-to-digital converter and sub-converter stage | |
| US20050024250A1 (en) | Space efficient low power cyclic A/D converter | |
| CN113839673A (en) | Novel digital domain self-calibration successive approximation analog-to-digital converter | |
| CN108880545B (en) | Offset foreground calibration circuit and method for comparator of pipeline analog-to-digital converter | |
| US9276596B1 (en) | Analog to digital converting apparatus and initial method thereof | |
| CN115733493A (en) | Asynchronous and synchronous coexisting two-stage analog-to-digital converter and working method thereof | |
| CN117498865B (en) | Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization | |
| CN109660259B (en) | Successive approximation type analog-digital converter with constant output common mode voltage and switching method thereof | |
| CN109921795B (en) | Successive approximation type analog-to-digital converter, error correction method and device based on double comparators | |
| CN115473533B (en) | FLASH-SAR ADC conversion method and circuit | |
| CN111740741A (en) | Pipelined ADC capacitance mismatch calibration circuit and method | |
| CN114629497B (en) | Comparator offset voltage eliminating circuit for column parallel single-slope analog-to-digital converter | |
| CN112953546B (en) | Successive approximation type analog-digital converter based on automatic zeroing and working method | |
| CN115459769A (en) | Successive approximation analog-to-digital converter with segmented reference voltage | |
| CN114285414A (en) | Scaling type incremental analog-to-digital conversion method and converter | |
| CN110535473B (en) | Non-acquisition-guarantee high-speed high-input-bandwidth pipeline structure ADC without path mismatch | |
| TWI703830B (en) | Analog to digital converting device and capacitor adjusting method thereof | |
| CN103546153A (en) | Time constant correcting circuit and method | |
| CN117478133B (en) | Automatic time sequence calibration method and device for asynchronous clock architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |