CN117498858A

CN117498858A - Signal quality detection method and signal quality detection circuit

Info

Publication number: CN117498858A
Application number: CN202410001530.1A
Authority: CN
Inventors: 李谊
Original assignee: Shanghai Mi Silicon Technology Co ltd
Current assignee: Shanghai Mi Silicon Technology Co ltd
Priority date: 2024-01-02
Filing date: 2024-01-02
Publication date: 2024-02-02
Anticipated expiration: 2044-01-02
Also published as: CN117498858B

Abstract

The application provides a signal quality detection method and a signal quality detection circuit, which are provided by the embodiment of the application, and the technical field of signal processing is designed, and the method comprises the following steps: the error rate statistics module receives a locking state signal generated by the CDR locking detection circuit, and the timer starts to count; the error rate statistics module triggers one-time counting when the CDR locking detection circuit generates an unlocking signal; when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module. According to the method and the device, the bit error rate statistics module is introduced, and the bit error rate detection is realized by detecting the locking state signal generated by the CDR locking detection circuit, so that the detection cost is reduced, and the configuration difficulty is reduced.

Description

Signal quality detection method and signal quality detection circuit

Technical Field

The present disclosure relates to the field of signal processing technologies, and in particular, to a signal quality detection method and a signal quality detection circuit.

Background

CDR (clock and data recovery) the CDR lock detection circuit is a special high-speed circuit that recovers clock signals and data information from an input high-speed data signal, processes the clock signals recovered by CDR, and samples the data information to obtain a clean eye state, which is called CDR lock state.

The existing error rate measurement is generally performed by external instruments and equipment, so that the cost is high and the configuration is complex.

Disclosure of Invention

In view of this, an object of the present application is to provide a signal quality detection method and a signal quality detection circuit, by introducing a bit error rate statistics module, and by detecting a lock state signal generated by a CDR lock detection circuit, bit error rate detection is achieved, detection cost is reduced, and configuration difficulty is reduced.

The application mainly comprises the following aspects:

in a first aspect, an embodiment of the present application provides a signal quality detection method, which is applied to a bit error rate detection circuit, where the bit error rate detection circuit includes a bit error rate statistics module, a timer, and a microprocessor, and the method includes: the error rate statistics module receives a locking state signal generated by the CDR locking detection circuit, and the timer starts to count; the error rate statistics module triggers one-time counting when the CDR locking detection circuit generates an unlocking signal; when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module.

In one possible implementation, the bit error rate statistics module includes a first switch, a second switch, a capacitor, a comparator, and a counter, wherein a control end of the first switch is connected to an output end of the CDR lock detection circuit, a first connection end of the first switch is connected to a power supply, a second connection end of the first switch is connected to a forward input end of the comparator and one end of the capacitor, respectively, another end of the capacitor is grounded, an inverse input end of the comparator is connected to a reference voltage, a control end of the second switch is connected to the microprocessor, a first connection end of the second switch is connected to a forward input end of the comparator, a second connection end of the second switch is grounded, an output end of the comparator is connected to an input end of the counter, and an output end of the counter is connected to the microprocessor, the bit error rate statistics module completes triggering counting by: a1, the first switch and the second switch are opened, when the CDR locking detection circuit generates an unlocking signal, the first switch is triggered to be closed, so that the power supply charges the capacitor, and energy storage voltages are generated at two ends of the capacitor; a2, the comparator compares the energy storage voltage with the reference voltage, and when the energy storage voltage is larger than the reference voltage, the counter is triggered to finish one-time counting; a3, after the counter finishes counting once, the first switch is opened, and the second switch is closed, so that the capacitor discharges until the energy storage voltage becomes 0V; and (3) circularly executing the steps A1-A3 until the timer reaches the preset time, and extracting the count of the counter.

In one possible implementation manner, the bit error rate statistics module further includes a current detection sensor for detecting a charging current corresponding to the capacitor, wherein the current detection sensor is connected in series between the power supply and the first connection terminal of the first switch, and the module current is the charging current detected by the current detection sensor, and the microprocessor determines the bit error rate corresponding to the high-speed data input to the CDR lock detection circuit under the current clock phase according to the following formula:

in the course of this formula (ii) the formula,indicating bit error rate +.>Indicating that the predetermined time +.>After that, the number of counts extracted by the counter, < >>Representing module current +.>Representing the data input frequency, i.e. the input frequency of the lock state signal, wherein->Is the number of single bit errors +.>Representing comparator reference voltage, +.>Representing capacitance.

In one possible embodiment, the method further comprises: the microprocessor adjusts the reference voltage of the CDR locking detection circuit within a preset voltage range according to a preset step length, and for each adjustment, the microprocessor executes: s11. the microprocessor sets a first count number err_cur=1, an initial value of a clock phase pi=180°, a count threshold thres, and an eye jump number thru_open=0; s12, the bit error rate statistics module receives a locking state signal generated by the CDR locking detection circuit under the current clock phase, and simultaneously starts to count a timer, and counts second count times ERR_NEW of an unlocking signal generated by the CDR locking detection circuit under the current clock phase within a preset time; s13, the microprocessor determines the position of the clock phase PI according to the first count number ERR_CUR, the second count number ERR_NEW and the set number threshold thres; s14, if the clock phase PI is in the eye opening part, ERR_CUR=ERR_NEW and PI=PI-preset moving step length are made, and the step S12 is executed in a return mode; s15, if the clock phase PI is at the edge of eye opening to eye closing, determining a left edge point EYELEFT=PI, the eye jump times THRU_OPEN=THRU_OPEN+1, and returning to the step S12; s16. If the clock phase PI is at the edge where the eye is closed to OPEN, then the number of eye transitions thru_open=thru_open+1, determining the right edge point eye=pi; s17. if thru_open=2, outputting values of eyleft and yeright, and if thru_open is not equal to 2, performing error reporting; and (5) circulating S11-S17 to obtain a left edge point EYELEFT value and a right edge point EYERIGHT corresponding to each reference voltage in a preset voltage range, and drawing to form an eye pattern.

In one possible embodiment, step S13 includes: if ERR_CUR is less than or equal to thres and ERR_NEW is greater than thres, determining that the clock phase PI is in the eye-opening portion; if err_cur < thres and err_new > thres, determining that the clock phase PI is at the edge of eye open to closed; if ERR_CUR > thres and ERR_NEW++thres, then clock phase PI is at the edge where the eye is closed to open.

In one possible implementation, step S14 includes: s141, let err_cur=err_new and let pi=pi-preset movement step; s142, acquiring the phase adjustment total amount delta PI between the current clock phase and the clock phase initial value; s143, judging whether THRU_OPEN is not equal to 2 and delta PI is not less than 360 degrees; s144, if the THRU_OPEN is not equal to 2 and delta PI is not less than 360 degrees, error reporting is carried out; s145, if THRU_OPEN is not equal to 2 and δPI is not less than 360 degrees, returning to the step S12.

In a second aspect, an embodiment of the present application further provides a signal quality detection circuit, where the signal quality detection circuit includes a bit error rate detection circuit and a CDR lock detection circuit, the bit error rate detection circuit includes a bit error rate statistics module, a timer, and a microprocessor, where the bit error rate statistics module receives a lock state signal generated by the CDR lock detection circuit, and the timer starts to count time at the same time; the code rate statistics module triggers one-time counting when the lock losing signal is generated by the lock state signal; when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module. In one possible implementation manner, the bit error rate statistics module comprises a first switch, a second switch, a capacitor, a comparator and a counter, wherein the control end of the first switch is connected to the output end of the CDR locking detection circuit, the first connection end of the first switch is connected to a power supply, the second connection end of the first switch is respectively connected to the positive input end of the comparator and one end of the capacitor, the other end of the capacitor is grounded, the negative input end of the comparator is connected to a reference voltage, the control end of the second switch is connected to the microprocessor, the first connection end of the second switch is connected to the positive input end of the comparator, the second connection end of the second switch is grounded, the output end of the comparator is connected to the input end of the counter, and the output end of the counter is connected to the microprocessor; wherein, error rate statistics module: a1, the first switch and the second switch are opened, when the CDR locking detection circuit generates an unlocking signal, the first switch is triggered to be closed, so that the power supply charges the capacitor, and energy storage voltages are generated at two ends of the capacitor; a2, the comparator compares the energy storage voltage with the reference voltage, and when the energy storage voltage is larger than the reference voltage, the counter is triggered to finish one-time counting; a3, after the counter finishes counting once, the first switch is opened, and the second switch is closed, so that the capacitor discharges until the energy storage voltage becomes 0V; and (3) circulating the steps A1-A3 until the timer reaches the preset time, and extracting the count of the counter.

In one possible implementation manner, the bit error rate statistics module further includes a current detection sensor, configured to detect a charging current corresponding to the capacitor, where the current detection sensor is connected in series between the power supply and the first connection terminal of the first switch, and the module current is the charging current detected by the current detection sensor, and where the microprocessor is further configured to: determining the corresponding error rate of high-speed data input into the CDR locking detection circuit under the current clock phase by the following formula:

in the course of this formula (ii) the formula,indicating bit error rate +.>Indicating that the predetermined time +.>After that, the number of counts extracted by the counter, < >>Representing module current +.>Representing the data input frequency, i.e. the input frequency of the lock state signal, wherein->For the number of single bit errors, vth represents the comparator reference voltage and C represents the capacitance.

In one possible implementation, the microprocessor is further configured to: adjusting the reference voltage of the CDR locking detection circuit within a preset voltage range according to a preset step length, and executing for each adjustment: s11. the microprocessor sets a first count number err_cur=1, an initial value of the clock phase pi=180°, a count threshold thres, and an eye jump number thru_open=0; s12, the bit error rate statistics module receives a locking state signal generated by the CDR locking detection circuit under the current clock phase, and simultaneously starts to count a timer, and counts second count times ERR_NEW of an unlocking signal generated by the CDR locking detection circuit under the current clock phase within a preset time; s13, the microprocessor determines the position of the clock phase PI according to the first count number ERR_CUR, the second count number ERR_NEW and the set number threshold thres; s14, if the clock phase PI is in the eye opening part, ERR_CUR=ERR_NEW and PI=PI-preset moving step length are made, and the step S12 is executed in a return mode; s15, if the clock phase PI is at the edge of eye opening to eye closing, determining a left edge point EYELEFT=PI, the eye jump times THRU_OPEN=THRU_OPEN+1, and returning to the step S12; s16. If the clock phase PI is at the edge where the eye is closed to OPEN, then the number of eye transitions thru_open=thru_open+1, determining the right edge point eye=pi; s17. if thru_open=2, outputting values of eyleft and yeright, and if thru_open is not equal to 2, performing error reporting; and (5) circulating S11-S17 to obtain a left edge point EYELEFT value and a right edge point EYERIGHT corresponding to each reference voltage in a preset voltage range, and drawing to form an eye pattern.

The signal quality detection method and the signal quality detection circuit provided by the embodiment of the application comprise the following steps: the error rate statistics module receives a locking state signal generated by the CDR locking detection circuit, and the timer starts to count; the error rate statistics module triggers one-time counting when the CDR locking detection circuit generates an unlocking signal; when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module. According to the method and the device, the bit error rate statistics module is introduced, and the bit error rate detection is realized by detecting the locking state signal generated by the CDR locking detection circuit, so that the detection cost is reduced, and the configuration difficulty is reduced.

The application has the advantages that:

1. directly accessing a bit error rate statistics module into the CDR locking detection circuit to calculate the bit error rate by using the out-of-lock signal generated in the CDR locking detection circuit, and compared with external instrument equipment, the method reduces the cost of calculating the bit error rate and simplifies the configuration structure;

2. in the prior art, a special eye diagram detection circuit and a special digital processing logic are required to be designed for operation in drawing of an eye diagram in the CDR, a large amount of data comparison is required to be stored, the consumption of chip area and power consumption is large, and in the method, the eye diagram drawing is directly completed by combining phase control with an error rate statistics module, so that the circuit is simplified, the digital processing logic is reduced, and the storage requirement and the operation requirement are reduced.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic structural diagram of a signal quality detection circuit according to an embodiment of the present application;

fig. 2 shows a flowchart of a signal quality detection method according to an embodiment of the present application;

fig. 3 shows a schematic structural diagram of an error rate statistics module provided in an embodiment of the present application;

FIG. 4 is a flow chart of a method for triggering counting according to an embodiment of the present application;

FIG. 5 illustrates one of the flow charts of steps provided in an embodiment of the present application for determining eye edge points;

FIG. 6 shows a schematic diagram of an eye diagram drawing provided by an embodiment of the present application;

fig. 7 shows a second flowchart of a step of determining an eye edge point according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be appreciated that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.

In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

The CDR circuit is a data and clock recovery circuit for high-speed data signals, and the CDR lock detection circuit is used for judging whether the data and clock recovered by the CDR circuit are correct or not, when the CDR lock detection circuit outputs a high level, the CDR circuit is unlocked, and when the CDR lock detection circuit outputs a low level, the CDR circuit is locked.

The existing error rate measurement is generally performed by external instruments and equipment, the cost is high, the configuration is complex, a special eye diagram detection circuit and a special digital processing logic are required to be designed for drawing an eye diagram in the CDR to operate, a large amount of data comparison is required to be stored, and the consumption of chip area and power consumption is large.

Based on this, the embodiment of the application provides a signal quality detection method and a signal quality detection circuit, which realize bit error rate detection by detecting a lock state signal generated by a CDR lock detection circuit, reduce detection cost, reduce configuration difficulty, and specifically include the following steps:

referring to fig. 1, fig. 1 is a schematic diagram illustrating a signal quality detection circuit according to an embodiment of the present application. Referring to fig. 2, fig. 2 is a flowchart illustrating a signal quality detection method according to an embodiment of the present application. As shown in fig. 1, the signal quality detection circuit includes a CDR lock detection circuit 1 AND a bit error rate detection circuit 2, where the CDR lock detection circuit 1 includes a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, AND a logic AND module AND, AND the bit error rate detection circuit 2 includes a bit error rate statistics module 21 AND a microprocessor (NOT shown in the figure), AND the flip-flops in this application are class D flip-flops.

The data input end of the first flip-flop DFF1 and the data input end of the second flip-flop DFF2 are both connected to a high-speed data signal, the clock input end of the first flip-flop DFF1 is connected to a clock signal, the output end of the first flip-flop DFF1 is connected to the data input end of the third flip-flop DFF3 and the input end of the third NOT gate NOT3 respectively, the output end of the third NOT gate NOT3 is connected to the data input end of the fourth flip-flop DFF4, the input end of the first NOT gate NOT1 is connected to a clock signal, the output end of the first NOT gate NOT1 is connected to the clock input end of the second flip-flop DFF2, and the output end of the second flip-flop DFF2 is connected to the clock input end of the third flip-flop DFF3 and the input end of the second NOT gate NOT2 respectively, and the output end of the second NOT gate NOT2 is connected to the clock input end of the fourth flip-flop DFF 4.

The output of the third flip-flop DFF3 is connected to the first input of the logical AND-block AND, the output of the fourth flip-flop DFF4 is connected to the second input of the logical AND-block AND, the output of the logical AND-block AND is connected as output of the CDR lock detection circuit 1 to the input of the bit error rate statistics block 21, AND the output of the bit error rate statistics block 21 is connected to the microcontroller.

As shown in fig. 2, the method includes:

s100, the bit error rate statistics module receives a locking state signal generated by the CDR locking detection circuit, and the timer starts timing.

And S200, triggering one-time counting by the bit error rate counting module when the CDR locking detection circuit generates an unlocking signal.

And S300, when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module.

In step S100 to step S300, the number of bit errors generated by the lock state signal LOL in the predetermined time is counted by the bit error rate counting module 21 to obtain a corresponding bit error rate, so that the bit error rate detection circuit is simplified, and the hardware cost is reduced.

Referring to fig. 3, fig. 3 shows a schematic structural diagram of an error rate statistics module according to an embodiment of the present application. As shown in fig. 3, the bit error rate statistics module 21 includes a first switch SW1, a second switch SW2, a capacitor C, a comparator COMP and a counter, where the control end of the first switch SW1 is connected to the output end of the CDR lock detection circuit 1, the first connection end of the first switch SW1 is connected to the power supply VCC, the second connection end of the first switch SW1 is connected to the forward input end of the comparator COMP and one end of the capacitor C, the other end of the capacitor C is grounded, the reverse input end of the comparator COMP is connected to the reference voltage Vth, the control end of the second switch SW2 is connected to a microprocessor (not shown in the figure, specifically, a reset pin connectable to the microprocessor), the first connection end of the second switch SW2 is grounded, the output end of the comparator COMP is connected to the input end of the counter, and the output end of the counter is connected to the microprocessor (not shown in the figure).

Referring to fig. 4, fig. 4 is a flowchart illustrating a method for triggering counting according to an embodiment of the present application. As shown in fig. 4, the bit error rate statistics module completes the trigger count during a predetermined time by:

a1, the first switch and the second switch are opened, when the CDR locking detection circuit generates an unlocking signal, the first switch is triggered to be closed, so that the power supply charges the capacitor, and energy storage voltages are generated at two ends of the capacitor.

A2, the comparator compares the energy storage voltage with the reference voltage, and when the energy storage voltage is larger than the reference voltage, the starting counter finishes one-time counting.

A3, after the counter finishes counting once, the first switch is opened, and the second switch is closed, so that the capacitor discharges until the energy storage voltage becomes 0V.

And (3) circularly executing the steps A1-A3 until the timer reaches the preset time, and extracting the count of the counter.

The lock state signal LOL is a high-speed binary signal, when the lock state signal lol=1, it indicates that the CDR circuit is unlocked, when the lock state signal lol=0, it indicates that the CDR circuit is locked, as shown in fig. 3, in step A1, in a default state, the first switch SW1 is opened, the second switch SW2 is closed, a circuit between the power supply VCC and the forward input terminal of the comparator COMP is opened, at this time, the power supply va=0 received by the forward input terminal of the comparator COMP, after a preset clock period, the second switch SW2 is opened, when the lock state signal lol=1 (unlock signal) received by the control terminal of the first switch SW1 is triggered, the circuit between the power supply VCC and the forward input terminal of the comparator COMP is turned on, the power supply VCC charges to the power supply C, so that the power supply Va is slowly increased, the comparator COMP compares the power supply Va with the reference voltage Vth in real time, and when the power supply voltage Vth > is counted once, the counter is triggered.

In this application, when the energy storage voltage Va has not risen to Va > reference voltage Vth, the control end of the first switch SW1 jumps to the locking signal, i.e. lol=0, and triggers the first switch SW1 to be turned off, the second switch SW2 maintains the off state, at this time, the energy storage voltage Va will maintain the current value under the influence of the capacitor C, and when the locking signal jumps again, the capacitor C is continuously charged to make the energy storage voltage Va continuously rise until the energy storage voltage Va > reference voltage Vth, the counter completes one counting, and after the counter completes one counting, the first switch is turned off, the second switch is turned on, so that the capacitor discharges until the energy storage voltage becomes 0V.

In a preferred embodiment, as shown in fig. 3, the bit error rate statistics module further includes a current detection sensor 22 for detecting a charging current corresponding to the capacitor, where the current detection sensor 22 is connected in series between the power supply VCC and the first connection terminal of the first switch SW1, and the module current is the charging current detected by the current detection sensor 22.

In another preferred embodiment, the microprocessor determines the corresponding bit error rate for the high-speed data input to the CDR lock detection circuit at the current clock phase by the following equation:

in the course of this formula (ii) the formula,indicating bit error rate +.>Indicating that the predetermined time +.>After that, the number of counts extracted by the counter, < >>Representing module current +.>Representing the data input frequency, i.e. the input frequency of the lock state signal (being a known value), wherein ∈>Is the number of single bit errors.

Referring to fig. 5, fig. 5 is a flowchart illustrating a step of determining an eye edge point according to an embodiment of the present application. In a preferred embodiment, the method further comprises:

the microprocessor adjusts the reference voltage of the CDR locking detection circuit within a preset voltage range according to a preset step length, determines a left edge point EYELEFT and a right edge point EYERIGHT for each adjustment, and draws and forms an eye pattern according to the left edge point EYELEFT and the right edge point EYERIGHT corresponding to each reference voltage.

As shown in fig. 5, each adjustment, performed:

s11. the microprocessor sets a first count number err_cur=1, an initial value of the clock phase pi=180°, a count threshold thres, and an eye transition number thru_open=0.

S12, the bit error rate statistics module receives a locking state signal generated by the CDR locking detection circuit under the current clock phase, and the timer starts to count, and counts second count times ERR_NEW of an unlocking signal generated by the CDR locking detection circuit under the current clock phase within a preset time.

S13, the microprocessor determines the position of the clock phase PI according to the first count number ERR_CUR, the second count number ERR_NEW and the set number threshold thres.

S14. if the clock phase PI is at the eye opening part, let err_cur=err_new and let pi=pi-preset movement step, and return to step S12.

S15. if the clock phase PI is at the edge where the eyes OPEN to close, the left edge point eyleft=pi is determined, the number of eye transitions thru_open=thru_open+1, and the process returns to step S12.

S16. if the clock phase PI is at the edge where the eye is closed to OPEN, the number of eye transitions thru_open=thru_open+1, and the right edge point eye=pi is determined.

S17, if thru_open=2, the values of eyleft and yeright are output, and if thru_open++2, an error report is presented.

And (5) circulating S11-S17 to obtain a left edge point EYELEFT value and a right edge point EYERIGHT corresponding to each reference voltage in a preset voltage range, and drawing to form an eye pattern.

The threshold value thres of the set times is related to the error tolerance, if the tolerance is higher, the threshold value can be set higher, the value of the threshold value thres of the set times can be 2-6, and the threshold value thres is set according to the actual error tolerance requirement.

Specifically, referring to fig. 6, fig. 6 is a schematic diagram illustrating an eye diagram drawing according to an embodiment of the present application. As shown in fig. 6, the horizontal axis x of the eye diagram represents the clock phase, the vertical axis y of the eye diagram represents the reference voltages corresponding to DFF in the CDR lock detection circuit, each reference voltage corresponds to a left edge point EYELEFT and a right edge point eyright, the left edge point EYELEFT and the right edge point eyright corresponding to each reference voltage can be determined by calling the error rate statistics module, and the left edge point EYELEFT and the right edge point eyright corresponding to each reference voltage are connected to form a corresponding eye diagram.

In a preferred embodiment, step S13 includes:

if err_cur is less than or equal to thres and err_new is > thres, then the clock phase PI is determined to be in the eye open portion, if err_cur is less than thres and err_new is > thres, then the clock phase PI is determined to be in the eye open to closed edge, and if err_cur is greater than thres and err_new is less than or equal to thres, then the clock phase PI is determined to be in the eye closed to open edge.

In another preferred embodiment, step S14 includes:

s141 let err_cur=err_new and let pi=pi-preset movement step.

S142, obtaining the total phase adjustment quantity delta PI between the current clock phase and the initial value of the clock phase.

S143, judging whether THRU_OPEN is not equal to 2 and delta PI is not less than 360 degrees;

s144, if the THRU_OPEN is not equal to 2 and delta PI is not less than 360 degrees, error reporting is carried out;

s145, if THRU_OPEN is not equal to 2 and δPI is not less than 360 degrees, returning to the step S12.

Referring to fig. 7, fig. 7 shows a second flowchart of a step of determining an eye edge point according to an embodiment of the present application. The above-mentioned step of determining the eye edge point is applied to a specific embodiment, and may be performed according to the flow shown in fig. 7, and specifically is as follows:

s71, acquiring a detection state corresponding to the CDR locking detection circuit.

The detection state comprises detection normal and detection abnormal, in the application, the CDR locking detection circuit loses lock and loses signal in the initialization process, the detection state is determined to be the detection abnormal, and otherwise, the detection state is determined to be the detection normal.

S72, judging whether the detection state is normal.

If the detection state is abnormal, the routine returns to S71.

S73, if the detection state is normal, err_cur=1, pi=180°, thres, thru_open=0, and a predetermined time count_tim are set.

Thres can be set according to the error tolerance, and if the tolerance is high, the threshold Thres can be set to be 2-6 for higher times.

S74, counting in the count_tim by the bit error rate statistics module to obtain ERR_NEW.

S75, judging whether ERR_CUR is less than or equal to Thres and ERR_NEW is more than Thres.

S76, if err_cur is less than or equal to Thres and err_new > Thres, let err_cur=err_new, pi=pi- θ.

θ represents a preset moving step length, positive and negative of θ may represent a moving direction, that is, a preset direction, θ represents a leftward movement if positive, a preset direction is a leftward movement, θ represents a rightward movement if negative, and θ may take a value of 1.

S77, determine whether thru_open+.2 and δpi+=360° are satisfied.

The current clock phase starts to move from an initial value, the supply and demand move 360 degrees, namely after the clock returns to the original position, two hops from closed to open and from open to closed are carried out at the left edge point and the right edge point corresponding to the eye pattern.

S78, if thru_open+.2 and δpi+=360°, the reception of the lock state signal is stopped and an error report is performed.

Here, it is explained that when the total phase adjustment amount has reached 360 °, but thru_open is not equal to 2, it is explained that the left and right edge points at the same reference voltage of the DFF are not completely found, and at this time, an error report is required.

If thru_open+.2 is not satisfied and δpi+=360°, the process returns to step S74.

S79, if ERR_CUR is not less than or equal to Thres and ERR_NEW is greater than or equal to Thres, judging whether ERR_CUR is greater than or equal to Thres and ERR_NEW is less than or equal to Thres.

S80, if err_cur > Thres is satisfied and err_new is less than or equal to Thres, then thru_open=thru_open+1.

If ERR_CUR > Thres is not satisfied and ERR_NEW is less than or equal to Thres, the process returns to step S76.

S81, it is determined whether thru_open=2 is satisfied.

If thru_open is not equal to 2, the current clock phase PI is written into eyleft, and the process returns to step S76.

When err_cur > Thres and err_new is less than or equal to Thres, it is indicated that the current clock phase PI moves to the edge where the eyes are OPEN to close, at this time, thru_open=1, if the preset direction is left, the current clock phase PI is the left edge point, as shown in the figure, in the process that the current clock phase PI moves leftwards from the initial position O, err_new measured at the next time is normally greater than or equal to err_new measured at the previous time, when err_new measured at the next time suddenly increases, it is indicated that the phase edge point is reached, at this time, thru_open=1, it is indicated that only one edge point is determined, and at this time, the movement along the preset direction needs to be continued.

S82, if thru_open=2, the current clock phase PI is written into eyright.

S83, ending the edge determination process.

Specifically, the DFF in the CDR lock detection circuit is adjusted to be within a preset voltage range l±200-500 mv, the preset step length may be ±1-20 mv, that is, the DFF moves along a longitudinal range L as shown in the figure, each moving position S1-S3 is shown in the figure, the above S11-S18 is executed, a corresponding left edge point and a right edge point under the DFF reference voltage at the moving position are obtained, and finally, an eye pattern is obtained by connection.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solutions of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solutions, or in the form of a software product, which is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A signal quality detection method, characterized in that it is applied to a bit error rate detection circuit, the bit error rate detection circuit includes a bit error rate statistics module, a timer and a microprocessor, the method includes:

the error rate statistics module receives a locking state signal generated by the CDR locking detection circuit, and the timer starts timing;

the error rate statistics module triggers one-time counting when the CDR locking detection circuit generates an unlocking signal;

when the microprocessor detects that the timer reaches the preset time, the timer is cleared, the counting times stored by the bit error rate statistics module are extracted, and the bit error rate of high-speed data input into the CDR locking detection circuit under the clock phase corresponding to the CDR locking detection circuit is determined according to the counting times and the stored energy storage charging current corresponding to the bit error rate statistics module.

2. The method of claim 1, wherein the bit error rate statistics module comprises a first switch, a second switch, a capacitor, a comparator, and a counter, wherein the control terminal of the first switch is connected to the output terminal of the CDR lock detection circuit, the first connection terminal of the first switch is connected to the power supply, the second connection terminal of the first switch is connected to the positive input terminal of the comparator and one terminal of the capacitor, respectively, the other terminal of the capacitor is grounded, the negative input terminal of the comparator is connected to the reference voltage, the control terminal of the second switch is connected to the microprocessor, the first connection terminal of the second switch is connected to the positive input terminal of the comparator, the second connection terminal of the second switch is grounded, the output terminal of the comparator is connected to the input terminal of the counter, the output terminal of the counter is connected to the microprocessor,

the bit error rate statistics module completes trigger counting by the following method:

a1, a first switch and a second switch are opened, when a CDR locking detection circuit generates an unlocking signal, the first switch is triggered to be closed, so that the power supply charges a capacitor, and energy storage voltages are generated at two ends of the capacitor;

a2, the comparator compares the energy storage voltage with the reference voltage, and when the energy storage voltage is larger than the reference voltage, the counter is triggered to finish one-time counting;

a3, after the counter finishes counting once, the first switch is opened, and the second switch is closed, so that the capacitor discharges until the energy storage voltage becomes 0V;

3. The method of claim 2, wherein the bit error rate statistics module further comprises a current detection sensor for detecting a charging current corresponding to the capacitor, wherein the current detection sensor is connected in series between the power supply and the first connection terminal of the first switch, the module current is the charging current detected by the current detection sensor,

the microprocessor determines the bit error rate corresponding to the high-speed data input into the CDR locking detection circuit under the current clock phase according to the following formula:

in the course of this formula (ii) the formula,indicating bit error rate +.>Indicating that the predetermined time +.>After that, the number of counts extracted by the counter, < >>Representing module current +.>Representing the data input frequency, i.e. the input frequency of the lock state signal, wherein,representing comparator reference voltage, +.>Representing capacitance.

4. The method according to claim 1, wherein the method further comprises:

the microprocessor adjusts the reference voltage of the CDR locking detection circuit within a preset voltage range according to a preset step length, and for each adjustment, the microprocessor executes:

s11. the microprocessor sets a first count number err_cur=1, an initial value of a clock phase pi=180°, a count threshold thres, and an eye jump number thru_open=0;

s12, the bit error rate statistics module receives a locking state signal generated by the CDR locking detection circuit under the current clock phase, and simultaneously starts to count a timer, and counts second count times ERR_NEW of an unlocking signal generated by the CDR locking detection circuit under the current clock phase within a preset time;

s13, the microprocessor determines the position of the clock phase PI according to the first count number ERR_CUR, the second count number ERR_NEW and the set number threshold thres;

s14, if the clock phase PI is in the eye opening part, ERR_CUR=ERR_NEW and PI=PI-preset moving step length are made, and the step S12 is executed in a return mode;

s15, if the clock phase PI is at the edge of eye opening to eye closing, determining a left edge point EYELEFT=PI, the eye jump times THRU_OPEN=THRU_OPEN+1, and returning to the step S12;

s16. If the clock phase PI is at the edge where the eye is closed to OPEN, then the number of eye transitions thru_open=thru_open+1, determining the right edge point eye=pi;

s17. if thru_open=2, then output values of eyleft and eyright;

s18, if THRU_OPEN is not equal to 2, performing error reporting prompt;

and (5) circulating S11-S18 to obtain a left edge point EYELEFT value and a right edge point EYERIGHT corresponding to each reference voltage in a preset voltage range, and drawing to form an eye pattern.

5. The method according to claim 4, wherein step S13 includes:

if ERR_CUR is less than or equal to thres and ERR_NEW is greater than thres, determining that the clock phase PI is in the eye-opening portion;

if err_cur < thres and err_new > thres, determining that the clock phase PI is at the edge of eye open to closed;

if ERR_CUR > thres and ERR_NEW++thres, then clock phase PI is at the edge where the eye is closed to open.

6. The method of claim 5, wherein step S14 comprises:

s141. let err_cur=err_new and let pi=pi-preset movement step;

s142, acquiring the phase adjustment total amount delta PI between the current clock phase and the clock phase initial value;

7. A signal quality detection circuit is characterized in that the signal quality detection circuit comprises an error rate detection circuit and a CDR locking detection circuit, the error rate detection circuit comprises an error rate statistics module, a timer and a microprocessor, wherein,

the error rate statistics module triggers one-time counting when the lock losing signal is generated by the lock state signal;

8. The signal quality detection circuit of claim 7, wherein the bit error rate statistics module comprises a first switch, a second switch, a capacitor, a comparator and a counter, wherein the control end of the first switch is connected to the output end of the CDR lock detection circuit, the first connection end of the first switch is connected to a power supply, the second connection end of the first switch is respectively connected to the positive input end of the comparator and one end of the capacitor, the other end of the capacitor is grounded, the negative input end of the comparator is connected to a reference voltage, the control end of the second switch is connected to a microprocessor, the first connection end of the second switch is connected to the positive input end of the comparator, the second connection end of the second switch is grounded, the output end of the comparator is connected to the input end of the counter, and the output end of the counter is connected to the microprocessor;

wherein, the bit error rate statistics module:

9. The signal quality detection circuit of claim 8, wherein the bit error rate statistics module further comprises a current detection sensor for detecting a charging current corresponding to the capacitor, wherein the current detection sensor is connected in series between a power supply and the first connection terminal of the first switch, the module current is the charging current detected by the current detection sensor,

wherein the microprocessor is further configured to:

determining the corresponding error rate of high-speed data input into the CDR locking detection circuit under the current clock phase through the following formula:

in the course of this formula (ii) the formula,indicating bit error rate +.>Indicating that the predetermined time +.>After that, the number of counts extracted by the counter, < >>Representing module current +.>Represents the data input frequency, i.e., the input frequency of the lock state signal, where Vth represents the comparator reference voltage and C represents the capacitance.

10. The signal quality detection circuit of claim 7, wherein the microprocessor is further configured to: adjusting the reference voltage of the CDR locking detection circuit within a preset voltage range according to a preset step length, and executing for each adjustment:

s17. if thru_open=2, outputting values of eyleft and yeright, and if thru_open is not equal to 2, performing error reporting;