CN117478144A - Capacitor weighted segmented buffer - Google Patents

Capacitor weighted segmented buffer Download PDF

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Publication number
CN117478144A
CN117478144A CN202310934336.4A CN202310934336A CN117478144A CN 117478144 A CN117478144 A CN 117478144A CN 202310934336 A CN202310934336 A CN 202310934336A CN 117478144 A CN117478144 A CN 117478144A
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capacitor
buffer
terminal
circuit
weighted segment
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谢颂恩
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US18/208,878 external-priority patent/US20240039546A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention provides a capacitor weighted segment buffer, comprising: a push-pull buffer circuit comprising: a first transistor, a second transistor, and a plurality of capacitors, wherein the second connection of the first transistor and the second connection of the second transistor are coupled to the output node of the capacitor weighted segment buffer, the plurality of capacitors comprising: a first capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal for receiving a first input signal of the capacitor weighted segment buffer; a second capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal for receiving the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal for receiving a second input signal of the capacitor weighted segment buffer; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal for receiving the second input signal.

Description

Capacitor weighted segmented buffer
Technical Field
The invention relates to a buffer circuit design, in particular to a low-power consumption, ultra-small-area and high-precision capacitor weighted segmented buffer.
Background
Digital-to-analog converters (DACs) are used to convert digital inputs to analog outputs. The buffer is used to buffer or drive the analog input to generate an analog output and output it to a subsequent processing stage. DACs and buffers are common components in a variety of circuits. In general, buffers can be classified into open-loop buffers and closed-loop buffers. Open loop buffers are subject to process, voltage, temperature (PVT) variations. Furthermore, typical circuit designs often work with open loop buffers using a separate DAC, resulting in a large chip area due to lack of integration. The closed loop buffer achieves the required stability/phase margin performance (phase margin performance) at the expense of speed and energy. Therefore, there is a need for an innovative buffer with low power consumption, ultra small area, and high accuracy (accuracies).
As noted above, DACs and buffers are common components in a variety of circuits. For example, convolutional neural networks (convolutional neural network, CNN) used by artificial intelligence (artificial intelligence, AI) applications are composed of neurons (neurons) with a learnable weight. Each neuron receives an AI input and performs a dot product (i.e., convolution operation) on the AI input and the weights. One conventional approach employs a Central Processing Unit (CPU) to process convolution operations, which is not a power-efficient solution. Another conventional approach may employ a bit-wise (bit-wise) current-based or time-based memory (CIM) circuit to handle convolution operations, which is neither a power-saving solution nor a high-accuracy solution. Therefore, there is a need for an innovative buffer with low power consumption, ultra-small area, and high accuracy to meet the requirements of the ACIM circuits used in AI applications.
Disclosure of Invention
It is an object of the present invention to provide a low power consumption, ultra small area, high accuracy capacitor weighted segment buffer (capacitor weighted segmentation buffer). For example, the capacitor weighted segment buffer may be integrated with the digital-to-analog converter. For another example, the capacitor weighted segment buffer may be an analog CIM buffer.
In accordance with an aspect of the present invention, an exemplary capacitor weighted segment buffer is disclosed. An exemplary capacitor weighted segment buffer includes a push-pull buffer circuit and a plurality of capacitors. The push-pull buffer circuit comprises a first transistor and a second transistor, the first transistor has a control terminal, a first connection terminal and a second connection terminal, the second transistor has a control terminal, a first connection terminal and a second connection terminal, wherein the second connection terminal of the first transistor and the second connection terminal of the second transistor are coupled to an output node of the capacitor weighted segment buffer. The capacitor includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, the first capacitor having a first end coupled to the control end of the first transistor and a second end arranged to receive a first input signal of the capacitor weighted segment buffer; the second capacitor has a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the first input signal of the capacitor weighted segment buffer; the third capacitor has a first terminal coupled to the control terminal of the first transistor, and a second terminal arranged to receive a second input signal of the capacitor weighted segment buffer; the fourth capacitor has a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal of the capacitor weighted segment buffer. Each of the first capacitor and the second capacitor has a first capacitance value, and each of the third capacitor and the fourth capacitor has a second capacitance value different from the first capacitance value.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
Drawings
Fig. 1 is a schematic diagram illustrating a capacitor weighted segment buffer according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a first phase (e.g., RST mode) of discrete operations (discrete operation) performed at the capacitor-weighted segment buffer shown in fig. 1, in accordance with an embodiment of the invention.
Fig. 3 is a schematic diagram illustrating a second phase (e.g., BUF mode) of discrete operations performed at the capacitor weighted segment buffer shown in fig. 1, in accordance with an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a first phase of discrete operations (e.g., RST mode) performed by a first processing circuit integrated with a DAC and a buffer according to an embodiment of the invention.
Fig. 5 is a schematic diagram illustrating a second phase of discrete operations (e.g., BUF mode) performed by a first processing circuit integrated with a DAC and a buffer according to an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating a first phase (e.g., RST mode) of discrete operations performed at a second processing circuit integrated with a DAC and a buffer according to an embodiment of the invention.
Fig. 7 is a schematic diagram illustrating a second phase of discrete operations (e.g., BUF mode) performed at a second processing circuit integrated with a DAC and a buffer according to an embodiment of the invention.
Fig. 8 is a schematic diagram illustrating a first ACIM circuit using a capacitor weighted segment buffer as its output buffer according to an embodiment of the present invention.
Fig. 9 is a schematic diagram illustrating a second ACIM circuit using a capacitor weighted segment buffer as its output buffer according to an embodiment of the present invention.
Detailed Description
Certain terms are used throughout the following description and claims to refer to particular components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to a component by different names. This application is not intended to distinguish between components that differ in name but not function. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to … …". Moreover, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device couples to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 is a schematic diagram illustrating a capacitor weighted segment buffer according to an embodiment of the present invention. The capacitor weighted segment buffer 100 includes a push-pull buffer circuit 102, a plurality of capacitors C 11 -C 1N And C 21 -C 2N (N.gtoreq.2), a switching circuit 104, and a replica bias circuit (replica bias circuit) 106. The push-pull buffer circuit 102 includes: two transistors M1 and M2. For example, the transistor M2 may be implemented by a P-channel metal-oxide-semiconductor (PMOS) transistor, and the transistor M1 may be implemented by an N-channel metal-oxide-semiconductor (NMOS) transistor. As shown in fig. 1, a transistor (e.g., an NMOS transistor) M1 has a control terminal (e.g., a gate terminal) and two connection terminals (e.g., a source terminal and a drain terminal), one of which is coupled to a reference terminal (e.g., a power supply voltage VDD), and the other of which is coupled to an output node n_out of the capacitor weighted segment buffer 100. In addition, the transistor (e.g., PMOS transistor) M2 has a control terminal (e.g., gate terminal) and two connection terminals (e.g., source terminal and drain terminal), one of which is coupled to another reference voltage (e.g., ground voltage GND) and the other of which is coupled to the output node n_out of the capacitor weighted segment buffer 100. In some embodiments of the present invention, the output node n_out of the capacitor weighted segment buffer 100 is coupled to a subsequent processing stage. In other words, the capacitor weighted segment buffer 100 may act as an output buffer or output driver for driving subsequent processing stages. For example, the subsequent processing stage may be an ACIM circuit.
Capacitor C 11 Having a first end (e.g., top plate) coupled to the control end of transistor M1 and a clothA second terminal (e.g., a backplane) positioned to receive a first input signal v_in1 of the capacitor weighted segment buffer 100. C (C) 21 Having a first end (e.g., a bottom plate) coupled to a control end of transistor M2 and a second end (e.g., a top plate) arranged to receive a first input signal v_in1 of capacitor weighted segment buffer 100. Capacitor C 12 Having a first terminal (e.g., a top plate) coupled to a control terminal of the transistor Ml, and a second terminal (e.g., a bottom plate) arranged to receive a second input signal v_in2 of the capacitor weighted segment buffer 100. Capacitor C 22 Having a first terminal (e.g., a bottom plate) coupled to a control terminal of transistor M2, and a second terminal (e.g., a top plate) arranged to receive a second input signal v_in2 of capacitor weighted segment buffer 100. Capacitor C 1N Having a first terminal (e.g., a top plate) coupled to a control terminal of transistor Ml and a second terminal (e.g., a bottom plate) arranged to receive an nth input signal v_inn of capacitor weighted segment buffer 100. Capacitor C 2N Having a first terminal (e.g., a bottom plate) coupled to a control terminal of transistor M2 and a second terminal (e.g., a top plate) arranged to receive an nth input signal v_inn of capacitor weighted segment buffer 100.
Capacitor C 1i And C 2i All have the same capacitance value CVi, where i= {1,2, …, N }. In addition, the capacitance CV 1 -CV N Including different capacitance values. For example, capacitance CV 1 Greater than the capacitance CV 2 And CV (CV) N Each of which has a capacitance CV 2 Greater than the capacitance CV N . Also for example, capacitor C 11 、C 12 、…、C 1N Forms a binary weighted capacitor array (binary weighted capacitor array), capacitor C 21 、C 22 、…、C 2N Constituting another binary weighted capacitor array. However, these are for illustrative purposes only and are not meant to limit the invention. In practice, the capacitance CV 1 -CV N The settings of (c) may be adjusted according to practical design considerations. Further, a capacitor C 11 -C 1N And C 21 -C 2N The number of (N.gtoreq.2) may be adjusted according to practical design considerations.
In the present embodiment, the push-pull buffer circuit 102 operates as a discrete-time push-pull buffer. Specifically, the discrete-time operation of the push-pull buffer circuit 102 includes a first phase in which the push-pull buffer circuit 102 operates in a Reset (RST) mode and a second phase in which the push-pull buffer circuit 102 operates in a Buffer (BUF) mode. The mode switching of the push-pull buffer circuit 102 is controlled by a switching circuit 104, which switching circuit 104 may be implemented using a plurality of switches. Specifically, the switching circuit 104 is arranged to support two configurations cfg_1 and cfg_2. When the switch circuit 104 is controlled to have a configuration cfg_1 (which is defined by the ON/OFF states of the switches in the switch circuit 104), the push-pull buffer circuit 102 operates in RST mode. When the switching circuit 104 is controlled to have a configuration cfg_2 (which is defined by the ON/OFF states of the switches in the switching circuit 104), the push-pull buffer circuit 102 operates in BUF mode.
As shown IN fig. 1, the switching circuit 104 is coupled between the replica bias circuit 106 and the control terminals of the transistors M1 and M2, and is further coupled at a plurality of input nodes n_in1, n_in2, n_inn, and capacitor C of the capacitor weighted segment buffer 100 11 -C 1N And C 21 -C 2N Wherein the input nodes n_in1-n_inn are arranged to receive input signals v_in1-v_inn, respectively, from a previous processing stage. The replica bias circuit 106 is arranged to generate one bias voltage Nbias for the transistor M1 (e.g. NMOS transistor) and to generate another bias voltage for the transistor M2 (e.g. PMOS transistor). Please refer to fig. 2 and 3. Fig. 2 is a schematic diagram illustrating a first phase (e.g., RST mode) of discrete operations performed at the capacitor weighted segment buffer 100 according to an embodiment of the present invention. Fig. 3 is a schematic diagram illustrating a second phase of discrete operations (e.g., BUF mode) performed at the capacitor weighted segment buffer 100 according to an embodiment of the present invention. For the sake of brevity, the weighting capacitor C 11 -C 1N (N.gtoreq.2) is represented collectively in FIG. 2 and FIG. 3 by a capacitor Ctop. Weighting capacitor C 21 -C 2N (N.gtoreq.2) is commonly represented in FIGS. 2 and 3 by a capacitor Cbot, and, an inputThe input signals v_in1-v_inn are collectively represented by one input signal (which is an analog input) vi. When the push-pull buffer circuit 102 is operated in RST mode due to the configuration cfg_1 of the switch circuit 104, the replica bias circuit 106 generates and outputs a bias voltage Nbias to the control terminal of the transistor M1, and generates and outputs a bias voltage Pbias to the control terminal of the transistor M2. When the push-pull buffer circuit 102 is operating in BUF mode due to the switch circuit 104 having the configuration cfg_2, the replica bias circuit 106 is disconnected from the push-pull buffer circuit 102. Since the replica bias circuit 106 is used to set the bias voltages Nbias and Pbias of the push-pull buffer circuit 102, the corresponding currents of the bias voltages Nbias and Pbias remain stable at PVT variations, so that the gain of the push-pull buffer circuit 102 does not vary with PVT variations. In other words, with the PVT tracking capability of the replica bias circuit 106, the push-pull buffer circuit 102 has a stable and strong buffering capability over all PVT variations.
IN addition, when the push-pull buffer circuit 102 operates IN the RST mode due to the switch circuit 104 having the configuration cfg_1, the input node n_in1 (specifically, the input signal v_in1 received by the input node n_in1) and the capacitor C 11 And C 21 Disconnected, input node n_in2 (specifically, input signal v_in2 received by input node n_in2) and capacitor C 12 And C 22 Disconnected and input node n_inn (specifically, input signal v_inn received by input node n_inn) and capacitor C 1N And C 2N Disconnecting the connection. In addition, a common-mode voltage vcm serving as a reset voltage is applied to all the weighting capacitors C 11 -C 1N And all weighting capacitors C 21 -C 2N Is a top plate of the (c). When the push-pull buffer circuit 102 is operated IN the BUF mode due to the configuration CFG_2 of the switch circuit 104, the input signal V_In1 received by the input node N_In1 is transmitted to the capacitor C 11 And C 21 (specifically, capacitor C 11 Bottom plate of (C) and capacitor C 21 A top plate) of (a) a top plate). The input signal V_In2 received by the input node N_In2 is transferred to the capacitor C 12 And C 22 (specifically, capacitor C 12 Bottom plate of (d) and capacitorC 22 Top plate of (C), and the input signal n_inn received by the input node v_inn is transmitted to the capacitor C 1N And C 2N (particularly capacitor C 1N Is connected to the bottom plate of the capacitor C 2N A top plate) of (a) a top plate).
By a weighted capacitor array C 11 -C 1N Charge redistribution (charge redistribution) between capacitors and weighted capacitor array C 21 -C 2N The charge redistribution among the capacitors combines the input signals v_in1-v_inn (which are analog inputs), and the capacitor-weighted segment buffer 100 generates an output signal v_out (which is an analog output) at an output node n_out. Thus, the previous processing stage (which provides the input signals v_in1-v_inn) may utilize the capacitor weighted segment buffer 100 to reduce complexity, e.g., reduce nodes (energy). Furthermore, since the push-pull buffer 102 is used as a discrete-time buffer instead of a continuous-time buffer, it allows integration of digital-to-analog converters (DACs) and buffers. In one exemplary embodiment, the capacitor weighted segment buffer 100 may be integrated with a DAC to achieve chip area reduction.
Please refer to fig. 4 and 5. Fig. 4 is a schematic diagram illustrating a first phase (e.g., RST mode) of discrete operations performed at a first processing circuit integrated with a DAC and a buffer according to an embodiment of the invention. Fig. 5 is a schematic diagram illustrating a second phase of discrete operations (e.g., BUF mode) performed at a first processing circuit integrated with a DAC and a buffer, according to an embodiment of the invention. In this embodiment, the processing circuit 400 includes a capacitor having four capacitors C 11 ＝16C、C 1N ＝1C(N＝2)、C 21 =16c and C 2N Capacitor weighted segment buffer 100 of=1c (n=2). As shown in fig. 4, when the push-pull buffer circuit 102 operates in RST mode due to the switch circuit 104 having the configuration cfg_1, the bias voltage Nbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M1, the bias voltage Pbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M2, and is defined by V<0>The set common mode voltage vcm is applied to all capacitors C 11 ＝16C，C 1N ＝1C(N＝2)，C 21 =16c, and C 2N ＝1C(N＝2)。
Processing circuit 400 employs DAC and buffer integration, with the DAC sharing capacitor C used by capacitor weighted segment buffer 100 11 ＝16C、C 1N ＝1C(N＝2)、C 21 =16c and C 2N =1c (n=2). In this embodiment, the DAC includes a resistor digital-to-analog converter (RDAC) 402 and a capacitor digital-to-analog converter (CDAC) 404, where capacitor C 11 ＝16C，C 1N ＝1C(N＝2)、C 21 =16c and C 2N =1c (n=2) is used by the CDAC 404. For certain applications, such as artificial intelligence (artificial intelligence, AI) applications, multiple processing circuits 400 may be used to provide multiple AI inputs to subsequent processing stages, such as ACIM circuits, for convolution analog computation. In some embodiments of the invention, RDAC 402 used by one processing circuit 400 may be shared by other processing circuits 400 to reduce hardware and cost. However, this is for illustrative purposes only and is not meant to limit the invention.
As shown IN fig. 5, when the push-pull buffer circuit 102 is operated IN the BUF mode due to the switch circuit 104 having the configuration cfg_2, the input signals v_in1 and v_in2 (i.e., n=2) generated by the DACs (including the RDACs 402 and the CDAC 404) are transferred to the capacitor C 11 ＝16C、C 1N ＝1C(N＝2)、C 21 =16c and C 2N =1c (n=2). Assume that the digital code da_vin of the DAC (including RDAC 402 and CDAC 404) has 8 bits. For example, a digital code DA_vin<7:0>May be one of the input data of the neural network used by the AI application. In the present embodiment, the digital code da_vin<7:0>Is divided into two 4-bit (4 b, 4-bit) segments, including a most significant bit (most significant bit, MSB) segment DA_vin<7:4>And a least significant bit (least significant bit, LSB) segment DA_vin<3:0>. Thus, RDAC 402 uses a voltage reference voltage level V that is arranged to provide a plurality of reference voltage levels<15:0>4b RDAC of (a). The CDAC404 includes two 4b decoders 406 and 408. The 4b decoder 406 functions as a multiplexer (multiplexer) and is arranged to be dependent on the MSB segment DA_vin<7:4>Selecting and inputtingOutput reference voltage level V<15:0>As an input signal V_In1, wherein the input signal V_In1 is applied to a capacitor C 11 Bottom plate of =16c and capacitor C 21 Top plate of=16c. The 4b decoder 408 acts as a multiplexer based on the LSB segment DA_vin<3:0>Select and output reference voltage level V<15:0>As an input signal v_in2 (i.e. v_inn, n=2), wherein the input signal v_in2 (i.e. v_inn, n=2) is applied to the capacitor C 1N Bottom plate of=1c (n=2) and capacitor C 2N Top plate of=1c (n=2).
The segmented designs shown in fig. 4 and 5 are for illustration purposes only and are not meant to limit the invention. In practice, the segment design may be adjusted depending on practical design considerations.
Please refer to fig. 6 and 7. Fig. 6 is a schematic diagram illustrating a first phase of discrete operations (e.g., RST mode) performed at a second processing circuit integrated with a DAC and a buffer, according to an embodiment of the invention. Fig. 7 is a schematic diagram illustrating a second phase of discrete operations (e.g., BUF mode) performed at a second processing circuit integrated with a DAC and a buffer, according to an embodiment of the invention. In this embodiment, the processing circuit 600 includes a capacitor having six capacitors C 11 ＝16C、C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 = C, C22 =4c and C 2N Capacitor weighted segment buffer 100 of=1c (n=3). As shown in fig. 6, when the push-pull buffer circuit 102 operates in RST mode due to the switch circuit 104 having the configuration cfg_1, the bias voltage Nbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M1, the bias voltage Pbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M2, and the voltage is defined by V<0>The set common mode voltage vcm is applied to the capacitor C 11 ＝16C，C 12 ＝4C，C 1N ＝1C(N＝3)，C 21 ＝16C，C 22 =4c, and C 2N ＝1C(N＝3)。
The processing circuit 600 employs DAC and buffer integration, the DAC sharing the capacitor C used by the capacitor weighted segment buffer 100 11 ＝16C、C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 ＝16C、C 22 =4c and C 2N =1c (n=3). In this embodiment, the DAC includes RDAC 602 and CDAC 604, where capacitor C 11 ＝16C，C 12 ＝4C，C 1N ＝1C(N＝3)，C 21 ＝16C，C 22 =4c and C 2N =1c (n=3) is used by the CDAC 604. For certain applications, such as AI applications, multiple processing circuits 600 may be used to provide multiple AI inputs to subsequent processing stages (e.g., ACIM circuits). Thus, RDAC 602 used by one processing circuit 600 may be shared by other processing circuits 600 to reduce hardware and cost. However, this is for illustrative purposes only and is not meant to limit the invention.
As shown IN fig. 7, when the push-pull buffer circuit 102 is operating IN BUF mode due to the switch circuit 104 having the configuration cfg_2, the input signals v_in1, v_in2, and v_in3 (i.e., v_inn, n=3) generated by the DACs (including the RDAC 602 and the CDAC 604) are transferred to the capacitor C 11 ＝16C、C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 ＝16C、C 22 =4c and C 2N =1c (n=3). Assume that the digital code da_vin of the DAC (including RDAC 402 and CDAC 404) has 6 bits. For example, a digital code DA_vin<5:0>May be one of the input data of the neural network used by the AI application. In the present embodiment, the digital code da_vin<5:0>Is divided into three 2-bit (2-bit, 2 b) segments including MSB segment DA_vin<5:4>Center significant (center significant bit, CSB) segment DA_vin<3:2>And LSB segment DA_vin<1:0>. Thus, RDAC 602 uses a voltage reference voltage level V that is arranged to provide a plurality of reference voltage levels<3:0>Is realized by 2b RDAC. The CDAC 604 includes three 2b decoders 606, 608, and 610. The 2b decoder 606 functions as a multiplexer (multiplexer) and is arranged to be dependent on the MSB segment DA_vin<5:4>Select and output reference voltage level V<3:0>As an input signal V_In1, wherein the input signal V_In1 is applied to a capacitor C 11 Bottom plate of =16c and capacitor C 21 Top plate of=16c. The 4b decoder 608 acts as a multiplexer for the data from the CSB segment DA_vin<3:2>Select and output reference voltage level V<3:0>One of (a)A plurality of reference voltage levels as an input signal V_In2, wherein the input signal V_In2 is applied to the capacitor C 12 Bottom plate of=4c and capacitor C 22 Top plate of=4c. The 4b decoder 410 acts as a multiplexer, based on the LSB segment DA_vin<1:0>Select and output reference voltage level V<3:0>As an input signal v_in3 (i.e., v_inn of n=3), wherein the input signal v_in3 (i.e., v_inn of n=3) is applied to the capacitor C 1N Bottom plate of =1c (n=3) and capacitor C 2N Top plate of=1c (n=3).
In summary, the processing circuit 400/600 integrated with the DAC and buffer uses a push-pull buffer circuit 102 biased by a replica bias circuit 106 that has stable and strong buffering/driving capability over all PVT variations, provides high DAC resolution using accurate RDACs 402/602 and CDACs 404/604, and uses appropriate segmentation to reduce nodes (energy). With the traditional DAC needs 2 8 Individual nodes to provide 2 8 The DACs including RDACs 402/602 and CDACs 406/606 require fewer nodes and thus occupy less chip area than the individual voltage levels alternatives.
In another exemplary embodiment, the capacitor weighted segment buffer 100 may be used as an ACIM buffer. Fig. 8 is a schematic diagram illustrating a first ACIM circuit using a capacitor weighted segment buffer as its output buffer according to an embodiment of the present invention. In this embodiment, the ACIM circuitry is implemented using the memory array 802. For example, the ACIM circuit is a static random access memory (static random access memory, SRAM) based CIM circuit that performs multiply and accumulate (multiplication and accumulation, MAC) operations in an analog (analog) manner. In the present embodiment, the capacitor-weighted segment buffer 100 has four capacitors C 11 ＝16C、C 1N ＝1C(N＝2)、C 21 =16c and C 2N =1c (n=2). When the push-pull buffer circuit 102 operates in RST mode due to the switch circuit 104 having the configuration cfg_1, the bias voltage Nbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M1, the bias voltage Pbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M2, and the common mode voltage Vcm is appliedApplied to capacitor C 11 ＝16C，C 1N ＝1C(N＝2)，C 21 =16c, and C 2N ＝1C(N＝2)。
When the push-pull buffer circuit 102 is operated IN the BUF mode due to the configuration CFG_2 of the switch circuit 104, the input voltages V_In1 and V_In2 (i.e. N=2) are transferred to the capacitor C 11 ＝16C，C 1N ＝1C(N＝2)，C 21 =16c and C 2N =1c (n=2). As shown IN fig. 8, the input voltages v_in1 and v_in2 (i.e., n=2) are generated by an ACIM circuit implemented using the memory array 802. The ACIM circuit is assumed to be used for AI applications to handle MAC operations. Thus, each of the input voltages v_in1 and v_in2 (i.e., n=2) corresponds to one input data of the neural network used by the AP application. For example, the AI input includes 64 8b input data IN 1 [7:0]-IN 64 [7:0]And is converted to analog input, e.g. 64 8b input data IN are input by 64 processing circuits 400/600 1 [7:0]-IN 64 [7:0]Respectively converted to analog inputs. The memory array 802 stores 64 8b weights W 1 [7:0]-W 64 [7:0]And receives input data IN representing 8b 1 [7:0]-IN 64 [7:0]Is a digital input. Based on the 8b input data and the 8b weights, the ACIM circuit has difficulty in implementing multiplication and accumulation. To reduce complexity, 8b weight W 1 [7:0]-W 64 [7:0]Is divided into MSB segments W [7:4 ]]And LSB segment W [3:0 ]]And the ACIM circuit includes two processing circuits (e.g., SRAM-based CIM circuits) 804 and 806. The processing circuit 804 is arranged to process 4b weight (4 bW) MSB bit line/word line (BL/WL) operations. Thus, the processing circuit 804 inputs the data IN according to the representation 8b 1 [7:0]-IN 64 [7:0]Is a weight of 8b W 1 [7:0]-W 64 [7:0]MSB segment W of (2) 1 [7:4]-W 64 [7:4]An input signal v_in1 is generated and output to a capacitor weighted segment buffer (which serves as an ACIM buffer) 100. The processing circuit 806 is arranged to process 4b weight (4 bW) LSB BL/WL operations. Thus, the processing circuit 806 inputs data IN according to the representation 8b 1 [7:0]-IN 64 [7:0]Is a weight of 8b W 1 [7:0]-W 64 [7:0]LSB segment W of (B) 1 [3:0]-W 64 [3:0]An input signal v_in2 (i.e., v_inn, n=2) is generated and output to a capacitor weighted segment buffer (which acts as an ACIM buffer) 100. The generation of the input signals v_in1 and v_in2 (i.e., n=2) can be expressed simply using the following equation:
the capacitor weighted segment buffer 100 passes through the weighted capacitor array C 11 ＝16C、C 1N Charge redistribution between capacitors in =1c (n=2) and weighting capacitor array C 21 ＝16C、C 2N Charge redistribution between capacitors in=1c (n=2) combines the input signals v_in1 and v_in2 (i.e., n=2) to produce an output signal v_out (which isAnalog output of (a).
The split design shown in fig. 8 is for illustrative purposes only and is not meant to limit the invention. In practice, the segment design may be adjusted according to practical design considerations. Fig. 9 is a schematic diagram illustrating a second ACIM circuit using a capacitor weighted segment buffer as its output buffer according to an embodiment of the present invention. In this embodiment, the ACIM circuitry is implemented using the memory array 902. For example, the ACIM circuit is an SRAM-based CIM circuit that performs MAC operations in an analog manner. In the present embodiment, the capacitor weighted segment buffer 100 has six capacitors C 11 ＝16C、C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 ＝16C、C 22 =4c and C 2N =1c (n=3). When the push-pull buffer circuit 102 operates in RST mode due to the switch circuit 104 having the configuration cfg_1, the bias voltage Nbias generated by the replica bias circuit 106 is applied to the control terminal of the transistor M1, and the bias generated by the replica bias circuit 106A voltage Pbias is applied to the control terminal of the transistor M2 and a common mode voltage Vcm is applied to the capacitor C 11 ＝16C、C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 ＝16C，C 22 =4c, and C 2N ＝1C(N＝3)。
When the push-pull buffer circuit 102 is operating IN the BUF mode due to the switching circuit 104 having the configuration cfg_2, the input voltages v_in1, v_in2 and v_in3 (i.e. v_inn with n=3) are transferred to the capacitor C 11 ＝16C，C 12 ＝4C、C 1N ＝1C(N＝3)、C 21 ＝16C、C 22 =4c and C 2N =1c (n=3). As shown IN fig. 9, the input voltages v_in1, v_in2, and v_in3 (i.e., n=3) are generated by an ACIM circuit implemented using the memory array 902. The ACIM circuit is assumed to be used for AI applications to handle MAC operations. Thus, each of the input voltages v_in1, v_in2, and v_in3 (i.e., v_inn of n=3) corresponds to one input data of the neural network used by the AP application. For example, the AI input includes 64 8b input data IN 1 [7:0]-IN 64 [7:0]And converted to analog inputs, for example, processed by 64 processing circuits 400/600, respectively. The memory array 902 stores 64 6b weights W 1 [5:0]-W 64 [5:0]And receives input data IN representing 8b 1 [7:0]-IN 64 [7:0]Is a digital input. To reduce complexity, 6b weight W 1 [5:0]-W 64 [5:0]Is divided into MSB segments W [5:4 ]]CSB segment W [3:2]And LSB segment W [1:0 ]]And the ACIM circuit includes three processing circuits (e.g., SRAM-based CIM circuits) 904, 906, and 908. The processing circuit 902 is arranged to process a 2b weight (2 bW) MSB BL/WL operation. Thus, the processing circuit 904 inputs data IN1[7:0 ] according to the representation 8b]-IN64[7:0]Is stored and the analog input of (1) and the stored 6b weight W1[5:0]-W64[5:0]MSB segment W1[5:4 ]]-W64[5:4]An input signal v_in1 is generated and output to a capacitor weighted segment buffer (which acts as an ACIM buffer) 100. The processing circuit 904 is arranged to process 2b weight (2 bW) MSB BL/WL operations. Thus, the processing circuitry 906 inputs data IN according to the representation 8b 1 [7:0]-IN 64 [7:0]Is a 6b weight W of analog input and storage 1 [5:0]-W 64 [5:0]CSB section W of (2) 1 [3:2]-W 64 [3:2]An input signal v_in2 is generated and output to a capacitor weighted segment buffer (which acts as an ACIM buffer) 100. The processing circuit 908 is arranged to process 2b weight (2 bW) LSB BL/WL operations. Thus, processing circuit 908 inputs data IN according to representation 8b 1 [7:0]-IN 64 [7:0]Is a 6b weight W of analog input and storage 1 [5:0]-W 64 [5:0]LSB segment W of (B) 1 [1:0]-W 64 [1:0]An input signal v_in3 (i.e., v_inn of n=3) is generated and output to a capacitor weighted segment buffer (which acts as an ACIM buffer) 100. The generation of the input signals v_in1, v_in2, and v_in3 (i.e., n=3) can be expressed simply using the following formulas.
The capacitor weighted segment buffer 100 passes through the weighted capacitor array C 11 ＝16C、C 12 ＝4C、C 1N Charge redistribution between capacitors in =1c (n=3) and weighting capacitor array C 21 ＝16C、C 22 ＝4C，
C 2N Charge redistribution between capacitors in=1c (n=3) combines the input signals v_in1, v_in2, and v_in3 (i.e., n=3) to produce an output signal v_out (which isAnalog output of (a).
In summary, for an ACM circuit using a capacitor weighted segment buffer 100 as its output buffer, the push-pull buffer circuit 102 biased by the replica bias circuit 106 can provide stable and strong buffering/driving capability over all PVT variations, the weighted capacitor has a precise capacitance ratio for recombining the input signals, and proper segmentation of the weights results in node (energy) reduction as well as chip area reduction.
Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the appended claims.

Claims (17)

1. A capacitor weighted segment buffer comprising:
a push-pull buffer circuit comprising:
the first transistor is provided with a control end, a first connection end and a second connection end; and
a second transistor having a control terminal, a first connection terminal, and a second connection terminal, wherein the second connection terminal of the first transistor and the second connection terminal of the second transistor are coupled to the output node of the capacitor weighted segment buffer, and
a plurality of capacitors, comprising:
a first capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal for receiving a first input signal of the capacitor weighted segment buffer;
a second capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal for receiving the first input signal of the capacitor weighted segment buffer;
a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal for receiving a second input signal of the capacitor weighted segment buffer; and
a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal for receiving a second input signal of the capacitor weighted segment buffer;
wherein each of the first capacitor and the second capacitor has a first capacitance value, and each of the third capacitor and the fourth capacitor has a second capacitance value different from the first capacitance value.
2. The capacitor-weighted segment buffer of claim 1, wherein the plurality of capacitors further comprises:
a fifth capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal for receiving a third input signal of the capacitor weighted segment buffer; and
a sixth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal for receiving a third input signal of the capacitor weighted segment buffer;
wherein each of the fifth capacitor and the sixth capacitor has a third capacitance value different from any one of the first capacitance value and the second capacitance value.
3. The capacitor-weighted segment buffer of claim 1, further comprising:
a switching circuit arranged to support a first configuration and a second configuration, wherein the push-pull buffer circuit operates in a reset mode when the switching circuit has the first configuration and in a buffer mode when the switching circuit has the second configuration.
4. The capacitor-weighted segment buffer of claim 3, further comprising:
a replica bias circuit for generating a first bias voltage and outputting the first bias voltage to a control terminal of the first transistor, and generating a second bias voltage and outputting the second bias voltage to a control terminal of the second transistor when the push-pull buffer circuit operates in a reset mode.
5. The capacitor-weighted segment buffer of claim 4 wherein the replica bias circuit is disconnected from the push-pull buffer circuit when the push-pull buffer circuit is operating in the buffer mode.
6. The capacitively weighted segment buffer of claim 3, wherein when the push-pull buffer circuit is operating in the buffer mode, the first input signal is transferred to the second terminal of the first capacitor and the second terminal of the second capacitor; and when the push-pull buffer circuit is operating in the buffer mode, the second input signal is transferred to the second terminal of the third capacitor and the second terminal of the fourth capacitor.
7. The capacitor-weighted segment buffer of claim 6, wherein the first input signal is disconnected from the first capacitor and the second input signal is disconnected from the third capacitor and the fourth capacitor when the push-pull buffer circuit is operating in the reset mode.
8. The capacitor-weighted segment buffer of claim 3 wherein a common mode voltage is transferred to the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the third capacitor and the second terminal of the fourth capacitor when the push-pull buffer circuit is operating in the reset mode.
9. The capacitor weighted segment buffer of claim 1, wherein the capacitor weighted segment buffer is integrated with a digital-to-analog converter (DAC).
10. The capacitor-weighted segment buffer of claim 9, wherein the DAC comprises:
a resistor digital-to-analog converter (RDAC) for providing a plurality of reference voltage levels; and
a capacitor digital-to-analog converter (CDAC), wherein the CDAC uses a plurality of capacitors and the plurality of reference voltage levels are provided to the CDAC.
11. The capacitor-weighted segment buffer of claim 10, wherein the CDAC comprises:
the first capacitor;
the third capacitor;
the second capacitor;
the fourth capacitor;
a first decoder for selecting and outputting one of the plurality of reference voltage levels as the first input signal according to a first segment of a digital code of the DAC; and
and a second decoder for selecting and outputting one of the plurality of reference voltage levels as the second input signal according to a second segment of the digital code of the DAC.
12. The capacitor-weighted segment buffer of claim 11, wherein the digital code is an input data of a neural network.
13. The capacitor-weighted segment buffer of claim 9, wherein an output node of the capacitor-weighted segment buffer is coupled to an analog integrated memory (ACIM) circuit.
14. The capacitor-weighted segment buffer of claim 1, wherein the capacitor-weighted segment buffer is a buffer of an analog ACIM circuit.
15. The capacitor-weighted segment buffer of claim 14, wherein each of the first input signal and the second input signal is generated from an ACIM circuit, and the ACIM circuit comprises:
a plurality of processing circuits, comprising:
a first processing circuit for generating and outputting the first input signal based on a plurality of analog inputs and a plurality of first segments of stored data; and
a second processing circuit for generating and outputting the second input signal based on the plurality of analog inputs and a second segment of the plurality of stored data.
16. The capacitor-weighted segment buffer of claim 15, wherein each processing circuit of the plurality of processing circuits is a multiply-accumulate (MAC) circuit.
17. The capacitor-weighted segment buffer of claim 15, wherein each analog input corresponds to one input data of a neural network.
CN202310934336.4A 2022-07-28 2023-07-27 Capacitor weighted segmented buffer Pending CN117478144A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US63/369,673 2022-07-28
US63/369,674 2022-07-28
US63/376,125 2022-09-19
US18/208,878 2023-06-12
US18/208,878 US20240039546A1 (en) 2022-07-28 2023-06-12 Capacitor weighted segmentation buffer

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