CN117423723A - Power device capable of improving avalanche tolerance of super junction structure and preparation method - Google Patents
Power device capable of improving avalanche tolerance of super junction structure and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000011049 filling Methods 0.000 claims abstract description 17
- 230000001965 increasing effect Effects 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 149
- 229920005591 polysilicon Polymers 0.000 claims description 146
- 238000000034 method Methods 0.000 claims description 40
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- 238000000407 epitaxy Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
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- 238000000137 annealing Methods 0.000 description 3
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Abstract
The invention relates to a power device capable of improving avalanche resistance of a super junction structure and a preparation method thereof. The semiconductor substrate comprises an active region and a terminal protection region, wherein the active region is prepared in a central region of the semiconductor substrate, the terminal protection region is positioned on the outer ring of the active region, and the terminal protection region surrounds the active region, wherein the active region comprises a front cell unit and a super junction unit, the super junction unit comprises a plurality of first conductive type columns and second conductive type columns which are alternately distributed in sequence, and the conductive type of the first conductive type columns is consistent with the conductive type of the semiconductor substrate; and for any second conductive type column, the second conductive type column comprises a plurality of second conductive type column doped regions which are sequentially epitaxially filled in the second conductive type column grooves, wherein the doping concentration of the second conductive type column doped regions is sequentially increased according to the sequence of epitaxial filling in the second conductive type column grooves. The invention can effectively promote the avalanche energy of the super junction device and is compatible with the prior art.
Description
Technical Field
The invention relates to a power device based on a super junction structure and a preparation method thereof, in particular to a power device capable of improving avalanche tolerance of the super junction structure and a preparation method thereof.
Background
In the field of semiconductors, a chip is divided into a plurality of parts, and the chip is divided into four parts according to product standards: integrated circuits, discrete devices, optoelectronic devices, and sensors; and the power device is an important component belonging to the discrete device. The development of power devices, i.e. semiconductor devices for power processing, is also specifically classified into rectifying devices and switching devices, and the development of switching devices is always performed along both high frequency and high power, and different devices have upper limits of their own frequency and power due to structures, materials, etc., so many attempts are currently made to improve the above limitations by using new materials, new device structures and/or new working principles.
VDMOS devices and IGBT devices are power devices, and occupy most of market share, and in a circuit, the switching devices realize control of large current and large voltage through small current or small voltage, so that proper output is provided for subsequent circuits.
For an electrical power system, the consumption of energy is partly in the load and partly in the switching device. For such a switching device, it is desirable to achieve as little switching energy loss as possible while satisfying high frequency and high power conditions, thereby reducing the heat generation of the chip and the system. The MOSFET is a monopole type power switching device, has the characteristic of fast switching frequency, and is widely applied to radars, switching power supplies, automobile electronics, inverters and the like.
Most of the conventional silicon-based VDMOS is applied below 1000V, because the relationship between the withstand voltage and the specific on-resistance is natural 2.5 times, namely, the larger the withstand voltage is, the larger the specific on-resistance of the device is in a 2.5 times relationship, and the power consumption of the device is greatly increased, so that the structure of SJ (super junction) -MOS is invented on the basis of the MOSFET structure. The superjunction structure is that two semiconductor materials with opposite polarities are staggered to form an alternative structure of NPNP, which is also called a charge balance structure, and the structure can be verified theoretically.
The super-junction structure improves the 2.5 power relation between the voltage resistance and the specific on-resistance, and under the condition of the same voltage resistance, the super-junction structure has smaller chip area, which means that more super-junction MOS can be manufactured on the wafer with the same area. In one aspect, this is both an advantage of superjunctions and a disadvantage of superjunctions; this is because it can pass a larger current under the same withstand voltage condition, but because the chip area is smaller, the "heat energy" generated when a large voltage and a large current pass is more concentrated, that is, the super junction device may be disabled during the switching process UIS (Unclamped Inductive Switching) under the non-clamping inductive load, so that the avalanche resistance of the super junction device needs to be optimized to ensure the safe working capability of the device under various working conditions.
The semiconductor device is widely applied in a plurality of fields of automobile electronics, aerospace and the like, has higher requirements on the reliability and stability of the device, and is one of the most important capabilities in bearing avalanche. Under the power device UIS, the device can be applied to an inductive circuit, and during the opening process of the circuit, the inductive circuit can store a part of energy due to the self-property of the inductive circuit, the part of energy can be discharged through the device at the moment of being turned off, and the maximum energy which can be safely discharged is called avalanche resistance. The avalanche resistance back represents the device's exposure to extreme stresses under a portion of the extreme operating conditions. Accordingly, efforts are being made to optimize device structures, fabrication processes, application circuit conditions, etc. to improve avalanche resistance of devices to improve device reliability.
For the super junction MOS device, avalanche tolerance is mainly influenced by two factors, on one hand, in the process of the UIS, a parasitic NPN transistor near the MOS structure PWELL is conducted, so that avalanche current is uncontrolled, and the device is possibly invalid. On the other hand, in the superjunction UIS process, the avalanche current is too concentrated to cause heat loss, thereby affecting the failure of the device. Therefore, the effective improvement of avalanche resistance of the super junction MOS device is a technical problem which needs to be solved at present.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a power device capable of improving avalanche tolerance of a superjunction structure and a preparation method thereof, which can effectively improve avalanche energy of the superjunction device and is compatible with the prior art.
According to the technical proposal provided by the invention, the power device capable of improving the avalanche resistance of the super junction structure comprises an active region prepared in the central region of a semiconductor substrate and a terminal protection region positioned on the outer ring of the active region, wherein the terminal protection region surrounds the active region in a surrounding way,
the active region comprises a front cell unit and a superjunction unit, wherein the superjunction unit comprises a plurality of first conductive type columns and second conductive type columns which are alternately distributed in turn, and the conductive type of the first conductive type columns is consistent with that of the semiconductor substrate;
and for any second conductive type column, the second conductive type column comprises a plurality of second conductive type column doped regions which are sequentially epitaxially filled in the second conductive type column grooves, wherein the doping concentration of the second conductive type column doped regions is sequentially increased according to the sequence of epitaxial filling in the second conductive type column grooves.
The semiconductor substrate includes a substrate of a first conductivity type and a drift region of the first conductivity type on the substrate, wherein,
The first conductivity type drift region is adjacent to the substrate;
the super junction unit is prepared in the first conductive type drift region, and the bottoms of the first conductive type columns and the bottoms of the second conductive type columns are positioned at the joint of the first conductive type drift region and the substrate;
the positive cell unit comprises a plurality of positive cells distributed in parallel;
on the section of the power device, for any positive cell, the power device comprises a first conductive type base region and second conductive type well regions symmetrically distributed on two sides of the first conductive type base region, wherein the first conductive type base region is positioned above a first conductive type column and is in contact with the first conductive type column, and the width of the first conductive type base region is smaller than that of the first conductive type column;
the width of the second conductive-type well region is larger than the width of the second conductive-type column, and the second conductive-type well region is in contact with the corresponding first conductive-type column and the second conductive-type column.
When the front cell adopts a planar cell, a first conductive type source region and a second conductive type heavily doped region are arranged in a second conductive type well region, wherein,
the second conductive type heavily doped region comprises a second conductive type first heavily doped region and a second conductive type second heavily doped region;
The bottom of the first conductive type source region is covered by the second conductive type first heavily doped region;
the second conductive type second heavily doped region corresponds to the second conductive type column doped region which is filled in the last epitaxy, and the width of the second conductive type second heavily doped region is not larger than the width of the second conductive type column doped region which is filled in the last epitaxy;
the first conductive type source region, the second conductive type first heavily doped region and the second conductive type second heavily doped region are in ohmic contact with the source metal.
And disposing gate conductive polysilicon over the first conductivity type base region, wherein,
the grid conductive polysilicon comprises a horizontal polysilicon body and vertical polysilicon bodies symmetrically distributed at two ends of the horizontal polysilicon body, and the vertical polysilicon bodies and the horizontal polysilicon bodies are connected into a whole;
the horizontal polysilicon body corresponds to the first conduction type base region positively, and is isolated from the first conduction type base region in an insulating way;
the vertical polysilicon body stretches into the second conductive type well region, is insulated and isolated from the second conductive type well region, the first conductive type source region and the second conductive type first heavily doped region, and the bottom of the vertical polysilicon body is positioned above the bottom of the first conductive type source region;
The vertical polysilicon body and the horizontal polysilicon body are insulated from the source metal.
A first conductivity type pillar heavily doped region is disposed within the first conductivity type pillar, wherein,
the first conductive type column heavy doping region extends from the top of the first conductive type column to the bottom of the first conductive type column vertically, and the width of the first conductive type column doping region is smaller than that of the first conductive type column;
the bottom of the heavily doped region of the first conductive type column is positioned above the bottom of the doped region of the last epitaxially filled second conductive type column.
And the second conductive type column doped region in the second conductive type column is columnar, and the second conductive type column doped region before the last filling is U-shaped.
The preparation method of the avalanche resistant power device capable of improving the super junction structure is used for preparing the power device, and comprises the following steps:
providing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a substrate of the first conductivity type and a drift base region of the first conductivity type positioned on the substrate;
carrying out groove etching on the first conductive type drift base region to form a second conductive type column groove after the groove etching, wherein the second conductive type column groove vertically extends to the substrate direction in the first conductive type drift base region;
Performing epitaxy of a second conductive type material in the second conductive type column groove to form a second conductive type column after the second conductive type column groove is filled by epitaxy, and forming first conductive type columns alternately distributed with the second conductive type column based on the first conductive type drift base region after the second conductive type column is formed, wherein the doping concentration of the second conductive type column doping region is sequentially increased according to the sequence of epitaxial filling in the second conductive type column groove;
performing first conductivity type material epitaxy on the first conductivity type drift base region to form a first conductivity type epitaxial base layer after epitaxy, and forming a first conductivity type drift region based on the first conductivity type epitaxial base layer and the first conductivity type drift base region;
and performing a positive cell process on the first conductive type drift region to prepare and form a positive cell unit and a terminal protection region, wherein the terminal protection region surrounds the positive cell unit.
The front side cell process comprises the following steps:
performing second conductivity type impurity ion implantation on the first conductivity type epitaxial base layer to form a second conductivity type well region and a first conductivity type base region for spacing the second conductivity type well region after the second conductivity type impurity ion implantation, wherein the first conductivity type base region is positioned on the first conductivity type column and is in contact with the N column, and the width of the first conductivity type base region is smaller than that of the N column;
The width of the second conductive type well region is larger than that of the second conductive type column, and the second conductive type well region is in contact with the corresponding first conductive type column and the second conductive type column;
and preparing a front structure of the front cell based on the first conductive type base region and the second conductive type well region.
The front side cell process further comprises:
performing second conductivity type impurity ion implantation above the second conductivity type well region to form a second conductivity type heavily doped base region in the second conductivity type well region, wherein the second conductivity type heavily doped base region comprises a second conductivity type first heavily doped base region and a second conductivity type second heavily doped base region, the second conductivity type first heavily doped base region is adjacent to a joint part of the second conductivity type column and the first conductivity type column, and the second conductivity type second heavily doped base region corresponds to a last filled second conductivity type column doped region;
and performing first-conductivity-type impurity ion implantation above the second-conductivity-type well region to form a first-conductivity-type source region in the second-conductivity-type well region, wherein the first-conductivity-type source region corresponds to the second-conductivity-type first-heavily-doped base region, so that after the first-conductivity-type source region is formed, a second-conductivity-type first-heavily-doped region is formed based on the second-conductivity-type first-heavily-doped base region, and the bottom of the first-conductivity-type source region is covered by the second-conductivity-type first-heavily-doped region.
The front side cell process further comprises:
carrying out groove etching on the first conductive type epitaxial base layer to form a polysilicon groove after the groove etching, wherein the polysilicon groove spans the first conductive type base region and the second conductive type well region, the bottom of the polysilicon groove is positioned above the bottom of the first conductive type source region, and the outer wall of the polysilicon groove positioned in the second conductive type well region is in contact with the first conductive type source region and the second conductive type first heavily doped region;
preparing a first oxidation isolation layer, wherein the first oxidation isolation layer covers the inner wall of the first conductive type base region and the inner wall of the polysilicon trench;
performing polysilicon deposition above the first conductive type base region to obtain gate conductive polysilicon, wherein the gate conductive polysilicon comprises a horizontal polysilicon body corresponding to the first conductive type base region and a vertical polysilicon body at least filled in the polysilicon trench, and the vertical polysilicon body is in contact with the horizontal polysilicon body;
preparing a second oxide isolation layer, wherein the second oxide isolation layer covers the outer surfaces of the horizontal polysilicon body and the vertical polysilicon body;
and preparing a source contact hole, and performing metal deposition after preparing the source contact hole so as to at least obtain source metal filled in the source contact hole, wherein the source metal is in ohmic contact with the first conductive type source region, the second conductive type first heavily doped region and the second conductive type second heavily doped region.
The invention has the advantages that: the second conductive type column is configured into a variable doping form, so that a peak electric field can be introduced through the second conductive type column, at the moment, a part of avalanche current can be split through the path so as to achieve the purpose of dispersing heat, namely, the avalanche current can be dispersed by utilizing the variable doping form of the second conductive type column, and the dispersion of heat can be realized due to the dispersion of the avalanche current, so that the avalanche tolerance of the super junction power device is improved.
In addition, since the gate conductive polysilicon includes a vertical polysilicon body, the threshold voltage of the power device when turned on can be substantially unaffected by the availability of the vertical polysilicon body, but a shorter current path and lower on-resistance is possessed by current through the forward parasitic NPN loop when an avalanche occurs.
Drawings
Fig. 1-9 are cross-sectional views of one embodiment of a specific process for manufacturing a power device according to the present invention, wherein,
figure 1 is a cross-sectional view of one embodiment of the present invention after forming an N-type drift base region on a substrate.
Fig. 2 is a cross-sectional view of an embodiment of the invention after etching to obtain P-pillar trenches.
Fig. 3 is a cross-sectional view of an embodiment of the present invention after a first epitaxial fill in the P-pillar trench.
Fig. 4 is a cross-sectional view of one embodiment of the present invention after three epitaxial fills have been performed in the P-pillar trench.
Fig. 5 is a cross-sectional view of one embodiment of the present invention after an N-type epitaxial substrate has been prepared.
Fig. 6 is a cross-sectional view of an embodiment of the p+ heavily doped base region of the present invention.
Fig. 7 is a cross-sectional view of an embodiment of the present invention after an n+ source region has been formed.
Fig. 8 is a cross-sectional view of an embodiment of the present invention after preparing a gate conductive polysilicon.
Fig. 9 is a cross-sectional view of the present invention after source metal is formed.
Reference numerals illustrate: the semiconductor device comprises a 1-substrate, a 2-N drift base region, a 3-first P column doped region, a 4-second P column doped region, a 5-third P column doped region, a 6-N column heavily doped region, a 7-N epitaxial base layer, an 8-P type well region, a 9-P+ first heavily doped base region, a 10-P+ second heavily doped base region, an 11-N+ source region, 12-grid conductive polycrystalline silicon, a 13-second oxidation isolation layer, 14-source metal, a 15-P column groove, a 16-N column, a 17-P+ first heavily doped region, a 18-first oxidation isolation layer, a 19-P+ second heavily doped region, a 20-N type base region, a 21-horizontal polycrystalline silicon body and a 22-vertical polycrystalline silicon part.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
In order to effectively increase avalanche energy of the superjunction device, for a power device capable of increasing avalanche resistance of the superjunction structure, taking a first conductivity type as an N type as an example, in one embodiment of the present invention, the power device includes an active region prepared in a central region of a semiconductor substrate and a terminal protection region located at an outer periphery of the active region, the terminal protection region surrounds the active region, wherein,
the active region comprises a positive cell unit and a superjunction unit, wherein the superjunction unit comprises a plurality of N columns 16 and P columns which are alternately distributed in turn;
for any P-pillar, the P-pillar doping regions sequentially epitaxially filled in the P-pillar trench 15 are included, wherein the doping concentration of the P-pillar doping regions sequentially increases in the order of the epitaxial filling in the P-pillar trench 15.
Specifically, the semiconductor substrate may be made of a conventional semiconductor material, such as silicon, and the material of the semiconductor substrate may be selected according to need. For a power device, the power device generally comprises an active area and a terminal protection area, wherein the active area is generally positioned in a central area of a semiconductor substrate, the terminal protection area surrounds the active area, the active area is used as a functional area of the power device, and the terminal protection area can be used for improving the voltage resistance of the active area.
For the super junction power device, a positive cell unit and a super junction unit are needed to be included in an active region of the super junction power device, the super junction structure of the super junction power device is formed by the super junction unit, and the positive cell of the super junction power device can be formed by the positive cell unit. When the first conductivity type is N-type, the second conductivity type is P-type, and at this time, for the superjunction unit, the superjunction unit generally includes a plurality of N pillars 16 and P pillars that are alternately distributed, and the arrangement direction of the N pillars 16 and P pillars is generally along the direction of the active region pointing to the terminal protection region, and the manner of sequentially alternately arranging the N pillars 16 and P pillars in the superjunction unit is consistent with the existing superjunction structure.
In order to improve avalanche resistance, in one embodiment of the present invention, P pillars in the superjunction unit are all configured to be in a variable doping form, and in order to form the variable doping form, when preparing the P pillars, it is necessary to prepare P pillar trenches 15 first, then perform epitaxy of P-type material in the P pillar trenches 15, and obtain P pillars after multiple epitaxy, where each epitaxy is filled to obtain P pillar doped regions, and at this time, the P pillars include a plurality of P pillar doped regions. In particular, the doping concentration of the P-pillar doped region obtained by each epitaxial filling is different, and preferably, the doping concentration of the P-pillar doped region is sequentially increased in the order of the epitaxial filling in the P-pillar trench 15.
Fig. 9 shows an embodiment of P-pillar fabrication by three epitaxial fills in the P-pillar trench 15, where the P-pillar includes a first P-pillar doped region 3, a second P-pillar doped region 4, and a third P-pillar doped region 5, and the first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 are sequentially epitaxially filled, thereby obtaining: the doping concentrations of the first P-pillar doping region 3, the second P-pillar doping region 4 and the third P-pillar doping region 5 are sequentially increased.
In the implementation, for the P column doped region in the P column, the P column doped region filled last time is columnar, and the P column doped region before filling last time is U-shaped. Namely, the first P-pillar doped region 3 and the second P-pillar doped region 4 are both U-shaped, and the third P-pillar doped region 5 is pillar-shaped. When the first P-pillar doped region 3 is formed by epitaxial filling, the first P-pillar doped region 3 covers the side wall and the bottom wall of the P-pillar trench 15, the second P-pillar doped region 4 covers the first P-pillar doped region 3, and the third P-pillar doped region 5 is surrounded by the second P-pillar doped region 4. Fig. 4 to 9 show only the P-pillar trench 15 and a partial form of the P-pillar, that is, only the first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 are shown in the P-pillar trench 15, and reference is made to the above description for specific cases.
On one hand, in the process of UIS, the parasitic NPN transistor near the P-type well region 8 of the MOS structure is conducted, so that the avalanche current is uncontrolled, and the device is possibly invalid. On the other hand, in the superjunction UIS process, the avalanche current is too concentrated, so that heat cannot be dissipated, and the failure of the device is affected.
Under the premise of two influencing factors, when the P column is configured into a variable doping form, a peak electric field can be introduced through the P column when avalanche occurs, and at the moment, a part of avalanche current can be split through the path so as to achieve the purpose of dispersing heat, namely, the avalanche current can be dispersed by utilizing the variable doping form of the P column, and the dispersion of heat can be realized due to the dispersion of the avalanche current, so that the avalanche tolerance of the super junction power device is improved.
In one embodiment of the present invention, the semiconductor substrate comprises an N-type substrate 1 and an N-type drift region on the substrate, wherein,
the N-type drift region is adjacent to the substrate 1;
the super junction unit is prepared in the N-type drift region, and the bottom of the N column 16 and the bottom of the P column are positioned at the joint of the N-type drift region and the substrate 1;
The positive cell unit comprises a plurality of positive cells distributed in parallel;
on the cross section of the power device, for any positive cell, the power device comprises an N-type base region 20 and P-type well regions 8 symmetrically distributed on two sides of the N-type base region 20, wherein the N-type base region 20 is positioned above an N column 16 and is in contact with the N column 16, and the width of the N-type base region 20 is smaller than that of the N column 16;
the width of the P-type well region 8 is larger than the width of the P-pillars, and the P-type well region 8 is in contact with the corresponding N-pillars 16 and P-pillars.
As is clear from the above description, when the conductivity type of the semiconductor substrate is N-type, the conductivity type of the substrate 1 of the semiconductor substrate is also N-type, the N-type drift region is located on the substrate 1, and the N-type drift region is adjacent to the substrate 1, and the doping concentration of the N-type drift region is generally smaller than that of the substrate 1. Typically, the superjunction cell is fabricated in an N-type drift region, with the bottom of the N-pillar 16 and the bottom of the P-pillar being located at the junction of the N-type drift region and the substrate 1. For the front cell unit in the active region, generally, the front cell unit includes a plurality of front cells distributed in parallel, in fig. 9, the front cell unit includes an N-type base region 20, and P-type well regions 8 are disposed at two sides of the N-type base region 20, where the P-type well regions 8 are in contact with the N-type base region 20, in fig. 9, only the N-type base region 20 and the P-type well regions 8 connected to one end of the N-type base region 20 are shown, and since the P-type well regions 8 at two sides are symmetrically distributed, the P-type well regions 8 are symmetrically distributed at two sides of the N-type base region 20, which can refer to the illustration in fig. 9.
In fig. 9, an N-type base region 20 corresponds to and contacts an N-pillar 16; the N-type base region 20 is located above the N pillar 16, where the above is the direction in which the substrate 1 points to the N-type drift region, and the below-described above all refer to the same direction. In addition, the width of the N-type base region 20 is smaller than the width of the N-pillar 16, and the width of the N-type base region 20 is the direction in which the N-type base region 20 points to the P-type well region 8. In fig. 9, the width of the P-type well region 8 is larger than the width of the P-pillar, and at this time, the junction between the P-type well region 8 and the N-type base region 20 falls within the N-pillar 16 when projected into the N-pillar 16; at the same time, the P-well 8 is in contact with the N-pillar 16 and the P-pillar. Based on the corresponding relation among the P-type well region 8, the N-type base region 20, the N column 16 and the P column, the front surface cell can be effectively prepared and formed, and the stability and reliability of the process are improved.
In one embodiment of the present invention, when the front-side cell is a planar cell, an n+ source region 11 and a p+ heavily doped region are disposed in the P-type well region 8, wherein,
the p+ heavily doped region includes a p+ first heavily doped region 17 and a p+ second heavily doped region 19;
the bottom of the N+ source region 11 is covered by the P+ first heavily doped region 17;
the P+ second heavily doped region 19 corresponds to the P column doped region filled in the last epitaxy, and the width of the P+ second heavily doped region 19 is not larger than the width of the P column doped region filled in the last epitaxy;
The n+ source region 11, the p+ first heavily doped region 17, and the p+ second heavily doped region 19 are all in ohmic contact with the source metal 14.
In fig. 9, an embodiment of an n+ source region 11, a p+ first heavily doped region 17 and a p+ second heavily doped region 19 are simultaneously disposed in a P-type well region 8, in which the n+ source region 11 extends from the surface of the P-type well region 8 vertically to the direction of the substrate 1, the junction depth of the n+ source region 11 is smaller than the thickness of the P-type well region 8, the p+ first heavily doped region 17 is located below the n+ source region 11, and the p+ first heavily doped region 17 wraps the bottom of the n+ source region 11. The P + first heavily doped region 17 is adjacent to the N-type base region 8 within the P-type well region 8.
The parasitic NPN transistor near the P-type well region 8 with the MOS structure specifically refers to an NPN transistor formed by an N-type base region 20, the P-type well region 8 and an N+ source region 11.
The bottom of the n+ source region 11 is covered by the p+ first heavily doped region 17, so that when electrons flow to the n+ source region 11, holes pass through the p+ first heavily doped region 17 with high concentration below, if there is no high concentration region based on the p+ first heavily doped region 17, the conduction voltage drop of the portion rises due to the rising of the resistivity, and the parasitic NPN transistor is turned on, that is, the p+ first heavily doped region 17 is matched with the n+ source region 11, so that the conduction of the parasitic NPN transistor can be effectively inhibited. The p+ second heavily doped region 19 mainly corresponds to a high concentration at the center of the P column, and when avalanche occurs, a spike electric field and a short current path are formed, thereby achieving the purpose of shunt.
The junction depths of the p+ second heavily doped region 19 and the p+ first heavily doped region 17 in the P-type well region 8 are the same, the p+ second heavily doped region 19 and the p+ first heavily doped region 17 can be generally prepared by the same process step, the p+ second heavily doped region 19 is spaced from the p+ first heavily doped region 17 by the P-type well region 8, the p+ second heavily doped region 19 corresponds to the P-pillar doped region which is epitaxially filled last time, as described above, the P-pillar doped region which is epitaxially filled last time is the third P-pillar doped region 5, at this time, the p+ second heavily doped region 19 corresponds to the third P-pillar doped region 5, but the width of the p+ second heavily doped region 19 is not greater than the width of the third P-pillar doped region 5.
In order to form the source electrode of the power device, a source metal 14 is required to be prepared above the N-type drift region, the source metal 14 is in ohmic contact with the n+ source region 11, the p+ first heavily doped region 17 and the p+ second heavily doped region 19, and the source metal 14 can be used to form the source electrode of the power device.
In one embodiment of the present invention, a gate conductive polysilicon 12 is disposed over the N-type base region 20, wherein,
the gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and vertical polysilicon bodies 22 symmetrically distributed at two ends of the horizontal polysilicon body 21, and the vertical polysilicon bodies 22 and the horizontal polysilicon body 21 are connected into a whole;
The horizontal polysilicon body 21 corresponds to the N-type base region 20 positively, and the horizontal polysilicon body 21 is insulated and isolated from the N-type base region 20;
the vertical polysilicon body 22 extends into the P-type well region 8, the vertical polysilicon body 22 is insulated and isolated from the P-type well region 8, the N+ source region 11 and the P+ first heavily doped region 17, and the bottom of the vertical polysilicon body 22 is positioned above the bottom of the N+ source region 11;
the vertical polysilicon body 22 and the horizontal polysilicon body 21 are insulated from the source metal 14.
An embodiment of the gate conductive polysilicon 12 is shown in fig. 8 and 9, in which the gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and a vertical polysilicon body 22, and the vertical polysilicon bodies 22 are symmetrically distributed at two ends of the horizontal polysilicon body 21 and are connected to each other to form a whole with the horizontal polysilicon body 21, and the horizontal polysilicon body 21 and the vertical polysilicon body 22 can be generally manufactured through the same process step, and specific process manufacturing procedures will be described in the following manufacturing processes.
The horizontal polysilicon body 21 corresponds to the N-type base region 20, the horizontal polysilicon body 21 is parallel to the N-type base region 20, and in fig. 8 and 9, the horizontal polysilicon body 21 is insulated from the N-type base region 20 by a first oxide isolation layer 18, which is typically a silicon dioxide layer, and the first oxide isolation layer 18 can be formed by a conventional gate oxide process.
In order to enable the vertical polysilicon body 22 to extend into the P-type well region 8, trench etching is generally performed at least in the P-type well region 8 to obtain a polysilicon trench, and when the horizontal polysilicon body 21 is prepared, polysilicon is simultaneously filled in the polysilicon trench, and at this time, the vertical polysilicon body 22 can be formed. Thus, the bottom of the vertical polysilicon body 22 is located below the horizontal polysilicon body 21, and the top of the vertical polysilicon body 21 is flush with the upper surface of the horizontal polysilicon body 21.
The first oxide isolation layer 18 also covers the inner wall of the polysilicon trench, the vertical polysilicon body 22 is isolated from the inner wall of the polysilicon trench by the first oxide isolation layer 18, at this time, the vertical polysilicon body 22 can be isolated from the P-type well region 8, the n+ source region 11 and the p+ first heavily doped region 17 by the first oxide isolation layer 18, and in fig. 8 and 9, the bottom of the vertical polysilicon body 22 is located above the bottom of the n+ source region 11, but the n+ source region 11 and the p+ first heavily doped region 17 are all in contact with the outer side wall of the corresponding adjacent polysilicon trench.
In fig. 8 and 9, after the vertical polysilicon body 22 is prepared, an oxidation process is further required to be performed again to prepare the second oxide isolation layer 13, where the second oxide isolation layer 13 may be a silicon dioxide layer, and the corresponding outer surfaces of the vertical polysilicon body 22 and the horizontal polysilicon body 21 may be covered by using the second oxide isolation layer 13.
In practice, since the gate conductive polysilicon 12 includes the vertical polysilicon body 22, the threshold voltage of the power device when turned on can be substantially unaffected by the vertical polysilicon body 12, but a shorter current path and lower on-resistance is provided when current flows through the forward parasitic NPN transistor loop when avalanche occurs.
In one embodiment of the present invention, N-pillar heavily doped region 6 is disposed within N-pillar 16, wherein,
the N-pillar heavily doped region 6 extends from the top of the N-pillar 16 vertically to the bottom of the N-pillar 16, and the width of the N-pillar doped region 6 is smaller than the width of the N-pillar 16;
the bottom of the N-pillar heavily doped region 6 is located above the bottom of the last epitaxially filled P-pillar doped region.
Fig. 5 to 9 show an embodiment of preparing the N-pillar heavily doped region 6 in the N pillar 16, when the N-pillar heavily doped region 6 is disposed in the N pillar 16, the N-pillar heavily doped region 6 can be used to balance charges between the P pillar and the N pillar 16, so as to reduce degradation of breakdown voltage of the superjunction structure, and can partially reduce resistance in forward conduction, so that the N-pillar heavily doped region has better compromise characteristics, that is, forward conduction characteristics and withstand voltage of the power device can be ensured.
For the super junction structure, the ideal situation is that the N column 16 and the P column have perfect charge balance, equal widths on two sides, opposite contained conductive types and equal charge quantity, and a complete depletion region is formed after contact so as to achieve a good voltage-withstanding effect, but because the P column doping concentration is improved, especially the center position of the P column is higher, the charge quantity of the P column is higher, therefore, after the N column heavy doping region 6 is arranged in the N column 16, the doping mode in the N column 16 can be improved in a corresponding region so as to realize charge balance with the P column forming the variable doping as far as possible.
The super junction power device can be prepared through the following process steps, in particular to a preparation method of an avalanche resistant power device capable of improving a super junction structure, wherein the preparation method comprises the following steps:
providing an N-type semiconductor substrate, wherein the semiconductor substrate comprises an N-type substrate 1 and an N-type drift base region 2 positioned on the substrate 1;
carrying out groove etching on the N-type drift base region 2 to form a P column groove 15 after the groove etching, wherein the P column groove 15 vertically extends to the direction of the substrate 1 in the N-type drift base region 2;
performing epitaxy of the P-type material in the P-pillar trench 15 to form P-pillars after the P-pillar trench 15 is filled with epitaxy, and forming N-pillars 16 alternately distributed with the P-pillars based on the N-type drift base region 2 after the P-pillars are formed, wherein the doping concentration of the P-pillar doping regions sequentially increases according to the sequence of the epitaxial filling in the P-pillar trench 15;
performing N-type material epitaxy on the N-type drift base region 2 to form an N-type epitaxial base layer 7 after epitaxy, and forming an N-type drift region based on the N-type epitaxial base layer 7 and the N-type drift base region 2;
and carrying out a positive cell process on the N-type drift region to prepare and form a positive cell unit and a terminal protection region, wherein the terminal protection region surrounds the positive cell unit.
In one embodiment of the semiconductor substrate shown in fig. 1, the N-type drift base region 2 may be epitaxially formed on the substrate 1, where the doping concentration of the N-type drift base region 2 is generally less than the doping concentration of the substrate 1.
In order to prepare the P-pillar of the superjunction unit, trench etching is performed on the N-type drift base region 2 to obtain a P-pillar trench 15 after etching, and in fig. 2, the depth of the P-pillar trench 15 is consistent with the thickness of the N-type drift base region 2, that is, the bottom of the P-pillar trench 15 is the substrate 1. The width and distribution of the P-pillar trench 15 can be selected as desired to produce the desired N-pillar 16 and P-pillar.
After the P-pillar trench 15 is etched, the P-type material is epitaxially grown, and fig. 3 shows the case after the first epitaxial filling, at this time, the first P-pillar doped region 3 may be prepared, where the first P-pillar doped region 3 covers the inner wall of the P-pillar trench 15. In fig. 4, after the second epitaxial filling and the third epitaxial filling, the second P-pillar doped region 4 and the third P-pillar doped region 5 may be sequentially prepared, and as can be seen from the above description, the doping concentrations of the first P-pillar doped region 3, the second P-pillar doped region 4 and the third P-pillar doped region 5 sequentially increase. Of course, in the specific implementation, the number of times of extending the filling can be selected according to the requirement, so as to meet the requirement that the doping concentration is sequentially increased and the P column is prepared, and the description is not repeated here. After forming the P-pillars, the N-type drift base region 2 may be used to form N-pillars 16, as shown in fig. 4.
In particular, when the N-pillar heavily doped region 6 needs to be prepared, after the P-pillar is prepared, N-type impurity ion implantation is performed, so that the N-pillar heavily doped region 6 is formed after implantation, as shown in fig. 4. After the heavily doped region 6 of the N column is prepared, polishing and flattening the surface of the N type drift base region 2, and then performing rapid thermal annealing and junction pushing to ensure that PN junction interfaces are well contacted and repair lattice surface damage, wherein the rapid annealing temperature can be 850-1150 ℃ generally, and the rapid annealing temperature and the rapid annealing process can be selected according to actual processes.
After the above process, N-type material epitaxy is performed on the N-type drift base region 2 to form an N-type epitaxial base layer 7 after epitaxy, and the N-type epitaxial base layer 7 covers the N-type drift region 2, at this time, the N-type epitaxial base layer 7 contacts with the top ends of the N pillars 16 and the P pillars, as shown in fig. 5. The N-type epitaxial base layer 7 and the N-type drift base region 2 may together form an N-type drift region. After the N-type drift region is formed, a positive cell process can be performed to prepare a positive cell unit.
In one embodiment of the present invention, the front side cell process includes:
p-type impurity ion implantation is performed on the N-type epitaxial base layer 7, so that a P-type well region 8 and an N-type base region 20 for spacing the P-type well region 8 are formed after the P-type impurity ion implantation is performed, the N-type base region 20 is positioned on an N column 16 and is in contact with the N column 16, and the width of the N-type base region 20 is smaller than that of the N column 16;
The width of the P-type well region 8 is larger than that of the P column, and the P-type well region 8 is in contact with the corresponding N column 16 and the P column;
based on the N-type base region 20 and the P-type well region 8 described above, the front structure of the front cell is prepared.
Specifically, after the N-type epitaxial base layer 7 is obtained, P-type impurity ions may be implanted by using a technical means commonly used in the art to form the P-type well region 8, and the N-type base region 8, the N-type base region 20, and the P-type well region 8 may be formed by using the N-type epitaxial base layer 7, as described above with reference to fig. 6. In general, the depth of the P-type well region 8 corresponds to the thickness of the N-type epitaxial base layer 7.
Further, the front side cell process further includes:
performing P-type impurity ion implantation above the P-type well region 8 to form a p+ heavily doped base region in the P-type well region 8, wherein the p+ heavily doped base region comprises a p+ first heavily doped base region 9 and a p+ second heavily doped base region 10, the p+ first heavily doped base region 9 is adjacent to the junction of the P column and the N column 16, and the p+ second heavily doped base region 10 corresponds to the P column doped region filled last time;
n-type impurity ion implantation is performed above the P-type well region 8 to form an n+ source region 11 in the P-type well region 8, where the n+ source region 11 corresponds to the p+ first heavily doped base region 9, so that after the n+ source region 11 is formed, a p+ first heavily doped region 17 is formed based on the p+ first heavily doped base region 9, and the p+ first heavily doped region 17 encapsulates the bottom of the n+ source region 11.
After the P-type well region 8 is obtained, a second P-type impurity ion implantation may be performed on the P-type well region 8, and at this time, a p+ heavily doped base region may be obtained, and fig. 6 shows an embodiment in which the p+ heavily doped base region includes a p+ first heavily doped base region 9 and a p+ second heavily doped base region 10, where the p+ first heavily doped base region 9 and the p+ second heavily doped base region 10 have the same junction depth.
Thereafter, N-type impurity ion implantation is performed above the P-type well region 8 to obtain an n+ source region 11, specifically, the region in which the n+ source region 11 is implanted is the p+ first heavily doped base region 9, at this time, after the n+ source region 11 is obtained, the p+ first heavily doped base region 9 may be utilized to form a p+ first heavily doped region 17, where the p+ first heavily doped region 17 is located below the n+ source region 11 and wraps the bottom of the n+ source region 11, as shown in fig. 7, so that the p+ first heavily doped region 17 is formed by the p+ first heavily doped base region 9 that does not form the n+ source region 11.
In one embodiment of the present invention, the front side cellular process further includes:
carrying out groove etching on the N-type epitaxial base layer 7 to form a polysilicon groove after the groove etching, wherein the polysilicon groove spans the N-type base region 20 and the P-type well region 8, the bottom of the polysilicon groove is positioned above the bottom of the N+ source region 11, and the outer wall of the polysilicon groove positioned in the P-type well region 8 is in contact with the N+ source region 11 and the P+ first heavily doped region 17;
Preparing a first oxidation isolation layer 18, wherein the first oxidation isolation layer 18 covers the N-type base region 20 and the inner wall of the polysilicon trench;
performing polysilicon deposition above the N-type base region 20 to obtain gate conductive polysilicon 12, wherein the gate conductive polysilicon 12 comprises a horizontal polysilicon body 21 corresponding to the N-type base region 20 and a vertical polysilicon body 22 at least filled in the polysilicon trench, and the vertical polysilicon body 22 is in contact with the horizontal polysilicon body 21;
preparing a second isolation oxide layer 13, wherein the second isolation oxide layer 13 covers the outer surfaces of the horizontal polysilicon body 21 and the vertical polysilicon body 22;
and preparing a source contact hole, and performing metal deposition after preparing the source contact hole so as to at least obtain a source metal 14 filled in the source contact hole, wherein the source metal 14 is in ohmic contact with the N+ source region 11, the P+ first heavily doped region 17 and the P+ second heavily doped region 19.
In order to prepare the gate conductive polysilicon 12, a trench etching is performed on the N-type epitaxial substrate 7 to form a polysilicon trench. For the formed polysilicon trench, one part of the polysilicon trench is located in the N-type base region 20, the other part of the polysilicon trench is located in the P-type well region 8 adjacent to the N-type base region 20, and the part of the polysilicon trench located in the P-type well region 8 is far larger than the part in the N-type base region 20. The notch of the polysilicon trench is located on the surfaces of the N-type base region 20 and the P-type well region 8, and the bottom of the polysilicon trench needs to be located above the bottom of the n+ source region 11. The polysilicon trench is located on the outer wall of the P-type well region 8 and is in contact with the n+ source region 11 and the p+ first heavily doped region 17, and at this time, the polysilicon trench is not in contact with the p+ second heavily doped base region 10.
After the polysilicon trench is etched, the first oxide isolation layer 18 is prepared by a process commonly used in the art, where the first oxide isolation layer 18 at least covers the N-type base region 20 and the inner wall of the polysilicon trench, and the situation of the first oxide isolation layer 18 can be referred to as the above description.
After the first oxide isolation layer 18 is prepared, polysilicon deposition is performed to prepare the gate conductive polysilicon 12, where it is known from the foregoing description that the gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and a vertical polysilicon body 22, the horizontal polysilicon body 21 corresponds to the N-type base region 20, the vertical polysilicon body 22 is filled in the polysilicon trench, and the vertical polysilicon body 22 is insulated from the n+ source region 11, the p+ first heavily doped base region 17, the P-type well region 8, and the N-type base region 20 by the first oxide isolation layer 18.
After the gate conductive polysilicon 12 is prepared, the second oxide isolation layer 13 is prepared, and after the second oxide isolation layer 13 is utilized, the first oxide isolation layer 18 and the second oxide isolation layer 13 can be utilized to realize the coating of the gate conductive polysilicon 12, as shown in fig. 8.
After the second oxide isolation layer 13 is prepared, an insulating dielectric layer is deposited, the insulating dielectric layer covers the N-type drift region, and then contact hole etching is performed to prepare a source contact hole. The source contact hole generally corresponds to the P-type well region 8, extends from the surface of the P-type well region 8 toward the P column direction, etches away part of the n+ source region 11, the p+ first heavily doped region 17 and the p+ second heavily doped base region 19, and forms the p+ second heavily doped region 19 by using the remaining part of the p+ second heavily doped base region 19.
After the source contact hole is formed, metal deposition may be performed by a conventional method in the art, where the source metal 14 may be formed, and the source metal 14 may cover the insulating dielectric layer and may be filled in the source contact hole, and ohmic contact between the source metal 14 and the n+ source region 11, the p+ first heavily doped region 17, and the p+ second heavily doped region 19 may be achieved by using the source metal 14 filled in the source contact hole, as shown in fig. 9.
In addition, when metal is deposited, gate metal can be prepared, the gate metal is in ohmic contact with the gate conductive polysilicon 12, so that a gate electrode or a gate of the power device is formed by ohmic contact between the gate metal and the gate conductive polysilicon 12, and when the gate electrode of the power device is formed, the power device is generally a MOSFET type device; when forming the gate of the power device, the power device is typically an IGBT device.
The above provides an embodiment of the method for preparing the active area, and the front-side cell unit and the super-junction unit in the active area can also be prepared by adopting other processes. Of course, the specific conditions of the terminal protection area and the back structure can be selected and determined according to actual needs. In the above process steps, the specific steps that are not limited may be adopted in the process conditions and procedures commonly used in the art, and the implementation of the specific steps is based on that the specific preparation process can be satisfied, which is not described herein.
Claims (10)
1. The power device capable of improving avalanche resistance of super junction structure is characterized by comprising an active region prepared in a central region of a semiconductor substrate and a terminal protection region positioned on the outer ring of the active region, wherein the terminal protection region surrounds the active region in a surrounding way,
the active region comprises a front cell unit and a superjunction unit, wherein the superjunction unit comprises a plurality of first conductive type columns and second conductive type columns which are alternately distributed in turn, and the conductive type of the first conductive type columns is consistent with that of the semiconductor substrate;
and for any second conductive type column, the second conductive type column comprises a plurality of second conductive type column doped regions which are sequentially epitaxially filled in the second conductive type column grooves, wherein the doping concentration of the second conductive type column doped regions is sequentially increased according to the sequence of epitaxial filling in the second conductive type column grooves.
2. The power device capable of improving avalanche resistance of super junction structure according to claim 1, wherein: the semiconductor substrate includes a substrate of a first conductivity type and a drift region of the first conductivity type on the substrate, wherein,
the first conductivity type drift region is adjacent to the substrate;
The super junction unit is prepared in the first conductive type drift region, and the bottoms of the first conductive type columns and the bottoms of the second conductive type columns are positioned at the joint of the first conductive type drift region and the substrate;
the positive cell unit comprises a plurality of positive cells distributed in parallel;
on the section of the power device, for any positive cell, the power device comprises a first conductive type base region and second conductive type well regions symmetrically distributed on two sides of the first conductive type base region, wherein the first conductive type base region is positioned above a first conductive type column and is in contact with the first conductive type column, and the width of the first conductive type base region is smaller than that of the first conductive type column;
the width of the second conductive-type well region is larger than the width of the second conductive-type column, and the second conductive-type well region is in contact with the corresponding first conductive-type column and the second conductive-type column.
3. The power device of claim 2, wherein when the front side cell is a planar cell, a first conductivity type source region and a second conductivity type heavily doped region are disposed in the second conductivity type well region, wherein,
the second conductive type heavily doped region comprises a second conductive type first heavily doped region and a second conductive type second heavily doped region;
The bottom of the first conductive type source region is covered by the second conductive type first heavily doped region;
the second conductive type second heavily doped region corresponds to the second conductive type column doped region which is filled in the last epitaxy, and the width of the second conductive type second heavily doped region is not larger than the width of the second conductive type column doped region which is filled in the last epitaxy;
the first conductive type source region, the second conductive type first heavily doped region and the second conductive type second heavily doped region are in ohmic contact with the source metal.
4. The power device for improving avalanche resistance of a superjunction structure according to claim 3, wherein a gate conductive polysilicon is disposed over said first conductivity type base region, wherein,
the grid conductive polysilicon comprises a horizontal polysilicon body and vertical polysilicon bodies symmetrically distributed at two ends of the horizontal polysilicon body, and the vertical polysilicon bodies and the horizontal polysilicon bodies are connected into a whole;
the horizontal polysilicon body corresponds to the first conduction type base region positively, and is isolated from the first conduction type base region in an insulating way;
the vertical polysilicon body stretches into the second conductive type well region, is insulated and isolated from the second conductive type well region, the first conductive type source region and the second conductive type first heavily doped region, and the bottom of the vertical polysilicon body is positioned above the bottom of the first conductive type source region;
The vertical polysilicon body and the horizontal polysilicon body are insulated from the source metal.
5. The power device of any one of claims 1 to 4, wherein a first conductivity type pillar heavily doped region is provided within the first conductivity type pillar, wherein,
the first conductive type column heavy doping region extends from the top of the first conductive type column to the bottom of the first conductive type column vertically, and the width of the first conductive type column doping region is smaller than that of the first conductive type column;
the bottom of the heavily doped region of the first conductive type column is positioned above the bottom of the doped region of the last epitaxially filled second conductive type column.
6. The power device capable of improving avalanche tolerance of super junction structure according to any one of claims 1 to 4, wherein: and the second conductive type column doped region in the second conductive type column is columnar, and the second conductive type column doped region before the last filling is U-shaped.
7. A method for manufacturing an avalanche resistive power device capable of improving a superjunction structure, which is characterized by being used for manufacturing the power device according to any one of claims 1 to 6, wherein the manufacturing method comprises the following steps:
Providing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a substrate of the first conductivity type and a drift base region of the first conductivity type positioned on the substrate;
carrying out groove etching on the first conductive type drift base region to form a second conductive type column groove after the groove etching, wherein the second conductive type column groove vertically extends to the substrate direction in the first conductive type drift base region;
performing epitaxy of a second conductive type material in the second conductive type column groove to form a second conductive type column after the second conductive type column groove is filled by epitaxy, and forming first conductive type columns alternately distributed with the second conductive type column based on the first conductive type drift base region after the second conductive type column is formed, wherein the doping concentration of the second conductive type column doping region is sequentially increased according to the sequence of epitaxial filling in the second conductive type column groove;
performing first conductivity type material epitaxy on the first conductivity type drift base region to form a first conductivity type epitaxial base layer after epitaxy, and forming a first conductivity type drift region based on the first conductivity type epitaxial base layer and the first conductivity type drift base region;
And performing a positive cell process on the first conductive type drift region to prepare and form a positive cell unit and a terminal protection region, wherein the terminal protection region surrounds the positive cell unit.
8. The method for manufacturing the avalanche resistive power device capable of improving the super junction structure according to claim 7, wherein the front side cell process comprises:
performing second conductivity type impurity ion implantation on the first conductivity type epitaxial base layer to form a second conductivity type well region and a first conductivity type base region for spacing the second conductivity type well region after the second conductivity type impurity ion implantation, wherein the first conductivity type base region is positioned on the first conductivity type column and is in contact with the N column, and the width of the first conductivity type base region is smaller than that of the N column;
the width of the second conductive type well region is larger than that of the second conductive type column, and the second conductive type well region is in contact with the corresponding first conductive type column and the second conductive type column;
and preparing a front structure of the front cell based on the first conductive type base region and the second conductive type well region.
9. The method for manufacturing an avalanche resistive power device capable of improving a superjunction structure according to claim 8, wherein the front side cell process further comprises:
Performing second conductivity type impurity ion implantation above the second conductivity type well region to form a second conductivity type heavily doped base region in the second conductivity type well region, wherein the second conductivity type heavily doped base region comprises a second conductivity type first heavily doped base region and a second conductivity type second heavily doped base region, the second conductivity type first heavily doped base region is adjacent to a joint part of the second conductivity type column and the first conductivity type column, and the second conductivity type second heavily doped base region corresponds to a last filled second conductivity type column doped region;
and performing first-conductivity-type impurity ion implantation above the second-conductivity-type well region to form a first-conductivity-type source region in the second-conductivity-type well region, wherein the first-conductivity-type source region corresponds to the second-conductivity-type first-heavily-doped base region, so that after the first-conductivity-type source region is formed, a second-conductivity-type first-heavily-doped region is formed based on the second-conductivity-type first-heavily-doped base region, and the bottom of the first-conductivity-type source region is covered by the second-conductivity-type first-heavily-doped region.
10. The method for manufacturing an avalanche resistive power device capable of improving a superjunction structure according to claim 9, wherein the front side cell process further comprises:
Carrying out groove etching on the first conductive type epitaxial base layer to form a polysilicon groove after the groove etching, wherein the polysilicon groove spans the first conductive type base region and the second conductive type well region, the bottom of the polysilicon groove is positioned above the bottom of the first conductive type source region, and the outer wall of the polysilicon groove positioned in the second conductive type well region is in contact with the first conductive type source region and the second conductive type first heavily doped region;
preparing a first oxidation isolation layer, wherein the first oxidation isolation layer covers the inner wall of the first conductive type base region and the inner wall of the polysilicon trench;
performing polysilicon deposition above the first conductive type base region to obtain gate conductive polysilicon, wherein the gate conductive polysilicon comprises a horizontal polysilicon body corresponding to the first conductive type base region and a vertical polysilicon body at least filled in the polysilicon trench, and the vertical polysilicon body is in contact with the horizontal polysilicon body;
preparing a second oxide isolation layer, wherein the second oxide isolation layer covers the outer surfaces of the horizontal polysilicon body and the vertical polysilicon body;
and preparing a source contact hole, and performing metal deposition after preparing the source contact hole so as to at least obtain source metal filled in the source contact hole, wherein the source metal is in ohmic contact with the first conductive type source region, the second conductive type first heavily doped region and the second conductive type second heavily doped region.
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