CN117378289A

CN117378289A - Circuit board, light-emitting substrate, backlight module, display panel and display device

Info

Publication number: CN117378289A
Application number: CN202280000839.8A
Authority: CN
Inventors: 姚念琦; 田忠朋; 宁策; 李正亮; 胡合合; 黄杰; 贺家煜; 李菲菲; 赵坤; 陈一民
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-04-21
Filing date: 2022-04-21
Publication date: 2024-01-09
Also published as: WO2023201618A1

Abstract

A wiring board (10) includes: a substrate (1) and a stress neutral layer (2) provided on one side of the substrate (1), wherein the stress neutral layer (2) comprises: at least one first metal layer (21) and at least one second metal layer (22), the at least one second metal layer (22) and the at least one first metal layer (21) are stacked, the material of the at least one first metal layer (21) in the at least one first metal layer (21) is a material generating tensile stress, and the material of the at least one second metal layer (22) in the at least one second metal layer (22) is a material generating compressive stress.

Description

Circuit board, light-emitting substrate, backlight module, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a circuit board, a light-emitting substrate, a backlight module, a display panel and a display device.

Background

The submillimeter Light-Emitting Diode (Mini-LED) refers to an LED device with a chip size of 50 μm to 200 μm, and the chip size and the chip pitch of the Mini-LED are smaller than those of the conventional LED and larger than those of the Micro LED, so that the submillimeter Light-Emitting Diode is widely used in backlight and display screens.

Disclosure of Invention

In one aspect, there is provided a wiring board comprising: a substrate and a stress neutral layer arranged on one side of the substrate. Wherein the stress neutral layer comprises: the device comprises at least one first metal layer and at least one second metal layer, wherein the at least one second metal layer is arranged in a lamination mode with the at least one first metal layer, the material of the at least one first metal layer is a material generating tensile stress, and the material of the at least one second metal layer is a material generating compressive stress.

In some embodiments, the at least one first metal layer is a multilayer, the at least one second metal layer is located between two first metal layers, and the at least one first metal layer is located between two second metal layers.

In some embodiments, the sum of the thicknesses of all of the at least one first metal layer is 70% to 99% of the thickness of the stress neutral layer.

In some embodiments, the stress neutral layer has a warp of 1mm or less.

In some embodiments, the material of the second metal layer comprises any one of W, WNi, WCu, WMo, WCr and WAl.

In some embodiments, the second metal layer has a resistance in the range of 1×10 ^-8 Ω·m～1×10 ^-5 Ω·m。

In some embodiments, the material of the first metal layer comprises copper.

In some embodiments, at least one of the at least one first metal layer further comprises at least one buffer layer.

In some embodiments, the material of the buffer layer includes any one of MoNb, moNiTi, ti, mo and MoTi.

In some embodiments, the buffer layer has a thickness in the range of 0 to 1000 angstroms.

In some embodiments, each first metal layer has a thickness ranging from 1 μm to 3 μm and each second metal layer has a thickness ranging from 300 angstroms to 5000 angstroms.

In some embodiments, where the at least one first metal layer is closest to the substrate, the at least one first metal layer comprises a copper layer and at least one buffer layer, and one of the at least one buffer layer is closer to the substrate than the copper layer.

In some embodiments, the substrate is a glass substrate.

In some embodiments, the stress neutral layer comprises a plurality of patterns formed by etching, each pattern of the plurality of patterns comprising a sub-pattern formed by the respective stack; in the case where the stress neutral layer includes a plurality of first metal layers and at least one second metal layer, the slope angle of the sub-pattern formed by the stack relatively far from the substrate is smaller than the slope angle of the sub-pattern formed by the stack relatively close to the substrate in the pattern, wherein the stack is any one of the first metal layer, the second metal layer, or a combined film layer of adjacent first metal layer and second metal layer.

In some embodiments, the slope angle of any one of the sub-patterns in the pattern is in the range of 20 ° to 70 °.

In another aspect, a light emitting substrate is provided, including a circuit board as described above, wherein the stress neutral layer is used to form traces and/or electrode pads.

In some embodiments, the light emitting substrate further comprises: the LED comprises a plurality of LEDs, wherein each LED comprises a first pin and a second pin, each electrode pad comprises a first electrode pad and a second electrode pad, each wire comprises a first wire and a second wire, the first wires are connected with the first pins of the LEDs through the first electrode pads, and the second wires are connected with the second pins of the LEDs through the second electrode pads.

In some embodiments, the electrode pad material may also be one of WNi and WCu.

In some embodiments, the light emitting diode is a sub-millimeter light emitting diode or a micro light emitting diode.

In yet another aspect, a backlight module is provided, the backlight module including the light-emitting substrate as described above.

In yet another aspect, a display device is provided, including a backlight module as described above, and further including a liquid crystal display panel connected to the backlight module.

In yet another aspect, a display panel is provided, comprising a light emitting substrate as described above.

In yet another aspect, a display device is provided, comprising a display panel as described above.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a circuit board provided according to some embodiments;

FIG. 2 is a graph of stress (warpage) versus thickness for copper layers provided in accordance with some embodiments of the present disclosure;

FIG. 3 is a graph of variation in coating power and warpage of a magnetron sputtering process provided in accordance with some embodiments of the present disclosure;

fig. 4 is a block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

Fig. 5 is another block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

fig. 6 is a further block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

FIG. 7 is a stress structure diagram of a second metal layer provided in accordance with some embodiments;

FIG. 8 is a graph of stress (warpage) of a second metal layer as a function of thickness provided in accordance with some embodiments of the present disclosure;

fig. 9 is a further block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

fig. 10a is a further block diagram of a wiring board provided in accordance with some embodiments of the present disclosure;

FIG. 10b is a scanning electron microscope view of a wiring board provided in accordance with some embodiments of the present disclosure;

fig. 11 is a further block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

fig. 12 is a further block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

fig. 13 is a further block diagram of a circuit board provided in accordance with some embodiments of the present disclosure;

FIG. 14 is an SEM image of a plurality of patterns etched in a stress neutral layer provided in accordance with some embodiments of the present disclosure;

fig. 15 is a block diagram of a light emitting substrate provided in accordance with some embodiments of the present disclosure;

Fig. 16 is a block diagram of a backlight module according to some embodiments of the present disclosure;

FIG. 17 is a block diagram of a display device provided in accordance with some embodiments of the present disclosure;

FIG. 18 is a block diagram of a display panel provided in accordance with some embodiments of the present disclosure;

fig. 19 is another block diagram of a display device provided according to some embodiments of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5 °; "vertical" includes absolute vertical and near vertical, where the acceptable deviation range for near vertical may also be deviations within 5 °, for example. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

For electronic components to which electrical signals are transmitted by wires, it is desirable to reduce voltage drop losses due to the wires as much as possible. According to the calculation formula of the resistance, the resistance of the conductive material, the length of the extending direction of the wire and the size of the cross section perpendicular to the extending direction are related, wherein the cross section is composed of a line width and a line height (i.e. thickness). Since the wiring space on the display panel is determined and the electrical reliability requirement needs to be met between two adjacent wires, the line spacing between any two adjacent wires has a minimum value, so that the line width of the wires has a design limit; in order to reduce the resistance of the wire as much as possible, the wire height of the wire may be increased as much as possible. On the other hand, a conductive material with a low resistivity should be selected, and copper is currently the best choice in view of cost. That is, one solution to achieve low resistance wires is to make copper wires of greater thickness, i.e., thick copper.

In the related art, the metal layer may be manufactured through an electroplating process or a magnetron sputtering process.

The electroplating process has the problems of high cost, large pollution, poor film quality and the like. The specific problems are as follows: (1) Firstly, forming a seed layer on a substrate in a sputtering chamber, then entering electroplating equipment to deposit coated metal, and respectively placing the substrate in different process chambers, thereby increasing the overall process time; (2) The electroplating process involves chemical reaction, hazardous waste exists, and the pollution to the environment is large; (3) The formed coating film has poor compactness and poor surface flatness, and the electroplating is carried out through electrochemical reaction liquid phase film formation, so that more byproducts are produced, and the substrate is easy to oxidize after being taken out of the electroplating equipment, so that the surface of the coating layer is dirty.

As shown in fig. 1 and 2, the metal layer 20 formed by the magnetron sputtering process has the advantages of good uniformity, high compactness and the like, however, because the plasma energy is high and the deposition speed is high in the sputtering process, for the substrate 11 prepared by the temperature sensitive material (such as glass), the substrate 11 is quickly heated, the thermal expansion coefficient of the metal plasma and the material of the substrate 11 is different, larger thermal stress is generated, the thermal stress has a positive correlation with the thickness, when the metal stress of the plating layer is larger, the substrate 11 is easy to warp, even crack and the like, so that a plurality of risks exist at present when the metal layer 20 with larger thickness (such as more than 2 μm) is manufactured on the substrate 11 by the sputtering process. Warpage refers to a case where a material is not shaped according to a designed shape, so that the material forms a distorted shape.

As shown in fig. 3, the metal stress of the plating layer can be reduced (for example, the warpage is prevented from being larger than 2 mm) by reducing the power of the plating film, but this reduces the film forming efficiency, thereby affecting the production efficiency.

Mini-LEDs (Mini Light Emitting Diode, mini light emitting diodes) are also known as sub-millimeter light emitting diodes, which are LEDs with a die size of about 80 μm to 500 μm, with a Mini-LED die size and dot spacing between conventional small pitch LEDs and Micro LEDs.

For the application of Mini-LEDs in backlight, the backlight comprises a plurality of Mini-LEDs arranged in an array, at least one of the Mini-LEDs is used as a partition, and the Mini-LEDs are matched with an LCD (Liquid Crystal Display ), so that the area dimming in a smaller range is realized. Compared with the traditional backlight design, the backlight module can realize better brightness uniformity and higher color contrast in a smaller light mixing distance, and further realize the ultrathin, high color rendering and power-saving performance of the terminal product. Meanwhile, the design of the display device can be matched with a flexible substrate, and can be matched with the curved surface of an LCD (Liquid Crystal Display ), so that the curved surface display similar to an OLED can be realized under the condition of ensuring the image quality.

For the application of Mini-LEDs On a display screen, RGB Mini-LEDs overcome the defects of wire bonding and reliability of a normal Chip, and meanwhile, the advantages of COB (Chip On Board) packaging are combined, and the IC is fixed On a printed circuit Board) are combined, so that the point distance of the display screen is further reduced. The visual effect of the corresponding terminal product is greatly improved, and meanwhile, the viewing distance can be greatly reduced. On the other hand, the RGB Mini-LED is matched with the flexible substrate, so that the high-image-quality display effect of a curved surface can be realized, and the self-luminous characteristic of the RGB Mini-LED is further realized, so that the RGB Mini-LED has a wider application field, such as automobile display.

For the high-resolution product using Mini-LEDs, the Mini-LEDs are current type components which need to show stable photoelectric characteristics under a large current, and wires prepared by using a metal layer 20 with the thickness of 2 μm are still difficult to meet the requirements.

Based on the above, the present disclosure provides a wiring board 10, as shown in fig. 4, 5 and 6, the wiring board 10 includes a substrate 1 and a stress neutral layer 2 provided on one side of the substrate 1. Wherein the stress neutral layer 2 comprises: at least one first metal layer 21 and at least one second metal layer 22, at least one second metal layer 22 and at least one first metal layer 21 are stacked, and the material of at least one first metal layer 21 is a material generating tensile stress, and the material of at least one second metal layer 22 is a material generating compressive stress.

The substrate 1 includes, for example, any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, and the like; or a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, or the like, an SOI (Silicon On Insulator; silicon on insulator) substrate, or the like. The substrate may also include an organic resin material such as epoxy, triazine, silicone, or polyimide. In some example embodiments, the substrate may be an FR4 type Printed Circuit Board (PCB), or may be a flexible PCB that is easily deformed. In some example embodiments, the substrate may include, for example, silicon nitride, alN, or Al ₂ O ₃ Or a metal or metal compound, or any of a Metal Core Printed Circuit Board (MCPCB) or a copper clad laminate (MCCL).

The material of the first metal layer 21 is a material that generates tensile stress, and the warpage generated after the material of the first metal layer 21 forms a film layer is positive. The material of the second metal layer 22 is a material generating compressive stress, which means that after the material of the second metal layer 22 forms a film layer, the warpage generated by the film layer is negative. The fact that the warpage of the first metal layer 21 is positive and the warpage of the second metal layer 22 is negative means that the first metal layer 21 and the second metal layer 22 have forces that generate warpage in opposite directions.

Illustratively, referring again to fig. 1 and 2, the material of the first metal layer 21, such as copper, may cause upward warpage. As shown in fig. 7 and 8, after the second metal layer 22 is formed, downward warpage occurs, and thus the structure shown in fig. 2 and the structure shown in fig. 7 generate forces to warp in opposite directions.

Illustratively, the at least one first metal layer 21 and the at least one second metal layer 22 form a stress neutral layer 2, and referring again to fig. 4 and 5, the at least one first metal layer 21 is one layer and the at least one second metal layer 22 is one layer, the stress neutral layer 2 means that the compressive stress generated by the second metal layer 22 effectively counteracts the tensile stress generated by the first metal layer 21.

For example, the thickness of the first metal layer 21 is 3 μm, the warp generated by the first metal layer 21 is 1.3mm, and the thickness of the second metal layer 22 is 2000 angstromsThe warpage generated by the second metal layer 22 is-0.65 mm, and then the theoretical value of the warpage of the stress neutral layer 2 formed by stacking the first metal layer 21 and the second metal layer 22 is the sum of the warpage of the first metal layer 21 and the warpage of the second metal layer 22, namely, 1.3mm-0.65 mm=0.65 mm. The actual measured warpage of the substrate 1, the first metal layer 21, and the second metal layer 22, which were laminated in this order, was 0.63mm, and the actual measured warpage of the substrate 1, the second metal layer 22, and the first metal layer 21, which were laminated in this order, was 0.6mm. The actual measured value and the theoretical calculated value are slightly different.

As shown in fig. 4, the substrate 1, the first metal layer 21, and the second metal layer 22 are stacked in this order. As shown in fig. 5, the substrate 1, the second metal layer 22, and the first metal layer 21 are stacked in this order, and the order of stacking the second metal layer 22 and the first metal layer 21 is not limited in the direction away from the substrate 1.

In some examples, at least one first metal layer comprises M layers and at least one second metal layer comprises N layers, wherein |M-N|+.2; of course, in some examples, the number of layers of the first metal layer and the number of layers of the second metal layer may not necessarily be related.

In some examples, referring again to fig. 6, the at least one first metal layer 21 is one layer, the at least one second metal layer 22 is two layers, namely a second metal layer 22a and a second metal layer 22b, and the substrate 1, the second metal layer 22a, the first metal layer 21, and the second metal layer 22b are sequentially stacked.

For example, the thickness of the first metal layer 21 is 3 μm, the warpage generated by the first metal layer 21 is 1.3mm, and the thickness of each second metal layer 22 is 2000 angstromsThe warpage generated by each second metal layer 22 is-0.65 mm, and then the warpage of the stress neutral layer 2 formed by stacking the first metal layer 21 and the two second metal layers 22 is the sum of the warpage of the first metal layer 21 and the warpage of the two second metal layers 22, namely, the theoretical value is 1.3mm-0.65mm-0.65 mm=0 mm. The actual measurement warp is-0.1 mm, and the actual measurement value and the theoretical calculation value have small differences.

According to the method, the first metal layer 21 generating tensile stress and the second metal layer 22 generating compressive stress are formed on the substrate 1, so that warping acting forces generated by the first metal layer 21 and the second metal layer 22 are mutually neutralized and offset, for example, stress generated by a copper material is tensile stress, stress generated by the second metal layer 22 is compressive stress, the second metal layer 22 can effectively eliminate the tensile stress generated by the copper material, the stress neutral layer 2 is formed, and defects such as cracking of the substrate 1 caused by warping of the metal layer 20 with larger thickness formed by a magnetron sputtering process can be effectively avoided.

In some embodiments, as shown in fig. 9 to 13, at least one first metal layer 21 is a multilayer, at least one second metal layer 22 is located between two first metal layers 21, and at least one first metal layer 21 is located between two second metal layers 22, i.e., the first metal layers 21 and the second metal layers 22 are alternately arranged.

In the case where at least one first metal layer 21 is a plurality of layers and at least one second metal layer 22 is a plurality of layers, the first metal layer 21 and the second metal layer 22 are alternately arranged, that is, the first metal layer 21, the second metal layer 22, and the like are sequentially stacked in a direction away from the substrate 1. Alternatively, the second metal layer 22, the first metal layer 21, and the like are stacked in this order in a direction away from the substrate 1, that is, a single layer of the first metal layer 21 and a single layer of the second metal layer 22 are alternately provided.

Alternatively, the first metal layer 21 and the second metal layer 22 are alternately arranged, which means that the first metal layer 21, the second metal layer 22, the first metal layer 21, the second metal layer 22, and the like are arranged in a direction away from the substrate 1. Alternatively, the second metal layer 22, the first metal layer 21, and the like are stacked in this order in a direction away from the substrate 1, that is, the double-layered first metal layer 21 and the single-layered second metal layer 22 are alternately provided.

Alternatively, the first metal layer 21 and the second metal layer 22 are alternately arranged, which means that the first metal layer 21, the second metal layer 22, and the like are arranged in a direction away from the substrate 1. Alternatively, the second metal layer 22, the first metal layer 21, the second metal layer 22, and the like are stacked in this order in a direction away from the substrate 1, that is, the double-layered first metal layer 21 or the single-layered first metal layer 21 is alternately provided with the single-layered second metal layer 22.

That is, when the first metal layer 21 and the second metal layer 22 are alternately arranged, the first metal layer 21 may be a single layer or a double layer, which is not limited herein, and other embodiments of the present disclosure are similar.

In some examples, as shown in fig. 9, the at least one first metal layer 21 is three layers, that is, the first metal layer 21a, the first metal layer 21b, and the first metal layer 21c, and the at least one second metal layer 22 is three layers, that is, the second metal layer 22a, the second metal layer 22b, and the second metal layer 22c, and the second metal layer 22a, the first metal layer 21b, the second metal layer 22b, the first metal layer 21c, and the second metal layer 22c are sequentially stacked in a direction away from the substrate 1.

In some examples, as shown in fig. 10a, at least one first metal layer 21 is two layers, namely, a first metal layer 21a and a first metal layer 21b, and at least one second metal layer 22 is two layers, namely, a second metal layer 22a and a second metal layer 22b, and the second metal layer 22a, the first metal layer 21a, the second metal layer 22b, and the first metal layer 21b are sequentially stacked in a direction away from the substrate 1.

In some examples, as shown in fig. 11, in the case where at least one first metal layer 21 is two and at least one second metal layer 22 is two, the first metal layer 21a, the second metal layer 22a, the first metal layer 21b, and the second metal layer 22b may be sequentially stacked in a direction away from the substrate 1, which is not limited.

In some examples, as shown in fig. 12, at least one first metal layer 21 is n layers, which are respectively a first metal layer 21a, a first metal layer 21b …, a first metal layer 21n, at least one second metal layer 22 is n layers, which are respectively a second metal layer 22a, a second metal layer 22b …, and a second metal layer 22a, a first metal layer 21a, a second metal layer 22b, a first metal layer 21b …, a second metal layer 22n, and a first metal layer 21n are sequentially stacked in a direction away from the substrate 1. Wherein n is a positive integer greater than or equal to 1.

In some examples, as shown in fig. 13, in the case where at least one first metal layer 21 is n-layered and at least one second metal layer 22 is n-layered, the first metal layer 21a, the second metal layer 22a, the first metal layer 21b, the second metal layer 22b …, the first metal layer 21n, and the second metal layer 22n may be sequentially stacked in a direction away from the substrate 1, which is not limited.

By providing the stress neutral layer 2 with a plurality of first metal layers 21 and a plurality of second metal layers 22, the overall thickness of the first metal layers 21 can be increased. For example, if the first metal layer 21 of the stress neutral layer 2 includes two layers spaced apart from each other, the thickness of the first metal layer 21 is the sum of the thicknesses of the two layers, so that the thickness of the first metal layer 21 is increased while ensuring a reduced warpage.

As shown in fig. 4 and 5, the stress neutral layer 2 includes a first metal layer 21, and the thickness of the first metal layer 21 ranges from 1 μm to 3 μm, and although the first metal layer 21 is less than 5 μm, the stress neutral layer 2 where the first metal layer 21 is located has a small warpage, for example, 0.6mm or 0.63mm as described above.

Illustratively, as shown in FIG. 6, the stress neutral layer 2 includes a first metal layer 21, the thickness of the first metal layer 21 ranging from 1 μm to 4 μm, and the warpage thereof may be, for example, -0.1mm or 0.6mm.

As shown in fig. 10a and 11, the first metal layer 21 in the stress neutral layer 2 includes two layers spaced apart from each other, the thickness of the first metal layer 21 is the sum of the first metal layer 21a and the first metal layer 21b, and the total thickness of the formed first metal layer 21 ranges from 1 μm to 6 μm, and the warpage thereof may be 0.6mm, 0.65mm, or 1mm, for example.

As shown in fig. 12 and 13, the first metal layer 21 in the stress neutral layer 2 includes two layers spaced apart from each other, and the thickness of the first metal layer 21 is the sum of the first metal layer 21a and the first metal layer 21b, and the total thickness of the formed first metal layer 21 ranges from 1 μm to 6 μm, and the warpage thereof may be 0.6mm or 0.65mm, for example. Therefore, the first metal layer 21 having a larger thickness can be formed with less warpage ensured.

In some examples, fig. 10b is an SEM electron microscope image of a circuit board including two first metal layers 21 and two second metal layers 22, and it can be seen that each film layer has better flatness everywhere, and the cross section of the adjacent first metal layers 21 and second metal layers 22 and the cross section of the second metal layers 22 and the substrate 1 are clear, without significant peeling, and better adhesion.

In some implementations, as shown in fig. 13, the sum of the thicknesses d2 of all of the first metal layers 21 in the at least one first metal layer 21 is 70% to 99% of the thickness d4 of the stress neutral layer 2.

Illustratively, the sum of the thicknesses d2 of all the first metal layers 21 is 70%, 75%, 80%, 86%, 95%, 99% or the like of the thickness d4 of the stress neutral layer 2, which is not limited herein.

In some embodiments, the warp of the stress neutral layer 2 is less than or equal to 1mm.

The stress neutral layer 2 is formed by at least one first metal layer 21 having a tensile stress and at least one second metal layer 22 having a compressive stress, and the stress neutral layer 2 having a warp of 1mm or less can be formed by controlling the material and thickness of the at least one first metal layer 21 and the at least one second metal layer 22, so that defects such as chipping of the substrate 1 due to excessive warp can be effectively avoided. The materials and thicknesses of the at least one first metal layer 21 and the at least one second metal layer 22 of the stress neutral layer 2 are described in detail below and will not be described here.

In some embodiments, the material of the second metal layer 22 includes any one of W, WNi, WCu, WMo, WCr and WAl.

By way of example, the material of the second metal layer 22 may be selected from W (tungsten) or WNi (tungsten nickel alloy), WCu (tungsten copper alloy), WMo (tungsten molybdenum alloy), WCr (tungsten chromium alloy), WAl (tungsten aluminum alloy).

Illustratively, when W is used as the material of the second metal layer 22, the relationship between the thickness and the warpage thereof is shown in the graph of fig. 8, and it can be seen that the warpage of the second metal layer 22 is negative, and the warpage of the second metal layer 22 decreases with the increase in the thickness of the second metal layer 22.

In some embodiments, the second metal layer 22 has a resistance in the range of 1×10 ^-8 Ω·m～1×10 ^-5 Omega.m. When the first metal layer 21 and the second metal layer 22 are stacked to form a trace, the resistance of the stacked structure is smaller than that of the first metal layer 21 (copper layer) alone after the stacked structure of the first metal layer 21 (copper) and the second metal layer 22 (tungsten) is formed, and the conductive performance of the stacked structure meets the use requirement.

In some embodiments, as shown in fig. 13, the material of the first metal layer 21 comprises copper.

The material of the first metal layer 21 includes copper, so that a wire made of copper is formed, and an electric signal is transmitted to the wire, thereby meeting the current driving requirement of the Mini-LED.

The film layer of copper in the first metal layer 21 is referred to as a copper layer 20.

In some embodiments, as shown in fig. 13, at least one first metal layer 21 of the at least one first metal layer 21 further comprises at least one buffer layer 211. That is, the at least one metal layer 21 includes a copper layer 20 and at least one buffer layer 211 located on at least one side of the copper layer 20.

Illustratively, referring again to fig. 13, the first metal layer 21 includes a plurality of layers, respectively a first metal layer 21a, a first metal layer 21b …, a first metal layer 21n, wherein the first metal layer 21a is a film layer closest to the substrate 1, the first metal layer 21a includes a copper layer 20 and at least one buffer layer 211, and the buffer layer 211 is included as one layer, one buffer layer 211 is stacked with the copper layer 20, and the buffer layer 211 may be closer to the substrate 1 than the copper layer 20. The first metal layer 21a may include a plurality of buffer layers 211, and is not limited herein.

In some embodiments, the material of the buffer layer 211 includes any one of MoNb, moNiTi, ti, mo and MoTi.

For example, the material of the buffer layer 211 may be MoNb (molybdenum nickel alloy) or MoNiTi (molybdenum nickel titanium alloy), ti (titanium), mo (molybdenum), moTi (molybdenum titanium alloy).

As shown in fig. 13, the adhesion between the first metal layer 21 and the adjacent layer, which may be the substrate 1 or the second metal layer 22, may be increased by providing the buffer layer 211 on one side of the copper layer 20.

In some embodiments, referring again to FIG. 13, the thickness d1 of buffer layer 211 ranges from 0 angstromsAbout 1000 angstroms

The thickness of a certain layer refers to the average value of the dimensions of the layer in the first direction Y perpendicular to the substrate 1, and the thickness is the same as described above and below.

It should be noted that the thickness d1 of the buffer layer 211 is 0 angstrom, and it is understood that the buffer layer 211 may not be provided, and the first metal layer 21 is only a copper layer. In the case where the buffer layer 211 is provided, the buffer layer 211 is exemplified by, but not limited to, 100 a, 300 a, 600 a, 800 a, 1000 a, or the like.

In some embodiments, referring again to fig. 13, the thickness d2 of each first metal layer 21 ranges from 1 μm to 3 μm. The thickness d3 of each second metal layer d3 ranges from 300 angstroms to 5000 angstroms.

The first metal layer 21 is formed by a magnetron sputtering process, for example.

The thickness d2 of the first metal layer 21 is illustratively, but not limited to, 1 μm, 1.5 μm, 2 μm, or 3 μm, etc.

The second metal layer 22 is illustratively formed by a magnetron sputtering process.

Illustratively, the thickness d3 of the second metal layer 22 is 300 angstroms, 1000 angstroms, 1500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 5000 angstroms, or the like, without limitation.

In some embodiments, referring again to fig. 4, in the case where the first metal layer 21 is closest to the substrate 1, the first metal layer 21 includes the copper layer 20 and at least one buffer layer 211, and one of the at least one buffer layer 211 is closer to the substrate 1 than the copper layer 20.

In some examples, as shown in fig. 4, the substrate 1, the first metal layer 21 and the second metal layer 22 are sequentially disposed, where the first metal layer 21 is disposed closest to the substrate 1, the first metal layer 21 includes a copper layer 20 and a buffer layer 211, and the buffer layer 211 is closer to the substrate 1 than the copper layer 20, and the buffer layer 211 may increase adhesion between the copper layer 20 and the substrate 1, thereby improving structural stability.

In some examples, as shown in fig. 11, the substrate 1, the first metal layer 21a, the second metal layer 22a, the first metal layer 21b, and the second metal layer 22b are sequentially stacked, as shown in fig. 13, the substrate 1, the first metal layer 21a, the second metal layer 22a, the first metal layer 21b, the second metal layer 22b …, the first metal layer 21n, and the second metal layer 22n are sequentially stacked, the first metal layer 21a is disposed closest to the substrate 1, and then the first metal layer 21 includes the copper layer 20 and the buffer layer 211, and the buffer layer 211 is closer to the substrate 1 than the copper layer 20. For the first metal layer 21 relatively far from the substrate 1, for example, the first metal layer 21b, the buffer layer 211 may be included or the buffer layer 211 may not be included, which is not limited herein.

In some examples, as shown in fig. 12, the second metal layer 22a, the first metal layer 21a, the second metal layer 22b, the first metal layer 21b …, the second metal layer 22n, and the first metal layer 21n are sequentially stacked on the substrate 1, and since the second metal layer 22a is closest to the substrate 1, the buffer layer 211 may not be provided on the first metal layer 21a, which may not only simplify the process flow but also reduce the process cost.

In some embodiments, the substrate 1 is a glass substrate, i.e. the substrate 1 is the glass substrate 11 described above.

Illustratively, the glass substrate is alkali-free glass, alkali glass, strengthened glass, or tempered glass. The glass substrate has good flatness, no need of splicing, high process precision, high heat conductivity and strong heat dissipation.

In some embodiments, as shown in fig. 14, the stress neutral layer 2 includes a plurality of patterns 23 formed by etching, each pattern 23 including a sub-pattern 23' formed by stacking layers, i.e., each pattern 23 includes a plurality of sub-patterns 23', the plurality of sub-patterns 23' being stacked in the first direction Y. In the case where the stress neutral layer 2 comprises a plurality of first metal layers 21 and at least one second metal layer 22, the slope angle α of the sub-pattern 23 'formed by the stack of layers relatively far from the substrate 1 in each pattern 23 is smaller than the slope angle α of the sub-pattern 23' formed by the stack of layers relatively close to the substrate 1, wherein the stack is the stack of the first metal layer 21, the second metal layer 22 or the adjacent second metal layer 22 and the first metal layer 21.

It will be understood that in the embodiments of the present disclosure, the slope angle of a film pattern refers to the angle between the side surface of the film pattern and the plane of the substrate 1 in a cross section perpendicular to the plane of the substrate 1 and perpendicular to the extending direction of the film pattern.

In some examples, referring again to fig. 14, the first metal layer 21 in the stress neutral layer 2 includes two layers spaced apart from each other, that is, a first metal layer 21a and a first metal layer 21b, a second metal layer 22 is disposed between the first metal layer 21a and the first metal layer 21b, the substrate 1, the first metal layer 21a, the second metal layer 22, and the first metal layer 21b are sequentially stacked, the first metal layer 21a is a stack, the second metal layer 22 and the first metal layer 21b are used as a stack, and after etching, different sub-patterns 23' are formed, that is, a first sub-pattern 231 and a second sub-pattern 232, respectively, the first sub-pattern 231 is closer to the substrate 1 than the second sub-pattern 232, and a gradient angle α1 of the first sub-pattern 231 is greater than a gradient angle α2 of the second sub-pattern 232.

It should be noted that, as shown in fig. 14, the thickness d2 of the first metal layer 21 is far greater than the thickness d3 of the second metal layer 22, taking the second metal layer 22 and the first metal layer 21b as examples, when the stress neutral layer is etched, since the second metal layer 22 is too thin, at the etching interface, the first metal layer 21b located on the side of the second metal layer 22 away from the substrate 1 and the interface transition with the second metal layer 22 are smoother, and the slope angle of the sub-pattern formed by etching the first metal layer 21 is approximately equal to the slope angle of the sub-pattern formed by etching the first metal layer 21b and the second metal layer 22 as a whole, so that, when the pattern formed by dividing the stack is divided, the pattern 23 formed by the second metal layer 22 and the first metal layer 21 which are next arranged in sequence can be regarded as the same sub-pattern 23, for example, the sub-pattern 23 formed by the second metal layer 22 and the first metal layer 21b is regarded as the second sub-pattern 232.

It will be appreciated that the sub-patterns formed by etching the stack of the first metal layer 21a, the second metal layer 22 and the first metal layer 21b may also be regarded as a separate sub-pattern for each metal layer, and it can be seen from the figure that the slope angle α of the sub-pattern formed by the stack relatively far from the substrate 1 is smaller in each pattern 23 than the slope angle α of the sub-pattern formed by the stack relatively close to the substrate 1.

In each pattern 23 of the stress neutral layer 2, each stack is etched to form a sub-pattern 23', the slope angle α of the sub-pattern 23' formed by the stack relatively far from the substrate 1 in all the sub-patterns 23 'is smaller than the slope angle α of the sub-pattern 23' formed by the stack relatively close to the substrate 1, i.e. the stress neutral layer 2 is formed to have a gradient slope angle, which does not affect the coverage of the stress neutral layer by the subsequent inorganic material insulating layer (such as the first passivation layer 51 and/or the second passivation layer 54) or the organic material insulating layer (such as the insulating layer 52 and/or the flat layer 53), and the stress neutral layer 2 can have better adhesion with the inorganic film layer covering the stress neutral layer 2.

Referring again to fig. 14, a notch is used in the stress neutral layer 2When the etching process is used for patterning, one side of the substrate 1 far away from the photoresist pattern PR after exposure is covered with the photoresist pattern PR as a mask, and the boundary of the photoresist pattern PR in the second direction X can be seen to exceed the boundary of the pattern left on the stress neutral layer 2 in the second direction X after the etching process; that is, after etching, the stress neutral layer 2 is set back by a certain amount with respect to the photoresist PR. Specifically, the boundary of the photoresist pattern PR in the second direction X exceeds the outermost boundary L of the sub-pattern formed in the stress neutral layer 2 relatively close to the stack of the substrate 1 ₂ Length, the boundary of the photoresist pattern PR in the second direction X exceeds the innermost boundary L of the sub-pattern formed by the stack relatively far from the substrate 1 in the stress neutral layer 2 ₁ Length. The second direction X is a direction parallel to the plane of the substrate 1 and perpendicular to the extending direction of the pattern.

The etching may be a dry etching process or a wet etching process, for example.

It should be noted that fig. 14 only shows an SEM image of the edge positions of the first metal layer 21 and the second metal layer 22 after etching to form the pattern 23 in one embodiment, and does not represent the morphology of the other embodiment, that is, fig. 14 is not a limitation of forming the pattern 23 after etching the first metal layer 21 and the second metal layer 22. It will be appreciated that by adjusting the formulation or concentration of the etching solution or the etching time, the stress neutral layer 2 may have a plurality of stacked layers with the same slope angle after etching, and the side surfaces of the stacked layers are substantially in the same plane.

Furthermore, it will be appreciated that the difference in the material, thickness, and distance from the substrate 1 between each of the first metal layers 21 and each of the second metal layers 22 in the stress neutral layer 2 may result in a different reaction rate with the etching solution, and in some embodiments, for the layer of the stress neutral layer 2 furthest from the substrate 1, which may form a roof structure after etching (i.e. which exceeds the other layers by a certain length in the second direction X), in which case the length of the roof structure may be controlled by adding an additive to the etching solution, preferably not exceeding 0.5 um.

In some embodiments, referring again to fig. 14, each of the plurality of etched patterns 23 includes any one of the sub-patterns 23' having an angle of gradient α ranging from 20 ° to 70 °.

Illustratively, the angle of the slope angle α of the sub-pattern 23' in the stress neutral layer 2 is 20 °, 30 °, 40 °, 60 °, 70 °, or the like, without limitation.

Other embodiments of the present disclosure provide a light emitting substrate 100, as shown in fig. 15, including the circuit board 10 described above. The light emitting substrate 100 further includes a plurality of light emitting devices L.

In some examples, referring again to fig. 15, in the light emitting substrate 100, the first metal layer 301 is disposed on a side of the substrate 1, the first metal layer 301 includes a plurality of first signal lines 301a, the first passivation layer 51 is disposed on a side of the first metal layer 301 away from the substrate 1, the insulating layer 52 is disposed on a side of the first metal layer 301 away from the substrate 1, the second metal layer 302 is disposed on a side of the insulating layer 52 away from the substrate 1, the planarization layer 53 is disposed on a side of the second metal layer 302 away from the substrate 1, and the second passivation layer 54 is disposed on a side of the planarization layer 53 away from the substrate 1.

The plurality of first signal lines 301a include a first power line Hm2 or a second power line Hm1, for example.

The second metal layer 302 includes a plurality of electrode pads 302b, and a second signal line 302a connected to at least two electrode pads of the plurality of electrode pads 302 b. The plurality of electrode pads 302b are used for electrically connecting with the pins of the light emitting device L and the pixel driving chip M, and specifically, the pins of the light emitting device L and the pins of the pixel driving chip M are connected with the corresponding electrode pads 302b through a solder material S (e.g., solder, tin-silver-copper alloy, tin-copper alloy, etc.). The planarization layer 53 includes a plurality of second vias a2, and the plurality of second vias a2 penetrate through to the second metal layer 302. The passivation layer 54 includes a plurality of third vias a3, and the plurality of third vias a3 penetrate through to the planarization layer 53. Wherein, a third via a3 and a second via a2 are formed corresponding to each other, and a through hole penetrating from the second passivation layer 54 to the electrode pad 302b of the second metal layer 302 is formed.

Illustratively, the leads of the light emitting device L are connected to the two electrode pads 302b through the through holes penetrating the planarization layer 53 and the second passivation layer 54, and the leads of the pixel driving chip M are connected to the electrode pads 302b through the vias penetrating the planarization layer 53 and the second passivation layer 54, so that the light emitting device L can emit light under the control of the pixel driving chip M.

The stress neutral layer 2 formed by the at least one first metal layer 21 and the at least one second metal layer 22 is used as the first power line Hm2 or the second power line Hm1, so that the thickness of the first power line Hm2 or the second power line Hm1 is increased, the requirement of low resistance is realized, and the influence of warping is effectively avoided.

Illustratively, the material of the first passivation layer 51 and/or the second passivation layer 54 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the insulating layer 52 and/or the planarization layer 53 is an organic material, such as a resin.

In some embodiments, the light emitting device L is a sub-millimeter light emitting diode or a micro light emitting diode.

The light emitting device L includes, for example, a red light emitting diode, a green light emitting diode, or a blue light emitting diode.

By way of example, a sub-millimeter light emitting diode refers to an LED having a die size of about 50 μm to 200 μm, and a micro light emitting diode refers to an LED having a die size of less than 50 μm.

The beneficial effects of the light-emitting substrate 100 are the same as those of the circuit board 10 provided in the first aspect of the present disclosure, and will not be described here again.

Some embodiments of the present disclosure further provide a backlight module 200, as shown in fig. 16, the backlight module 200 includes the light emitting substrate 100 as described above.

It is understood that the light emitting substrate 100 includes a plurality of light emitting devices L.

The beneficial effects of the backlight module 200 are the same as those of the light-emitting substrate 100 provided in the disclosure, and will not be described here again.

Some embodiments of the present disclosure further provide a display device 1000, as shown in fig. 17, where the display device 1000 includes the backlight module 200 as described above, and further includes a liquid crystal display panel 300 connected to the backlight module 200.

It can be understood that the liquid crystal display panel 300 is disposed on the light emitting side E of the backlight module 200.

For example, referring again to fig. 17, the display device 1000 further includes a plurality of optical films 301, and the plurality of optical films 301 are located between the backlight module 200 and the liquid crystal display panel 300 for adjusting the light output of the backlight module 200.

The beneficial effects of the display device 1000 are the same as those of the backlight module 200 provided by the present disclosure, and will not be described herein.

The display device 1000 described above may be any device that displays an image whether in motion (e.g., video) or stationary (e.g., still image) and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

Some embodiments of the present disclosure also provide a display panel 400, as shown in fig. 18, the display panel 400 including the light emitting substrate 100 as described above.

By way of example, the application of the light-emitting substrate 100 to a Mini-LED display screen can further reduce the dot pitch of the display screen, thereby greatly improving the visual effect of the corresponding terminal product and greatly reducing the viewing distance.

The beneficial effects of the display panel 400 are the same as those of the light-emitting substrate 100 provided in the present disclosure, and will not be described here again.

Some embodiments of the present disclosure also provide a display device 2000, as shown in fig. 19, the display device 2000 including the display panel 400 as described above.

The display device 2000 described above may be any device that displays images whether in motion (e.g., video) or stationary (e.g., still image) and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

The beneficial effects of the display device 2000 are the same as those of the display panel 400 provided by the present disclosure, and will not be described herein.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

A circuit board, comprising:

a substrate;

a stress neutral layer arranged on one side of the substrate;

wherein the stress neutral layer comprises:

at least one first metal layer;

at least one second metal layer laminated with the at least one first metal layer; and the material of at least one first metal layer of the at least one first metal layer is a material generating tensile stress, and the material of at least one second metal layer of the at least one second metal layer is a material generating compressive stress.
The circuit board of claim 1, wherein the at least one first metal layer is a plurality of layers, the at least one second metal layer is located between two first metal layers, and the at least one first metal layer is located between two second metal layers.
The circuit board of claim 1 or 2, wherein the sum of the thicknesses of all of the at least one first metal layer is 70-99% of the stress neutral layer thickness.
The wiring board according to any one of claims 1 to 3, wherein the warp of the stress neutral layer is 1mm or less.
The wiring board according to any one of claims 1 to 4, wherein the material of the second metal layer comprises any one of W, WNi, WCu, WMo, WCr and WAl.
The circuit board of claim 5, wherein the second metal layer has a resistance in a range of 1 x 10 ^-8 Ω·m～1×10 ^-5 Ω·m。
The circuit board of any of claims 1-6, wherein the material of the first metal layer comprises copper.
The circuit board of claim 7, wherein at least one of the at least one first metal layer further comprises at least one buffer layer.
The wiring board of claim 8, wherein the material of the buffer layer comprises any one of MoNb, moNiTi, ti, mo and MoTi.
The wiring board according to claim 8 or 9, wherein the thickness of the buffer layer ranges from 0 to 1000 angstroms.
The wiring board according to any one of claims 1 to 10, wherein a thickness of each first metal layer ranges from 1 μm to 3 μm;

Each second metal layer has a thickness in the range of 300 angstroms to 5000 angstroms.
The circuit board of any of claims 1-11, wherein a first metal layer of the at least one first metal layer closest to the substrate comprises a copper layer and at least one buffer layer; and one of the at least one buffer layer is closer to the substrate than the copper layer.
The wiring board according to any one of claims 1 to 12, wherein the substrate is a glass substrate.
The wiring board of any one of claims 1-13, wherein the stress neutral layer comprises a plurality of patterns formed by etching, each pattern of the plurality of patterns comprising a sub-pattern formed by a respective stack; in the case where the stress neutral layer includes a plurality of first metal layers and at least one second metal layer, a slope angle of a sub-pattern formed by a stack relatively far from the substrate is smaller than a slope angle of a sub-pattern formed by a stack relatively close to the substrate in the pattern; wherein the lamination is any one of a first metal layer, a second metal layer or a combined film layer adjacent to the first metal layer and the second metal layer.
The circuit board of claim 14, wherein the slope angle of any one of the sub-patterns is in the range of 20 ° to 70 °.
A light emitting substrate comprising a wiring board according to any one of claims 1 to 15, wherein the stress neutral layer is used to form traces and/or electrode pads.
The light emitting substrate of claim 16, further comprising:

the LED comprises a plurality of LEDs, wherein the LEDs comprise first pins and second pins, the electrode pads comprise first electrode pads and second electrode pads, and the wires comprise first wires and second wires;

the first wiring is connected with a first pin of the light emitting diode through the first electrode pad;

the second wiring is connected with a second pin of the light emitting diode through the second electrode pad.
The light emitting substrate of claim 17, wherein the electrode pad material is further one of WNi and WCu.
The light emitting substrate of claim 17 or 18, wherein the light emitting diode is a sub-millimeter light emitting diode or a micro light emitting diode.
A backlight module comprising a light emitting substrate according to any one of claims 16 to 19.
A display device comprising the backlight module of claim 20;

the backlight module is connected with the liquid crystal display panel.
A display panel comprising the light-emitting substrate according to any one of claims 16 to 19.
A display device comprising the display panel of claim 22.