CN117375578A - Six-bit broadband digital phase shifter - Google Patents
Six-bit broadband digital phase shifter Download PDFInfo
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- H—ELECTRICITY
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- H03H17/08—Networks for phase shifting
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
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Abstract
The application relates to a six-bit broadband digital phase shifter, comprising: a combined structure of a 5.625-degree phase shifting unit, an 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit. Wherein, 180 phase shift unit integrated configuration includes: and the 90-degree phase shifting units are of two three-order high-low pass structures which are connected in series. The third-order high-low pass structure comprises: the first equivalent single-pole double-throw switch, the second equivalent single-pole double-throw switch, the high-pass filtering branch and the low-pass filtering branch; the first equivalent single-pole double-throw switch is connected with the first ends of the high-pass filtering branch circuit and the low-pass filtering branch circuit; the second equivalent single-pole double-throw switch is connected with the second ends of the high-pass filtering branch and the low-pass filtering branch; the high pass filtering branch is connected in parallel with the low pass filtering branch. In the method, a 180-degree phase shifting subunit structure is changed into a 90-degree phase shifting unit series structure with two three-order high-low pass structures, so that the layout area of the six-bit broadband digital phase shifter is greatly reduced.
Description
Technical Field
The application relates to the technical field of phase shifters, in particular to a six-bit broadband digital phase shifter.
Background
The phase shifter is a two-port network, which is an element used to change the phase transmission of signals. The working state of the radio frequency circuit is changed through the direct-current bias voltage acting on the control switch device, so that the phases of the output port and the input port are changed, and the purpose of specific phase shifting is achieved. For different application scenes, different classification standards are provided for the phase shifter. The phase shifter may be classified into an analog type and a digital type according to the continuity of phase transmission. The phase shift value of the analog phase shifter realizes 0-360 DEG phase continuous change, and the phase shift value of the digital phase shifter is a plurality of discrete values. The digital phase shifter has two types of transmission type and reflection type phase shifters according to the transmission type, including switch line, loading line, high-low pass, reflection type circuit topology and the like.
The digital phase shifter has the advantages of convenient interface, high response speed, high phase shifting precision, good consistency and the like, and is widely applied to phased array radars and communication systems. The common six-bit digital phase shifter consists of six basic bits, namely 5.625 degrees, 11.25 degrees, 22.5 degrees, 45 degrees, 90 degrees and 180 degrees, and 64 phase shifting states with a stepping value of 5.625 degrees and a phase shifting range of 0-360 degrees can be realized by controlling the combination of six phase shifting units.
The multi-channel guard through multifunctional chip integrated with the phase shifter adopts the gallium arsenide compound technology, and when the chip area is too large, the use links of the packaging clamping piece and the like can have larger splitting risks (the thickness is 0.1 mm). The existing six-bit broadband digital phase shifter adopts five-order high-low pass structure for 180 DEG phase shifting subunit, so that the occupied area of the phase shifter chip is large, and the structure is unfavorable for being applied to the integration of the multifunctional guard chip.
Disclosure of Invention
In order to overcome the problem that the six-bit broadband digital phase shifter chip in the related technology occupies a large area at least to a certain extent, and the structure is unfavorable for being applied to the integration of the multifunctional guard chip, the application provides a six-bit broadband digital phase shifter.
The scheme of the application is as follows:
a six-bit wideband digital phase shifter, comprising:
a combined structure of a 5.625-degree phase shifting unit, an 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit;
the 180 DEG phase shift unit combination structure comprises: the 90-degree phase shifting unit is connected with two three-order high-low pass structures in series;
the third-order high-low pass structure comprises: the first equivalent single-pole double-throw switch, the second equivalent single-pole double-throw switch, the high-pass filtering branch and the low-pass filtering branch;
the first equivalent single-pole double-throw switch is connected with the first ends of the high-pass filtering branch circuit and the low-pass filtering branch circuit;
the second equivalent single-pole double-throw switch is connected with the second ends of the high-pass filtering branch and the low-pass filtering branch;
the high-pass filtering branch is connected in parallel with the low-pass filtering branch.
Preferably, the third-order high-low pass structure includes:
a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first inductor and a second inductor;
the first equivalent single-pole double-throw switch is formed by the first MOS tube, the second MOS tube, the fifth MOS tube and the sixth MOS tube;
the third MOS tube, the fourth MOS tube, the seventh MOS tube and the eighth MOS tube form the second equivalent single-pole double-throw switch;
the first capacitor, the second capacitor and the first inductor form the high-pass filtering branch;
the third capacitor, the fourth capacitor and the second inductor form the low-pass filtering branch.
Preferably, the source electrode of the first MOS tube is connected with the signal input end, the grid electrode is connected with the negative electrode of the power supply, and the drain electrode is connected with the source electrode of the second MOS tube, the first end of the first capacitor and the first end of the first inductor;
the drain electrode of the second MOS tube is grounded, and the grid electrode of the second MOS tube is connected with the positive electrode of the power supply;
the second end of the first capacitor is grounded;
the second end of the first inductor is connected with the first end of the second capacitor, the source electrode of the third MOS tube and the source electrode of the fourth MOS tube;
the second end of the second capacitor is grounded;
the drain electrode of the third MOS tube is connected with the signal output end, and the grid electrode of the third MOS tube is connected with the negative electrode of the power supply;
and the drain electrode of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is connected with the positive electrode of the power supply.
Preferably, the source electrode of the fifth MOS tube is connected with the signal input end, the grid electrode is connected with the positive electrode of the power supply, and the drain electrode is connected with the source electrode of the sixth MOS tube and the first end of the third capacitor;
the drain electrode of the sixth MOS tube is grounded, and the grid electrode is connected with the negative electrode of the power supply;
the second end of the third capacitor is connected with the first end of the second inductor and the first end of the fourth capacitor;
the second end of the second inductor is grounded;
the second end of the fourth capacitor is connected with the source electrode of the seventh MOS tube and the source electrode of the eighth MOS tube;
the drain electrode of the seventh MOS tube is connected with the signal output end, and the grid electrode of the seventh MOS tube is connected with the positive electrode of the power supply;
and the drain electrode of the eighth MOS tube is grounded, and the grid electrode is connected with the negative electrode of the power supply.
Preferably, the third-order high-low pass structure further includes:
a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;
the grid electrode of the first MOS tube is connected with the negative electrode of the power supply through the first resistor;
the grid electrode of the second MOS tube is connected with the positive electrode of the power supply through the second resistor;
the grid electrode of the third MOS tube is connected with the negative electrode of the power supply through the third resistor;
the grid electrode of the fourth MOS tube is connected with the positive electrode of the power supply through the fourth resistor;
the grid electrode of the fifth MOS tube is connected with the positive electrode of the power supply through the fifth resistor;
the grid electrode of the sixth MOS tube is connected with the negative electrode of the power supply through the sixth resistor;
the grid electrode of the seventh MOS tube is connected with the positive electrode of the power supply through the seventh resistor;
and the grid electrode of the eighth MOS tube is connected with the negative electrode of the power supply through the eighth resistor.
Preferably, when the center angular frequency satisfies the impedance matching, a capacitance value and an inductance value corresponding to the desired insertion phase are determined by the desired insertion phase, the center angular frequency, and the characteristic impedance.
Preferably, the phase shift bit map of the third-order high-low pass structure is generated based on a circuit diagram of the third-order high-low pass structure.
Preferably, the phase shift bit layout of the 180 DEG phase shift unit combined structure is composed of phase shift bit layouts of two three-order high-low pass structures.
The technical scheme that this application provided can include following beneficial effect: a six-bit wideband digital phase shifter in this application, comprising: a combined structure of a 5.625-degree phase shifting unit, an 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit. Wherein, 180 phase shift unit integrated configuration includes: and the 90-degree phase shifting units are of two three-order high-low pass structures which are connected in series. The third-order high-low pass structure comprises: the first equivalent single-pole double-throw switch, the second equivalent single-pole double-throw switch, the high-pass filtering branch and the low-pass filtering branch; the first equivalent single-pole double-throw switch is connected with the first ends of the high-pass filtering branch circuit and the low-pass filtering branch circuit; the second equivalent single-pole double-throw switch is connected with the second ends of the high-pass filtering branch and the low-pass filtering branch; the high pass filtering branch is connected in parallel with the low pass filtering branch. In order to reduce the layout area of a phase shifter chip and improve the layout design flexibility, the structure of the phase shifting subunit of 180 degrees is changed into a serial structure of 90-degree phase shifting units of two three-order high-low-pass structures, and the layout area of the six-bit broadband digital phase shifter is greatly reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a three-order high-low pass structure in a six-bit wideband digital phase shifter according to one embodiment of the present application;
FIG. 2 is a schematic block diagram of a prior art six-bit wideband digital phase shifter;
FIG. 3 is a schematic block diagram of a six-bit wideband digital phase shifter provided in one embodiment of the present application;
FIG. 4 is a schematic block diagram of a third order high-low pass architecture in a six-bit wideband digital phase shifter according to one embodiment of the present application;
FIG. 5 is a phase shift bit layout of a single third order high low pass structure in a six-bit wideband digital phase shifter provided in one embodiment of the present application;
fig. 6 is a phase shift layout of a 180 ° phase shift unit combination structure in a six-bit wideband digital phase shifter according to one embodiment of the present application.
Reference numerals: a first MOS transistor-M1; a second MOS transistor-M2; a third MOS tube-M3; a fourth MOS transistor-M4; fifth MOS tube-M5; a sixth MOS transistor-M6; seventh MOS tube-M7; eighth MOS transistor-M8; a first capacitor-C1; a second capacitor-C2; a third capacitor-C3; a fourth capacitance-C4; a first inductance-L1; a second inductance-L2; a first resistor-R1; a second resistor-R2; a third resistor-R3; a fourth resistor-R4; a fifth resistor-R5; a sixth resistor-R6; a seventh resistor-R7; eighth resistor-R8.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
Fig. 1 is a schematic circuit diagram of a third-order high-low-pass structure in a six-bit wideband digital phase shifter according to an embodiment of the present application, and referring to fig. 1, a six-bit wideband digital phase shifter includes:
a combined structure of a 5.625-degree phase shifting unit, an 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit;
the 180 DEG phase shift unit combination structure comprises: the 90-degree phase shifting unit is connected with two three-order high-low pass structures in series;
the third-order high-low pass structure comprises: the first equivalent single-pole double-throw switch, the second equivalent single-pole double-throw switch, the high-pass filtering branch and the low-pass filtering branch;
the first equivalent single-pole double-throw switch is connected with the first ends of the high-pass filtering branch circuit and the low-pass filtering branch circuit;
the second equivalent single-pole double-throw switch is connected with the second ends of the high-pass filtering branch and the low-pass filtering branch;
the high pass filtering branch is connected in parallel with the low pass filtering branch.
As shown in fig. 2, the existing six-bit broadband digital phase shifter is composed of six basic bits, which are 5.625 °,11.25 °,22.5 °,45 °,90 ° and 180 °, respectively, and 64 phase shifting states with a step value of 5.625 ° and a phase shifting range of 0 ° -360 ° can be realized by controlling the combination of six phase shifting units.
In fig. 2, P1 is a signal input terminal, and P2 is a signal output terminal.
In order to reduce the layout area of a phase shifter chip and improve the layout design flexibility, the structure of a 180-degree phase shifting subunit is changed into a 90-degree phase shifting unit series structure of two three-order high-low pass structures, and the layout area of the six-bit broadband digital phase shifter is greatly reduced as shown in fig. 3.
In fig. 3, P1 is a signal input terminal, and P2 is a signal output terminal.
It should be noted that, the high-low pass structure is the most commonly used structure of three large phase shifting units of 45 °,90 ° and 180 ° as the switch-type phase shifter structure, and the schematic block diagram of the three-order high-low pass structure in the six-bit wideband digital phase shifter in this embodiment is shown in fig. 4.
In fig. 4, P1 is a signal input terminal, and P2 is a signal output terminal.
It should be noted that, referring to fig. 1, the third-order high-low pass structure in this embodiment includes:
the MOS transistor comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first inductor L1 and a second inductor L2;
the first MOS tube M1, the second MOS tube M2, the fifth MOS tube M5 and the sixth MOS tube M6 form a first equivalent single-pole double-throw switch;
the third MOS tube M3, the fourth MOS tube M4, the seventh MOS tube M7 and the eighth MOS tube M8 form a second equivalent single-pole double-throw switch;
the first capacitor C1, the second capacitor C2 and the first inductor L1 form a high-pass filtering branch;
the third capacitor C3, the fourth capacitor C4 and the second inductor L2 form a low-pass filtering branch.
The source electrode of the first MOS tube M1 is connected with the signal input end, the grid electrode is connected with the negative electrode of the power supply, and the drain electrode is connected with the source electrode of the second MOS tube M2, the first end of the first capacitor C1 and the first end of the first inductor L1;
the drain electrode of the second MOS tube M2 is grounded, and the grid electrode is connected with the positive electrode of the power supply;
the second end of the first capacitor C1 is grounded;
the second end of the first inductor L1 is connected with the first end of the second capacitor C2, the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4;
the second end of the second capacitor C2 is grounded;
the drain electrode of the third MOS tube M3 is connected with the signal output end, and the grid electrode is connected with the negative electrode of the power supply;
the drain electrode of the fourth MOS tube M4 is grounded, and the grid electrode is connected with the positive electrode of the power supply.
The source electrode of the fifth MOS tube M5 is connected with the signal input end, the grid electrode is connected with the positive electrode of the power supply, and the drain electrode is connected with the source electrode of the sixth MOS tube M6 and the first end of the third capacitor C3;
the drain electrode of the sixth MOS tube M6 is grounded, and the grid electrode is connected with the negative electrode of the power supply;
the second end of the third capacitor C3 is connected with the first end of the second inductor L2 and the first end of the fourth capacitor C4;
the second end of the second inductor L2 is grounded;
the second end of the fourth capacitor C4 is connected with the source electrode of the seventh MOS tube M7 and the source electrode of the eighth MOS tube M8;
the drain electrode of the seventh MOS tube M7 is connected with the signal output end, and the grid electrode is connected with the positive electrode of the power supply;
the drain electrode of the eighth MOS tube M8 is grounded, and the grid electrode is connected with the negative electrode of the power supply.
In the embodiment, a first equivalent single-pole double-throw switch is formed by a first MOS tube M1, a second MOS tube M2, a fifth MOS tube M5 and a sixth MOS tube M6; a second equivalent single-pole double-throw switch is formed by a third MOS tube M3, a fourth MOS tube M4, a seventh MOS tube M7 and an eighth MOS tube M8; the series switch determines insertion loss and the parallel MOS die improves circuit isolation.
The first capacitor C1, the second capacitor C2 and the first inductor L1 form a high-pass filtering branch;
the third capacitor C3, the fourth capacitor C4 and the second inductor L2 form a low-pass filtering branch
As shown in fig. 4, the phase shift function is realized by the difference in phase frequency characteristics of two network parameter functions by switching signals between the high pass filter branch HPF and the low pass filter branch LPF through the single pole double throw switches SW1 and SW 2.
In specific practice, the third-order high-low pass structure further comprises:
the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8;
the grid electrode of the first MOS tube M1 is connected with the negative electrode of the power supply through a first resistor R1;
the grid electrode of the second MOS tube M2 is connected with the positive electrode of the power supply through a second resistor R2;
the grid electrode of the third MOS tube M3 is connected with the negative electrode of the power supply through a third resistor R3;
the grid electrode of the fourth MOS tube M4 is connected with the positive electrode of the power supply through a fourth resistor R4;
the grid electrode of the fifth MOS tube M5 is connected with the positive electrode of the power supply through a fifth resistor R5;
the grid electrode of the sixth MOS tube M6 is connected with the negative electrode of the power supply through a sixth resistor R6;
the grid electrode of the seventh MOS tube M7 is connected with the positive electrode of the power supply through a seventh resistor R7;
the grid electrode of the eighth MOS tube M8 is connected with the negative electrode of the power supply through an eighth resistor R8.
When the center angular frequency satisfies impedance matching, the capacitance value and the inductance value corresponding to the required insertion phase are determined by the required insertion phase, the center angular frequency and the characteristic impedance.
The calculation formula is as follows:
；
；
wherein,representing the required insertion phase,/->Represents the center angular frequency, +.>Representing the characteristic impedance, the value is 50Ω; l (L) 1 An inductance value representing the first inductance L1; l (L) 2 An inductance value representing the second inductance L2; c (C) 1 The capacitance values of the first capacitor C1 and the second capacitor C2 (the capacitance values of the first capacitor C1 and the second capacitor C2 are the same); c (C) 2 The capacitance values of the third capacitor C3 and the fourth capacitor C4 are indicated (the capacitance values of the third capacitor C3 and the fourth capacitor C4 are the same).
When (when)When the circuit parameter is 90 degrees, circuit parameters (capacitance value and inductance value) of the central frequency point can be calculated, and based on the calculated circuit parameters, circuit schematic diagram design is carried out by combining actual measurement data of the switch tube core.
The phase shift bit map of the third-order high-low pass structure is generated based on the circuit diagram of the third-order high-low pass structure.
In specific practice, after the circuit diagram of the third-order high-low pass structure is simulated and debugged to ideal performance, the third-order high-low pass structure is generated based on the circuit diagram of the third-order high-low pass structureThe layout area of 90 DEG phase shifting unit is about 550 x 350um as shown in figure 5 2 。
It should be noted that, in the 180 ° phase shift unit, when the broadband is large and the phase shift is large, it is difficult for a typical three-order high-low pass filter to achieve ideal bandwidth and phase flatness. The conventional technical scheme is that the filter order is increased, a seven-order high-pass five-order low-pass phase shift network is adopted to reduce the matching difficulty of circuits, expand the response bandwidth of a phase shifter and increase the phase shift value, but simultaneously sacrifice very large circuit size and insertion loss, reduce the flexibility of the integral typesetting of a chip layout, and the layout area is about 1100 x 900um 2 。
By comparing the 90 ° phase shift units 550 x 350um in fig. 5 2 1100 x 900um of phase shift unit with 180 degree and layout area of (2) 2 The layout area of the phase shifter chip full-page layout area reduction optimization is not facilitated by using the seven-order high-pass five-order low-pass structure of the traditional 180-degree phase shifting unit. Therefore, the application proposes a 90-degree phase shifting unit with a traditional 180-degree phase shifting unit structure changed into two three-order high-low pass structures connected in series, the actual layout is shown in figure 6, and the layout area is about 550 x 700um 2 。
Namely, under the same gallium arsenide technology, the layout area (1100 x 900 um) of the seven-order high-pass five-order low-pass structure of the traditional 180 DEG phase shifting unit 2 ) Is far larger than the layout area (550 x 700 um) of the 180-degree phase shifting unit of the application 2 ）。
According to the technical scheme, the 180-degree phase shifting subunit structure is changed into the 90-degree phase shifting unit serial structure with two three-order high-low pass structures, and the layout area of the six-bit broadband digital phase shifter is greatly reduced.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (8)
1. A six-bit wideband digital phase shifter, comprising:
a combined structure of a 5.625-degree phase shifting unit, an 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit;
the 180 DEG phase shift unit combination structure comprises: the 90-degree phase shifting unit is connected with two three-order high-low pass structures in series;
the third-order high-low pass structure comprises: the first equivalent single-pole double-throw switch, the second equivalent single-pole double-throw switch, the high-pass filtering branch and the low-pass filtering branch;
the first equivalent single-pole double-throw switch is connected with the first ends of the high-pass filtering branch circuit and the low-pass filtering branch circuit;
the second equivalent single-pole double-throw switch is connected with the second ends of the high-pass filtering branch and the low-pass filtering branch;
the high-pass filtering branch is connected in parallel with the low-pass filtering branch.
2. The six bit wideband digital phase shifter of claim 1, wherein the three-order high-low pass structure comprises:
the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first inductor and a second inductor;
the first equivalent single-pole double-throw switch is formed by the first MOS tube, the second MOS tube, the fifth MOS tube and the sixth MOS tube;
the third MOS tube, the fourth MOS tube, the seventh MOS tube and the eighth MOS tube form the second equivalent single-pole double-throw switch;
the first capacitor, the second capacitor and the first inductor form the high-pass filtering branch;
the third capacitor, the fourth capacitor and the second inductor form the low-pass filtering branch.
3. The six-bit wideband digital phase shifter according to claim 2, wherein the source electrode of the first MOS transistor is connected to the signal input terminal, the gate electrode is connected to the negative electrode of the power supply, and the drain electrode is connected to the source electrode of the second MOS transistor, the first end of the first capacitor, and the first end of the first inductor;
the drain electrode of the second MOS tube is grounded, and the grid electrode of the second MOS tube is connected with the positive electrode of the power supply;
the second end of the first capacitor is grounded;
the second end of the first inductor is connected with the first end of the second capacitor, the source electrode of the third MOS tube and the source electrode of the fourth MOS tube;
the second end of the second capacitor is grounded;
the drain electrode of the third MOS tube is connected with the signal output end, and the grid electrode of the third MOS tube is connected with the negative electrode of the power supply;
and the drain electrode of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is connected with the positive electrode of the power supply.
4. The six-bit wideband digital phase shifter according to claim 2, wherein the source electrode of the fifth MOS transistor is connected to the signal input terminal, the gate electrode is connected to the positive electrode of the power supply, and the drain electrode is connected to the source electrode of the sixth MOS transistor and the first end of the third capacitor;
the drain electrode of the sixth MOS tube is grounded, and the grid electrode is connected with the negative electrode of the power supply;
the second end of the third capacitor is connected with the first end of the second inductor and the first end of the fourth capacitor;
the second end of the second inductor is grounded;
the second end of the fourth capacitor is connected with the source electrode of the seventh MOS tube and the source electrode of the eighth MOS tube;
the drain electrode of the seventh MOS tube is connected with the signal output end, and the grid electrode of the seventh MOS tube is connected with the positive electrode of the power supply;
and the drain electrode of the eighth MOS tube is grounded, and the grid electrode is connected with the negative electrode of the power supply.
5. The six bit wideband digital phase shifter of claim 2, wherein the three-order high-low pass structure further comprises:
a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;
the grid electrode of the first MOS tube is connected with the negative electrode of the power supply through the first resistor;
the grid electrode of the second MOS tube is connected with the positive electrode of the power supply through the second resistor;
the grid electrode of the third MOS tube is connected with the negative electrode of the power supply through the third resistor;
the grid electrode of the fourth MOS tube is connected with the positive electrode of the power supply through the fourth resistor;
the grid electrode of the fifth MOS tube is connected with the positive electrode of the power supply through the fifth resistor;
the grid electrode of the sixth MOS tube is connected with the negative electrode of the power supply through the sixth resistor;
the grid electrode of the seventh MOS tube is connected with the positive electrode of the power supply through the seventh resistor;
and the grid electrode of the eighth MOS tube is connected with the negative electrode of the power supply through the eighth resistor.
6. The six bit wideband digital phase shifter of claim 2, wherein the capacitance and inductance values corresponding to the desired insertion phase are determined from the desired insertion phase, the center angular frequency, and the characteristic impedance when the center angular frequency satisfies the impedance match.
7. The six-bit wideband digital phase shifter of claim 1, wherein the phase shift bit map of the third order high-low pass structure is generated based on a circuit diagram of the third order high-low pass structure.
8. The six-bit wideband digital phase shifter of claim 1, wherein the phase shift pattern of the 180 ° phase shift cell combination structure is composed of phase shift patterns of two three-order high-low pass structures.
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| CN102055428A (en) * | 2010-11-24 | 2011-05-11 | 南京理工大学 | Microwave and millimeter wave wideband 5bit singlechip integrated digital phase shifter |
| CN103281047A (en) * | 2013-04-25 | 2013-09-04 | 重庆西南集成电路设计有限责任公司 | 180-degree broadband phase shifter on passive chip |
| CN109239673A (en) * | 2018-09-29 | 2019-01-18 | 扬州海科电子科技有限公司 | A kind of width phase control multifunction chip of 6-18GHz |
| CN113162581A (en) * | 2021-03-22 | 2021-07-23 | 中国电子科技集团公司第十三研究所 | Broadband digital phase shifter based on GaN HEMT device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055428A (en) * | 2010-11-24 | 2011-05-11 | 南京理工大学 | Microwave and millimeter wave wideband 5bit singlechip integrated digital phase shifter |
| CN103281047A (en) * | 2013-04-25 | 2013-09-04 | 重庆西南集成电路设计有限责任公司 | 180-degree broadband phase shifter on passive chip |
| CN109239673A (en) * | 2018-09-29 | 2019-01-18 | 扬州海科电子科技有限公司 | A kind of width phase control multifunction chip of 6-18GHz |
| CN113162581A (en) * | 2021-03-22 | 2021-07-23 | 中国电子科技集团公司第十三研究所 | Broadband digital phase shifter based on GaN HEMT device |
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