CN109239673A - A kind of width phase control multifunction chip of 6-18GHz - Google Patents
A kind of width phase control multifunction chip of 6-18GHz Download PDFInfo
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- CN109239673A CN109239673A CN201811150111.5A CN201811150111A CN109239673A CN 109239673 A CN109239673 A CN 109239673A CN 201811150111 A CN201811150111 A CN 201811150111A CN 109239673 A CN109239673 A CN 109239673A
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Abstract
The invention discloses a kind of 6-18GHz multifunction chips, including the first single-pole double-throw switch (SPDT), numerical-control attenuator, the first driving amplifier, digital phase shifter, the second driving amplifier, the second single-pole double-throw switch (SPDT), third single-pole double-throw switch (SPDT), reception input terminal, transmitting output end and transmitting-receiving common end；Wherein numerical-control attenuator, the first driving amplifier, digital phase shifter and the second driving amplifier sequentially cascade, and numerical-control attenuator connects the common of the first single-pole double-throw switch (SPDT), and the second driving amplifier connects the common of the second single-pole double-throw switch (SPDT)；The first contact connection of first single-pole double-throw switch (SPDT) receives input terminal, and the second contact connects the second contact of third single-pole double-throw switch (SPDT)；With transmitting output end, the first contact connects the first contact of third single-pole double-throw switch (SPDT) for second touching connection of the second single-pole double-throw switch (SPDT)；The common connection transmitting-receiving common end of third single-pole double-throw switch (SPDT).The present invention has the advantages that integrated level is high, assembly is simple, consistency is good.
Description
Technical field
The invention belongs to microwave and millimeter wave width phase control chip technology field, the width phase controls of especially a kind of 6-18GHz
Multifunction chip.
Background technique
With extensive use of the Connectors for Active Phased Array Radar in electronics investigation and electronic countermeasure, transmitting-receiving (T/R) component is made
For the core of phased-array technique, determine whether entire phased array system is up to standard.Typical phased array is to utilize electrometer
Calculation machine controls phase shifter, changes the phase distribution on antenna aperature, to realize wave beam in spacescan, due to the working mechanism,
Width phase control is the important component of T/R component.
Width phase control function is still realized in traditional T/R component using independent digital phase shifter and numerical-control attenuator,
On the one hand this method is assembled complex, on the other hand additional assembly is unfavorable for the one of digital phase shifter and numerical-control attenuator
Cause property, directly affects the performance of entire T/R component.
Summary of the invention
The purpose of the present invention is to provide a kind of integrated numerical-control phase shift simultaneously, numerical control attenuation, amplification and transmitting-receiving switching function
The width phase control multifunction chip of the 6-18GHz of energy improves chip to mitigate assembly work amount when T/R component batch produces
Reliability and consistency.
The technical solution achieved the object of the present invention are as follows: a kind of width phase control multifunction chip of 6-18GHz, including first
Single-pole double-throw switch (SPDT), numerical-control attenuator, the first driving amplifier, digital phase shifter, the second driving amplifier, the second single-pole double throw
Switch, third single-pole double-throw switch (SPDT) receive input terminal, transmitting output end and transmitting-receiving common end；
The reception input terminal is connect with the first contact of the first single-pole double-throw switch (SPDT), the first single-pole double-throw switch (SPDT) it is public
The connection of the input terminal of contact and numerical-control attenuator；The output end of numerical-control attenuator is connect with the input terminal of the first driving amplifier,
The output end of first driving amplifier and the input terminal of digital phase shifter connect；The output end of digital phase shifter is put with the second driving
The input terminal connection of big device, the output end of the second driving amplifier are connect with the common of the second single-pole double-throw switch (SPDT)；Second
Second contact of single-pole double-throw switch (SPDT) is connect with transmitting output end, and the first contact of the second single-pole double-throw switch (SPDT) and third hilted broadsword are double
First contact of throw switch connects；The common of third single-pole double-throw switch (SPDT) is connect with transmitting-receiving common end, third single-pole double throw
Second contact of switch is connect with the second contact of the first single-pole double-throw switch (SPDT).
Further, first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT) and third single-pole double-throw switch (SPDT) structure
It is identical, it is all made of 4 N-channel MOS FET and is gone here and there and cascaded, realize and the on-off of signal is controlled, specifically:
The drain electrode of first MOSFET is connect with the drain electrode of the 2nd MOSFET and the tie point is common, the first MOSFET
Source electrode on the one hand connect the second contact, on the other hand connect the 3rd MOSFET drain electrode, the 3rd MOSFET source electrode ground connection；The
On the one hand drain electrode that the source electrode of two MOSFET connects the first contact, on the other hand connects the 4th MOSFET, the source of the 4th MOSFET
Pole ground connection；
First MOSFET, the 4th MOSFET grid voltage be Vg1, the grid voltage of the 2nd MOSFET, the 3rd MOSFET
It is the control level of reverse phase each other for Vg2, Vg1 and Vg2, Vg1 is high level, and when Vg2 is low level, the second contact is opened；Phase
Instead, Vg1 is low level, and when Vg2 is high level, the first contact is opened.
Further, the numerical-control attenuator use switch-resistance method, have 6 numerical control attenuation positions, be respectively 0.5dB,
1dB, 2dB, 4dB, 8dB and 16dB；Wherein 0.5dB and 1dB uses T-type attenuating structure, and 2dB, 4dB and 8dB are using π type decaying knot
Structure, 16dB are realized using two π type attenuating structure series connection.
Further, first driving amplifier and the second driving amplifier use identical structure, are all made of two-stage and put
Big device cascade, first order amplifier are matched using optimum noise, and introduce series inductance in source, so that noise matching and input
Standing wave matching is close；Second level amplifier uses LRC Shunt negative feedback structure；
When choosing dc point, first order amplifier operating point is selected in the 30% of saturation current, second level amplifier
Operating point is selected in the 50% of saturation current.
Further, the digital phase shifter uses high-pass and low-pass filter type topological structure, has 6 displacement phases, is respectively
5.625 °, 11.25 °, 22.5 °, 45 °, 90 ° and 180 °, thus realize 5.625 ° -360 ° of phase shift range, wherein 5.625 °,
11.25 and 22.5 ° use shunt inductance type structure, and other jayrators lead to structure using π/T hybrid high/low.
Further, the circuit of the T-type attenuating structure specifically:
The drain electrode connection signal link of 5th MOSFET, source electrode are connected to ground, grid connection control level Q1 by resistance；
When Q1 is high level, signal link parallel resistance to ground, work is in attenuation state, and when Q1 is low level, signal link is same
Resistance R is disconnected, and is worked in pass-through state.
Further, the π type attenuating structure circuit specifically:
Drain electrode connection π output end, the source electrode of 6th MOSFET connects π input terminal；The drain electrode connection first of 7th MOSFET
One end of resistance, source electrode ground connection；One end of the drain electrode connection 3rd resistor of 8th MOSFET, source electrode ground connection；The one of second resistance
The other end and π input terminal of end connection first resistor, the other end and π of the other end connection 3rd resistor of second resistance
Output end, wherein second resistance is equal with the resistance value of 3rd resistor；
The gate control levels of 6th MOSFET are that the grid voltage of Q2, the 7th MOSFET and the 8th MOSFET areIts
Middle Q2 andReverse phase；When Q2 is high level,For low level, the 6th MOSFET conducting, the 7th MOSFET and the 8th
MOSFET shutdown, π input terminal are directly connected to π output end, are worked in pass-through state；When Q2 is low level,For high electricity
Flat, the 6th MOSFET shutdown, the 7th MOSFET and the 8th MOSFET conducting, first resistor R1 and 3rd resistor R3 are connected to ground,
π type attenuation network is formed with second resistance R2, is worked in attenuation state.
Further, first driving amplifier and the second driving amplifier use identical structure, and physical circuit is as follows:
Output of the 4th resistance of source series and the tenth inductance of first pHEMT pipe to ground, drain electrode as the first pHEMT pipe
End, grid are as circuit input end；The source electrode ground connection of 2nd pHEMT pipe, the 11st inductance of drain series to circuit output end, electricity
Output end the 11st capacitor in parallel in road is to ground, another aspect circuit output end series connection the 12nd inductance, the 5th resistance and the tenth
The grid of two capacitors to the 2nd pHEMT pipe, the input terminal as the 2nd pHEMT pipe；First pHEMT pipe and the 2nd pHEMT pipe
Cascade passes through the 13rd inductance of connecting between the output end of the first pHEMT pipe and the input terminal of the 2nd pHEMT pipe, and parallel connection
13rd capacitor is realized to ground.
Further, the shunt inductance type structure, specifically:
The drain electrode of 9th MOSFET and source electrode are the same as the 7th inductance in parallel, drain electrode connection circuit input end, source electrode connection circuit
Output end, grid connection control level Q3；When Q3 is high level, the 9th MOSFET conducting, input terminal and output end directly connect
It connects, works in pass-through state；When Q3 is low level, the 9th MOSFET shutdown, input terminal the 7th inductance of series connection to output end, shape
At low-pass network, work in delayed phase state.
Further, π/T hybrid high/low leads to structure, specifically:
It being grounded in the source electrode of circuit input end, the tenth MOSFET, the source electrode for same 11st MOSFET that drains is connected, and the 11st
The drain electrode of MOSFET is connected with the drain electrode of the 12nd MOSFET, and as circuit input end, and the source electrode of the 12nd MOSFET is the same as the
13 MOSFET drain electrode is connected, the source electrode ground connection of the 13rd MOSFET；In circuit output end, the 14th MOSFET source is grounded,
Drain electrode is connected with the source electrode of the 15th MOSFET, and the drain electrode of the 15th MOSFET is connected with the drain electrode of the 16th MOSFET, and makees
Source electrode for circuit output end, the 16th MOSFET is connected with the 17th MOSFET drain electrode, the source electrode ground connection of the 17th MOSFET；
7th capacitor, the 8th capacitor and the 8th inductance form π type low-pass network, and with the drain electrode and the 14th of the tenth MOSFET
The drain series of MOSFET；9th capacitor, the tenth capacitor and the 9th inductance form T-type high pass network, and with the 13rd
The drain electrode of MOSFET and the drain series of the 17th MOSFET；
Tenth MOSFET, the 12nd MOSFET, the 14th MOSFET and the 16th MOSFET gate control levels Q4, the
11 MOSFET, the 13rd MOSFET, the 15th MOSFET and the 17th MOSFET gate control levelsWherein Q4 andReverse phase；When Q4 is high level,For low level, the tenth MOSFET, the 12nd MOSFET, the 14th MOSFET and
16 MOSFET conducting, the 11st MOSFET, the 13rd MOSFET, the 15th MOSFET and the 17th MOSFET shutdown are defeated
Enter end and connected with output end by T-type high pass network, is worked in phase Lead conditions；When Q4 is low level,For high electricity
It is flat, the 11st MOSFET, the 13rd MOSFET, the 15th MOSFET and the 17th MOSFET conducting, the tenth MOSFET, the tenth
Two MOSFET, the 14th MOSFET and the 16th MOSFET shutdown, circuit input end and output end are connected by π type low-pass network
It connects, works in delayed phase state.
Compared with prior art, the present invention its remarkable advantage is: (1) by the numerical control phase shift of 6-18GHz frequency band signals, number
Control decaying, amplification and transmitting-receiving switching are integrated on a chip, simplify assembly work amount when T/R component batch produces；(2) it mentions
High reliability, has the advantages that integrated level height, consistency are good.
Detailed description of the invention
Fig. 1 is the electrical block diagram of 6-18GHz multifunction chip of the present invention.
Fig. 2 is the electrical block diagram of single-pole double-throw switch (SPDT) in the present invention.
Fig. 3 is the electrical block diagram of numerical-control attenuator in the present invention.
Fig. 4 is the topological structure schematic diagram of decaying position in the present invention, wherein (a) is the topological structure signal of simple T decaying
Figure is (b) the topological structure schematic diagram of simple π type decaying.
Fig. 5 is the topological structure schematic diagram of driving amplifier in the present invention.
Fig. 6 is the electrical block diagram of digital phase shifter in the present invention.
Fig. 7 is the topological structure schematic diagram of jayrator high-pass and low-pass filter in the present invention, wherein (a) is that π type jayrator is high
The topological structure schematic diagram of low-pass filter is (b) the topological structure schematic diagram of T-type jayrator high-pass and low-pass filter.
Fig. 8 is the topological structure schematic diagram of the jayrator high-pass and low-pass filter simplified in the present invention, wherein (a) is electricity in parallel
The topological structure schematic diagram of sense type jayrator high-pass and low-pass filter, (b) opening up for π/T mixed type type jayrator high-pass and low-pass filter
Flutter structural schematic diagram.
Fig. 9 is the appearance schematic diagram of 6-18GHz multifunction chip of the present invention.
Specific embodiment
The present invention will be further described in the following with reference to the drawings and specific embodiments.
The width phase control multifunction chip of 6-18GHz of the present invention, including the first single-pole double-throw switch (SPDT), numerical-control attenuator,
One driving amplifier, the second driving amplifier, the second single-pole double-throw switch (SPDT), third single-pole double-throw switch (SPDT), receives digital phase shifter
Input terminal, transmitting output end and transmitting-receiving common end；
The reception input terminal is connect with the first contact of the first single-pole double-throw switch (SPDT), the first single-pole double-throw switch (SPDT) it is public
The connection of the input terminal of contact and numerical-control attenuator；The output end of numerical-control attenuator is connect with the input terminal of the first driving amplifier,
The output end of first driving amplifier and the input terminal of digital phase shifter connect；The output end of digital phase shifter is put with the second driving
The input terminal connection of big device, the output end of the second driving amplifier are connect with the common of the second single-pole double-throw switch (SPDT)；Second
Second contact of single-pole double-throw switch (SPDT) is connect with transmitting output end, and the first contact of the second single-pole double-throw switch (SPDT) and third hilted broadsword are double
First contact of throw switch connects；The common of third single-pole double-throw switch (SPDT) is connect with transmitting-receiving common end, third single-pole double throw
Second contact of switch is connect with the second contact of the first single-pole double-throw switch (SPDT).
Further, first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT) and third single-pole double-throw switch (SPDT) structure
It is identical, it is all made of 4 N-channel MOS FET and is gone here and there and cascaded, realize and the on-off of signal is controlled, specifically:
The drain electrode of first MOSFETM1 connect with the drain electrode of the 2nd MOSFETM2 and the tie point be common, first
On the one hand drain electrode that the source electrode of MOSFETM1 connects the second contact, on the other hand connects the 3rd MOSFETM3, the 3rd MOSFETM3
Source electrode ground connection；On the one hand leakage that the source electrode of 2nd MOSFETM2 connects the first contact, on the other hand connects the 4th MOSFETM4
Pole, the source electrode ground connection of the 4th MOSFETM4；
First MOSFETM1, the 4th MOSFETM4 grid voltage be Vg1, the 2nd MOSFETM2, the 3rd MOSFETM3
Grid voltage is the control level that Vg2, Vg1 and Vg2 are reverse phase each other, and Vg1 is high level, when Vg2 is low level, the second contact
It opens；On the contrary, Vg1 is low level, when Vg2 is high level, the first contact is opened.
Further, the numerical-control attenuator use switch-resistance method, have 6 numerical control attenuation positions, be respectively 0.5dB,
1dB, 2dB, 4dB, 8dB and 16dB；Wherein 0.5dB and 1dB uses T-type attenuating structure, and 2dB, 4dB and 8dB are using π type decaying knot
Structure, 16dB are realized using two π type attenuating structure series connection.
The circuit of the T-type attenuating structure specifically:
The drain electrode connection signal link of 5th MOSFETM5, source electrode are connected to ground, grid connection control level by resistance R
Q1；When Q1 is high level, signal link parallel resistance R to ground, work is in attenuation state, when Q1 is low level, signal chains
Road is disconnected with resistance R, is worked in pass-through state.
π type attenuating structure circuit specifically:
Drain electrode connection π output end, the source electrode of 6th MOSFETM6 connects π input terminal；The drain electrode of 7th MOSFETM7 connects
One end of first resistor R1, source electrode ground connection；One end of the drain electrode connection 3rd resistor R3 of 8th MOSFETM8, source electrode ground connection；The
The other end and π input terminal of one end connection first resistor R1 of two resistance R2, the other end connection third electricity of second resistance R2
Hinder the other end of R3 and the output end of π, wherein second resistance R2 is equal with the resistance value of 3rd resistor R3；
The gate control levels of 6th MOSFETM6 are that the grid voltage of Q2, the 7th MOSFETM7 and the 8th MOSFETM8 areWherein Q2 andReverse phase；When Q2 is high level,For low level, the 6th MOSFETM6 conducting, the 7th MOSFETM7
It is turned off with the 8th MOSFETM8, π input terminal is directly connected to π output end, is worked in pass-through state；When Q2 is low level,For high level, the 6th MOSFETM6 shutdown, the 7th MOSFETM7 and the 8th MOSFETM8 conducting, first resistor R1 and third
Resistance R3 is connected to ground, forms π type attenuation network with second resistance R2, works in attenuation state.
On the topological structure that circuit is realized, for small attenuation since structure is simple, impedance is poor, and it is defeated to be not interposing at input
Outlet.
Further, first driving amplifier and the second driving amplifier use identical structure, are all made of two-stage and put
Big device cascade, first order amplifier are matched using optimum noise, and introduce series inductance in source, so that noise matching and input
Standing wave matching is close；Second level amplifier uses LRC Shunt negative feedback structure；
When choosing dc point, first order amplifier operating point is selected in the 30% of saturation current, second level amplifier
Operating point is selected in the 50% of saturation current.
First driving amplifier and the second driving amplifier use identical structure, and physical circuit is as follows:
Source series the 4th resistance Rs and the tenth inductance Ls of first pHEMT pipe D1 is managed to ground, drain electrode as the first pHEMT
The output end of D1, grid are as circuit input end；The source electrode ground connection of 2nd pHEMT pipe D2, the 11st inductance Ld of drain series are arrived
Circuit output end, circuit output end the 11st capacitor Cout of parallel connection to ground, another aspect circuit output end the 12nd inductance of series connection
LFB, the 5th resistance RFB and the 12nd capacitor CFBInput to the grid of the 2nd pHEMT pipe D2, as the 2nd pHEMT pipe D2
End；The cascade of first pHEMT pipe D1 and the 2nd pHEMT pipe D2 are managed by the output end of the first pHEMT pipe D1 and the 2nd pHEMT
Connect the 13rd inductance Lin between the input terminal of D2, and the 13rd capacitor Cin of parallel connection is realized to ground.
Further, the digital phase shifter uses high-pass and low-pass filter type topological structure, has 6 displacement phases, is respectively
5.625 °, 11.25 °, 22.5 °, 45 °, 90 ° and 180 °, thus realize 5.625 ° -360 ° of phase shift range, wherein 5.625 °,
11.25 and 22.5 ° use shunt inductance type structure, and other jayrators lead to structure using π/T hybrid high/low, few as far as possible to use
Inductance, to reduce chip size.
The shunt inductance type structure, specifically:
The drain electrode of 9th MOSFETM9 and source electrode are in parallel with the 7th inductance L7, drain electrode connection circuit input end, source electrode connection
Circuit output end, grid connection control level Q3；When Q3 is high level, the 9th MOSFETM9 is connected, input terminal and output end
It is directly connected to, works in pass-through state；When Q3 is low level, the 9th MOSFETM9 shutdown, the 7th inductance L7 of input terminal series connection
To output end, low-pass network is formed, is worked in delayed phase state.
π/T hybrid high/low leads to structure, specifically:
It being grounded in the source electrode of circuit input end, the tenth MOSFETM10, the source electrode for same 11st MOSFETM11 that drains is connected,
The drain electrode of 11st MOSFETM11 is connected with the drain electrode of the 12nd MOSFETM12, and as circuit input end, and the 12nd
The source electrode of MOSFETM12 is connected with the 13rd MOSFETM13 drain electrode, the source electrode ground connection of the 13rd MOSFETM13；In circuit output
The source electrode at end, the 14th MOSFETM14 source electrode ground connection, same 15th MOSFETM15 that drains is connected, the 15th MOSFETM15's
Drain electrode is connected with the drain electrode of the 16th MOSFETM16, and as circuit output end, the source electrode of the 16th MOSFETM16 is the same as the tenth
Seven MOSFETM17 drain electrode is connected, the source electrode ground connection of the 17th MOSFETM17；7th capacitor C7, the 8th capacitor C8 and the 8th electricity
Feel L8 and form π type low-pass network, and with the drain electrode of the tenth MOSFETM10 and the drain series of the 14th MOSFETM14；9th electricity
Hold C9, the tenth capacitor C10 and the 9th inductance L9 and form T-type high pass network, and with the drain electrode and the tenth of the 13rd MOSFETM13
The drain series of seven MOSFETM17；
Tenth MOSFETM10, the 12nd MOSFETM12, the 14th MOSFETM14 and the 16th MOSFETM16 grid
Control level Q4, the 11st MOSFETM11, the 13rd MOSFETM13, the 15th MOSFETM15 and the 17th MOSFETM17
Gate control levelsWherein Q4 andReverse phase；When Q4 is high level,For low level, the tenth MOSFETM10,
12 MOSFETM12, the 14th MOSFETM14 and the 16th MOSFETM16 conducting, the 11st MOSFETM11, the 13rd
MOSFETM13, the 15th MOSFETM15 and the 17th MOSFETM17 shutdown, input terminal and output end pass through T-type high pass net
Network connection, works in phase Lead conditions；When Q4 is low level,For high level, the 11st MOSFETM11, the 13rd
MOSFETM13, the 15th MOSFETM15 and the 17th MOSFETM17 conducting, the tenth MOSFETM10, the 12nd
MOSFETM12, the 14th MOSFETM14 and the 16th MOSFETM16 shutdown, circuit input end and output end pass through π type low pass
Network connection works in delayed phase state.
On the topological structure that circuit is realized, for low phase shift since structure is simple, impedance is poor, and it is defeated to be not interposing at input
Outlet.
The present invention will be further described in the following with reference to the drawings and specific embodiments.
Embodiment
As shown in Figure 1, a kind of 6-18GHz multifunction chip, including the first single-pole double-throw switch (SPDT), numerical-control attenuator, first
Driving amplifier, digital phase shifter, the second driving amplifier, the second single-pole double-throw switch (SPDT), third single-pole double-throw switch (SPDT), reception are defeated
Enter end, transmitting output end and transmitting-receiving common end；
It is described receive input terminal with the first single-pole double-throw switch (SPDT) the first contact connect, the first single-pole double-throw switch (SPDT) it is public
Contact is connected with the input terminal of numerical-control attenuator；The output end of numerical-control attenuator is connected with the input terminal of the first driving amplifier,
The output end of first driving amplifier is connected with the input terminal of digital phase shifter；The output end of digital phase shifter is put with the second driving
The output end of the input terminal connection of big device, the second driving amplifier is connected with the common of the second single-pole double-throw switch (SPDT)；Second
With transmitting output end connection, the first contact of the second single-pole double-throw switch (SPDT) is double with third hilted broadsword for second contact of single-pole double-throw switch (SPDT)
First contact of throw switch connects；The common of third single-pole double-throw switch (SPDT) is the same as the connection of transmitting-receiving common end, third single-pole double throw
Second contact of switch is connected with the second contact of the first single-pole double-throw switch (SPDT).,
Further, first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT) and third single-pole double-throw switch (SPDT) are adopted
It with same design method, is gone here and there and is cascaded using MOSFET, realized and the on-off of signal is controlled；
In conjunction with Fig. 2, the first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT) and third single-pole double-throw switch (SPDT) use N-channel
Transistor provides low channel resistance, reduces insertion loss.The circuit is by two series/parallel topology formations, wherein series connection is brilliant
Body pipe is main switching transistor, is incorporated to parallel transistor and is isolated with further improvement；Single-pole double-throw switch (SPDT) is a three port devices
Part is common, the first contact and the second contact respectively；Vg1 and Vg2 is the control level of reverse phase each other, and Vg1 is high electricity
Flat, when Vg2 is low level, the second contact is opened；On the contrary, Vg1 is low level, when Vg2 is high level, the first contact is opened.
Further, the numerical-control attenuator uses switch-resistance method, there is 6 numerical control attenuation positions, stepping 0.5dB；
In conjunction with Fig. 3, numerical-control attenuator is made of 6 decaying positions, is 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB respectively,
Wherein 0.5dB and 1dB is small attenuation decaying position, and others are big attenuation decaying position.In order to reduce additional phase when decaying
It moves, using switch-resistance method, i.e., resistance element independent is selected by switching.As shown in figure 4, the electricity of each decaying position
Road includes two kinds of topological structures, and the symmetry of both structures improves the anti-process fluctuation and environment resistant temperature of numerical-control attenuator
Spend variability.Wherein 0.5dB and 1dB selects such as simple T-type attenuating structure of Fig. 4 (a)~(b), and 2dB, 4dB and 8dB are selected such as
The π type attenuating structure of Fig. 4,16dB select two π type attenuating structure series connection to realize.Since small attenuation decaying bit architecture is simple,
Insertion loss is small, and effect is undesirable in terms of impedance, is easy to be influenced by bonding gold wire length, so being not interposing at input
Output end.Resistance on each decaying position is all made of film resistor.
Further, first driving amplifier and the second driving amplifier use same design method, are all made of two
Grade amplifier cascade, first order amplifier are matched using optimum noise, and introduce series inductance in source；Second level amplifier is adopted
With LRC Shunt negative feedback structure；
In conjunction with Fig. 5, driving amplifier is using two-stage amplification, automatic biasing structure.First order amplification, for simultaneously to noise system
Number and input standing wave matched, active device source introduce serial Feedback inductance so that the input impedance of device with
Output loading and serial Feedback change, and optimum noise impedance is dependent only on serial Feedback part, controls the inductance of source
Amount and grid width, so that ΓoptAnd ΓsClose to the matching that can meet simultaneously to noise coefficient and input standing wave.Second level amplification,
Using LRC Shunt negative feedback structure, input and output matching on the one hand can be improved, and the gain by reducing low frequency is steady to improve
Fixed degree；On the other hand, a part of itself is offset by negative feedback network by the non-linear distortion signal that exports amplifier
It is non-linear, and then reach the requirement for improving Amplifier linearity；Meanwhile negative feedback structure also reduces amplifier performance to technique
The susceptibility of fluctuation.When choosing dc point, first order amplifier considers optimum noise matching, and operating point is selected in saturation electricity
The 30% of stream, second level amplifier consider best power matching, and operating point is selected in the 50% of saturation current.Γopt、ΓsIt is respectively
Best source reflection coefficient, transistor input terminal source reflection coefficient when amplifier is matched by Minimum noises coefficients.
Further, the digital phase shifter uses high-pass and low-pass filter type topological structure, has 6 displacement phases, stepping is
5.625°；
In conjunction with Fig. 6, digital phase shifter is made of 6 displacement phases, is 5.625 ° respectively, 11.25 °, 22.5 °, 45 °, 90 ° and
180°.Since bandwidth of operation is 6-18GHz, while there is lesser additional amplitude to change, each jayrator uses high/low flow-through
Filter construction.When signal passes through high-pass filter, since high-pass filter frequency domain characteristic is there are zero point, phase is super
Before；When signal passes through low-pass filter, low-pass filter frequency domain characteristic is there are pole, therefore delayed phase；It is cut by switch
High and low pass filter path is changed, phase shift can be realized, as shown in Fig. 7 (a)~(b), wherein (a) is the high low-pass filtering of π type jayrator
The topological structure schematic diagram of device is (b) the topological structure schematic diagram of T-type jayrator high-pass and low-pass filter；Simultaneously because both
The frequency response of filter is different, and the leading phase of high-pass filter is increased with frequency to be reduced, the lagging phase of low-pass filter
Increase with the raising of frequency, the phase change of the two compensates mutually, therefore the structure can be realized on wider frequency band
Flat phase-frequency response is suitable for wide-band applications.Since on-chip spiral inductor size is larger, so using mixed type
π/T structure reduces the use of inductance.According to the size of jayrator, using two kinds of circuit structures as shown in Fig. 8 (a)~(b),
Wherein 5.625 °, 11.25 and 22.5 ° of high lowpass structures of shunt inductance type using Fig. 8 (a), other jayrators use Fig. 8
(b) π/T hybrid high/low leads to structure.Since the structure of low jayrator is simple, insertion loss is small, the effect in terms of impedance
It is undesirable, it is easy to be influenced by bonding gold wire length, so being not interposing at input/output terminal.
A kind of 6-18GHz multifunction chip of the present invention, maximum noise coefficient are no more than 11dB；Receive maximum input 1dB function
Rate is not less than 14dBm；It receives and dispatches gain fluctuation and is not more than 3dB；Numerical-controlled attenuation precision is no more than 1.5dB, and additive phase variation does not surpass
Cross ± 7 °；Numerical control phase shifting accuracy is not more than 7 °, and additional amplitude variation is no more than 0.7dB；Final chip area be 6.6mm ×
4.6mm, as shown in Figure 9.Entire chip is integrated on a single die by multiple unifunctional circuits, has integrated level height, assembly letter
The advantage single, consistency is good, overall performance is excellent, can be advantageously applied to the production of high-volume T/R component.
Claims (10)
1. the width phase control multifunction chip of 6-18GHz a kind of, which is characterized in that decline including the first single-pole double-throw switch (SPDT), numerical control
Subtract device, the first driving amplifier, digital phase shifter, the second driving amplifier, the second single-pole double-throw switch (SPDT), third single-pole double throw to open
It closes, receive input terminal, transmitting output end and transmitting-receiving common end；
The reception input terminal is connect with the first contact of the first single-pole double-throw switch (SPDT), the common of the first single-pole double-throw switch (SPDT)
It is connect with the input terminal of numerical-control attenuator；The output end of numerical-control attenuator is connect with the input terminal of the first driving amplifier, and first
The output end of driving amplifier and the input terminal of digital phase shifter connect；The output end of digital phase shifter and the second driving amplifier
Input terminal connection, the output end of the second driving amplifier connect with the common of the second single-pole double-throw switch (SPDT)；Second hilted broadsword
Second contact of commutator is connect with transmitting output end, and the first contact and the third single-pole double throw of the second single-pole double-throw switch (SPDT) are opened
The the first contact connection closed；The common of third single-pole double-throw switch (SPDT) is connect with transmitting-receiving common end, third single-pole double-throw switch (SPDT)
The second contact connect with the second contact of the first single-pole double-throw switch (SPDT).
2. the width phase control multifunction chip of 6-18GHz according to claim 1, which is characterized in that first hilted broadsword
Commutator, the second single-pole double-throw switch (SPDT) are identical with third single-pole double-throw switch (SPDT) structure, are all made of 4 N-channel MOS FET and carry out
It goes here and there and cascades, realize and the on-off of signal is controlled, specifically:
The drain electrode of first MOSFET (M1) connect with the drain electrode of the 2nd MOSFET (M2) and the tie point be common, first
On the one hand drain electrode that the source electrode of MOSFET (M1) connects the second contact, on the other hand connects the 3rd MOSFET (M3), third
The source electrode of MOSFET (M3) is grounded；On the one hand the source electrode of 2nd MOSFET (M2) connects the first contact, on the other hand connects the 4th
The drain electrode of MOSFET (M4), the source electrode ground connection of the 4th MOSFET (M4)；
First MOSFET (M1), the 4th MOSFET (M4) grid voltage be Vg1, the 2nd MOSFET (M2), the 3rd MOSFET
(M3) grid voltage is the control level that Vg2, Vg1 and Vg2 are reverse phase each other, and Vg1 is high level, when Vg2 is low level, the
It opens two contacts；On the contrary, Vg1 is low level, when Vg2 is high level, the first contact is opened.
3. the width phase control multifunction chip of 6-18GHz according to claim 1, which is characterized in that the numerical control attenuation
Device uses switch-resistance method, has 6 numerical control attenuation positions, is 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB respectively；Wherein 0.5dB
T-type attenuating structure is used with 1dB, 2dB, 4dB and 8dB use π type attenuating structure, and 16dB is using two π type attenuating structure series connection
It realizes.
4. the width phase control multifunction chip of 6-18GHz according to claim 1, which is characterized in that first driving
Amplifier and the second driving amplifier use identical structure, are all made of dual-stage amplifier cascade, first order amplifier is using best
Noise matching, and series inductance is introduced in source, so that noise matching and input standing wave matching are close；Second level amplifier uses
LRC Shunt negative feedback structure；
When choosing dc point, first order amplifier operating point is selected in the 30% of saturation current, second level amplifier operation
Point is selected in the 50% of saturation current.
5. the width phase control multifunction chip of 6-18GHz according to claim 1, which is characterized in that the numerical control phase shift
Device use high-pass and low-pass filter type topological structure, have 6 displacement phases, be respectively 5.625 °, 11.25 °, 22.5 °, 45 °, 90 ° and
180 °, thus realize 5.625 ° -360 ° of phase shift range, wherein 5.625 °, 11.25 and 22.5 ° use shunt inductance type structure,
Other jayrators lead to structure using π/T hybrid high/low.
6. the width phase control multifunction chip of 6-18GHz according to claim 3, which is characterized in that the T-type decaying knot
The circuit of structure specifically:
The drain electrode connection signal link of 5th MOSFET (M5), source electrode are connected to ground, grid connection control level by resistance (R)
Q1；When Q1 is high level, signal link parallel resistance (R) to ground, work is in attenuation state, when Q1 is low level, signal
Link is disconnected with resistance R, is worked in pass-through state.
7. the width phase control multifunction chip of 6-18GHz according to claim 3, which is characterized in that the π type decaying knot
Structure circuit specifically:
Drain electrode connection π output end, the source electrode of 6th MOSFET (M6) connects π input terminal；The drain electrode of 7th MOSFET (M7) connects
One end of first resistor (R1), source electrode ground connection；One end of drain electrode connection 3rd resistor (R3) of 8th MOSFET (M8), source electrode connect
Ground；The other end and π input terminal of one end connection first resistor (R1) of second resistance (R2), the other end of second resistance (R2)
Connect the other end of 3rd resistor (R3) and the output end of π, wherein the resistance value phase of second resistance (R2) same to 3rd resistor (R3)
Deng；
The gate control levels of 6th MOSFET (M6) are Q2, the grid voltage of the 7th MOSFET (M7) and the 8th MOSFET (M8)
ForWherein Q2 andReverse phase；When Q2 is high level,For low level, the 6th MOSFET (M6) is connected, and the 7th
MOSFET (M7) and the 8th MOSFET (M8) shutdown, π input terminal are directly connected to π output end, are worked in pass-through state；When Q2 is
When low level,For high level, the 6th MOSFET (M6) shutdown, the 7th MOSFET (M7) and the 8th MOSFET (M8) are connected,
First resistor R1 and 3rd resistor R3 is connected to ground, forms π type attenuation network with second resistance R2, works in attenuation state.
8. the width phase control multifunction chip of 6-18GHz according to claim 4, which is characterized in that first driving
Amplifier and the second driving amplifier use identical structure, and physical circuit is as follows:
First pHEMT manages the 4th resistance (Rs) of source series of (D1) and the tenth inductance (Ls) arrives ground, drain electrode is used as the first pHEMT
The output end of (D1), grid are managed as circuit input end；2nd pHEMT manages the source electrode ground connection of (D2), the 11st electricity of drain series
Feel (Ld) and arrives circuit output end, circuit output end the 11st capacitor (Cout) of parallel connection to ground, the series connection of another aspect circuit output end
12nd inductance (LFB), the 5th resistance (RFB) and the 12nd capacitor (CFB) to the grid of the 2nd pHEMT pipe (D2), as the
Two pHEMT manage the input terminal of (D2)；First pHEMT manages the cascade of (D1) and the 2nd pHEMT pipe (D2), is managed by the first pHEMT
(D1) the 13rd inductance (Lin) of series connection between the input terminal of output end and the 2nd pHEMT pipe (D2), and the 13rd electricity of parallel connection
Hold (Cin) to realize to ground.
9. the width phase control multifunction chip of 6-18GHz according to claim 5, which is characterized in that the shunt inductance
Type structure, specifically:
The drain electrode of 9th MOSFET (M9) and source electrode are in parallel with the 7th inductance (L7), drain electrode connection circuit input end, source electrode connection
Circuit output end, grid connection control level Q3；When Q3 is high level, the 9th MOSFET (M9) is connected, input terminal and output
End is directly connected to, and is worked in pass-through state；When Q3 is low level, the 9th MOSFET (M9) shutdown, the 7th electricity of input terminal series connection
(L7) is felt to output end, is formed low-pass network, is worked in delayed phase state.
10. the width phase control multifunction chip of 6-18GHz according to claim 5, which is characterized in that π/T mixing
The high lowpass structures of type, specifically:
It being grounded in the source electrode of circuit input end, the tenth MOSFET (M10), the source electrode for same 11st MOSFET (M11) that drains is connected,
The drain electrode of 11st MOSFET (M11) is connected with the drain electrode of the 12nd MOSFET (M12), and as circuit input end, and the 12nd
The source electrode of MOSFET (M12) is connected with the 13rd MOSFET (M13) drain electrode, the source electrode ground connection of the 13rd MOSFET (M13)；In electricity
The source electrode of road output end, the 14th MOSFET (M14) source electrode ground connection, same 15th MOSFET (M15) that drains is connected, and the 15th
The drain electrode of MOSFET (M15) is connected with the drain electrode of the 16th MOSFET (M16), and as circuit output end, the 16th MOSFET
(M16) source electrode is connected with the 17th MOSFET (M17) drain electrode, the source electrode ground connection of the 17th MOSFET (M17)；7th capacitor
(C7), the 8th capacitor (C8) and the 8th inductance (L8) form π type low-pass network, and with the drain electrode of the tenth MOSFET (M10) and
The drain series of 14th MOSFET (M14)；9th capacitor (C9), the tenth capacitor (C10) and the 9th inductance (L9) form T-type
High pass network, and with the drain electrode of the 13rd MOSFET (M13) and the drain series of the 17th MOSFET (M17)；
Tenth MOSFET (M10), the 12nd MOSFET (M12), the 14th MOSFET (M14) and the 16th MOSFET (M16)
Gate control levels Q4, the 11st MOSFET (M11), the 13rd MOSFET (M13), the 15th MOSFET (M15) and the tenth
Seven MOSFET (M17) gate control levelsWherein Q4 andReverse phase；When Q4 is high level,For low level, the tenth
MOSFET (M10), the 12nd MOSFET (M12), the 14th MOSFET (M14) and the 16th MOSFET (M16) conducting, the 11st
MOSFET (M11), the 13rd MOSFET (M13), the 15th MOSFET (M15) and the 17th MOSFET (M17) shutdown, input
End is connected with output end by T-type high pass network, is worked in phase Lead conditions；When Q4 is low level,For high level,
11st MOSFET (M11), the 13rd MOSFET (M13), the 15th MOSFET (M15) and the 17th MOSFET (M17) are led
Logical, the tenth MOSFET (M10), the 12nd MOSFET (M12), the 14th MOSFET (M14) and the 16th MOSFET (M16) are closed
Disconnected, circuit input end is connected with output end by π type low-pass network, is worked in delayed phase state.
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| CN110324023A (en) * | 2019-06-13 | 2019-10-11 | 浙江大学 | A kind of low phase error digital pad of ultra wide band based on parallel capacitive compensation |
| CN111082773A (en) * | 2019-11-26 | 2020-04-28 | 扬州海科电子科技有限公司 | X/Ku wave band amplitude-phase control transceiver chip |
| CN112866158A (en) * | 2021-01-25 | 2021-05-28 | 凯迈（洛阳）测控有限公司 | Double-channel radio fuze simulator |
| CN112865830A (en) * | 2021-01-19 | 2021-05-28 | 无锡国芯微电子***有限公司 | Numerical control amplitude-phase multifunctional chip |
| CN113162647A (en) * | 2021-03-16 | 2021-07-23 | 复旦大学 | Broadband multifunctional transceiving component in phased array system |
| CN113162581A (en) * | 2021-03-22 | 2021-07-23 | 中国电子科技集团公司第十三研究所 | Broadband digital phase shifter based on GaN HEMT device |
| CN113541718A (en) * | 2021-06-15 | 2021-10-22 | 中国电子科技集团公司第十三研究所 | Four-channel multifunctional chip |
| CN113839659A (en) * | 2021-08-11 | 2021-12-24 | 中国电子科技集团公司第二十九研究所 | High-isolation single-pole double-throw switch circuit |
| CN113938138A (en) * | 2021-08-26 | 2022-01-14 | 北京遥测技术研究所 | X-frequency band 8-channel receiving chip of monolithic integrated switch network |
| CN114826230A (en) * | 2022-04-28 | 2022-07-29 | 电子科技大学 | Ultra-wideband single-pole multi-throw radio frequency switch applying reconfigurable filter network |
| CN117040577A (en) * | 2023-08-10 | 2023-11-10 | 上海安其威微电子科技有限公司 | Phased array receiving and transmitting system, device and method with feedback path |
| CN117375578A (en) * | 2023-12-07 | 2024-01-09 | 成都天成电科科技有限公司 | Six-bit broadband digital phase shifter |
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| CN110324023A (en) * | 2019-06-13 | 2019-10-11 | 浙江大学 | A kind of low phase error digital pad of ultra wide band based on parallel capacitive compensation |
| CN111082773A (en) * | 2019-11-26 | 2020-04-28 | 扬州海科电子科技有限公司 | X/Ku wave band amplitude-phase control transceiver chip |
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| CN112865830B (en) * | 2021-01-19 | 2022-02-18 | 无锡国芯微电子***有限公司 | Numerical control amplitude-phase multifunctional chip |
| CN112866158A (en) * | 2021-01-25 | 2021-05-28 | 凯迈（洛阳）测控有限公司 | Double-channel radio fuze simulator |
| CN113162647A (en) * | 2021-03-16 | 2021-07-23 | 复旦大学 | Broadband multifunctional transceiving component in phased array system |
| CN113162581A (en) * | 2021-03-22 | 2021-07-23 | 中国电子科技集团公司第十三研究所 | Broadband digital phase shifter based on GaN HEMT device |
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| CN113839659A (en) * | 2021-08-11 | 2021-12-24 | 中国电子科技集团公司第二十九研究所 | High-isolation single-pole double-throw switch circuit |
| CN113938138A (en) * | 2021-08-26 | 2022-01-14 | 北京遥测技术研究所 | X-frequency band 8-channel receiving chip of monolithic integrated switch network |
| CN114826230A (en) * | 2022-04-28 | 2022-07-29 | 电子科技大学 | Ultra-wideband single-pole multi-throw radio frequency switch applying reconfigurable filter network |
| CN117040577A (en) * | 2023-08-10 | 2023-11-10 | 上海安其威微电子科技有限公司 | Phased array receiving and transmitting system, device and method with feedback path |
| CN117040577B (en) * | 2023-08-10 | 2024-04-30 | 上海安其威微电子科技有限公司 | Phased array receiving and transmitting system, device and method with feedback path |
| CN117375578A (en) * | 2023-12-07 | 2024-01-09 | 成都天成电科科技有限公司 | Six-bit broadband digital phase shifter |
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