CN113408222B - File generation method and device, electronic equipment and storage medium - Google Patents
File generation method and device, electronic equipment and storage medium Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The disclosure provides a file generation method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring a general configuration file of a current chip subsystem and an information description file aiming at different chip subsystems; generating a condition constraint set for carrying out low-power design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power design stages on power consumption intention description files; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file; and filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information, and generating the power consumption intention file.
Description
Technical Field
The disclosure relates to the technical field of chip design, and in particular relates to a file generation method, a device, electronic equipment and a storage medium.
Background
With the continuous expansion of the chip design scale, the functions of the chip are more and more abundant. In order to meet the practical demands of the chip market, low power consumption design of chips is receiving more and more attention. The power consumption intention description may be introduced in the early stage of System on chip (SoC) development to support the whole process of low power consumption design, verification, integration, layout and wiring of the chip, and the like.
Generally, in order to describe the low-power architecture of the SoC, descriptions of various power domain types, power domain boundaries and power consumption scenes need to be provided for the chip, and then the power consumption intention file can be generated manually by a professional engineer. However, in the above manner of writing the power consumption intention file by the professional engineer, writing errors are likely to occur, and the generation efficiency is low.
Disclosure of Invention
In view of this, the present disclosure provides at least a file generating method, a device, an electronic apparatus, and a storage medium.
In a first aspect, the present disclosure provides a file generating method, including:
acquiring a general configuration file of a current chip subsystem and an information description file aiming at different chip subsystems;
generating a condition constraint set for carrying out low-power design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power design stages on power consumption intention description files; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file;
and filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information, and generating the power consumption intention file.
In the method, the general configuration file is analyzed to generate the condition constraint set for low-power-consumption design of the current chip subsystem, wherein the condition constraint set is used for indicating the requirements of different low-power-consumption design stages on the power-consumption intention description file, and the design requirements of the power-consumption intention description file of the current chip subsystem can be determined according to the condition constraint set; the information description file can be analyzed to generate power consumption strategy information for low-power consumption design of different chip subsystems; furthermore, the file template of the power consumption intention file can be filled based on the condition constraint set and the power consumption strategy information, the power consumption intention file is automatically generated, a professional engineer is not required to write the power consumption intention file, the generation efficiency of the power consumption intention file is improved, the occurrence of writing errors caused when the professional engineer writes the power consumption intention file can be relieved, and the accuracy of the power consumption intention file is improved.
In a possible implementation manner, the generating a power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the power consumption policy information includes:
determining target power consumption strategy information required for low-power consumption design of the current chip subsystem from the power consumption strategy information based on the condition constraint set;
And filling a file template of a power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file.
The power consumption strategy information can comprise power consumption strategy information required by low-power consumption design of different chip subsystems, so that when the low-power consumption design is carried out on the different chip subsystems, the power consumption strategy information matched with each chip subsystem can be directly determined from the analyzed power consumption strategy information, the information description file is not required to be analyzed for multiple times, the file generation efficiency is improved, meanwhile, the resource waste caused by analyzing the information description file for multiple times can be avoided, and the processing resources are saved.
In a possible implementation manner, the generating the power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the target power consumption policy information includes:
determining template content to be filled from the file template based on the condition constraint set and the target power consumption strategy information;
filling the template content by utilizing the target power consumption strategy information;
and generating the power consumption intention file based on the filled template content.
In the method, the file template can comprise a plurality of template contents, and each template content corresponds to different power consumption strategy information and/or condition constraint combination, so that the template content to be filled can be determined from the file template based on the condition constraint set and the target power consumption strategy information; filling the template content by utilizing the target power consumption strategy information; and generating a power consumption intention file based on the filled template content, wherein the power consumption intention file is simpler and more convenient in generation process and higher in efficiency.
In a possible implementation manner, the filling the template content with the target power consumption policy information includes:
performing target operation processing on the target power consumption strategy information based on the template content to generate processed target power consumption strategy information; the target operation processing comprises at least one of data format conversion, data statistics and data calculation;
and filling the template content by using the processed target power consumption strategy information.
In a possible implementation manner, the condition constraint set includes one or more of the following:
global macro variables, design types, tool types, mapping relationships for module instantiations, power lists.
In a possible implementation manner, the power consumption policy information includes one or more of the following information:
statement information of power domain, integration information of power domain, power domain information of port, information of power switch, information of power mode, information of power isolation strategy, information of level shift strategy, information of power retention strategy, incremental design information and post-processing information.
In a possible implementation manner, the obtaining the general configuration file of the current chip subsystem and the information description file for different chip subsystems includes:
acquiring a general configuration file of a current chip subsystem;
and acquiring the information description file from a target storage position corresponding to the access path according to the access path indicated in the general configuration file.
Here, by setting the access path corresponding to the information description file in the general configuration file, the information description file can be acquired more quickly according to the access path after the general configuration file is acquired, transmission of the information description file is not needed, and the acquisition process is more convenient.
In one possible embodiment, after generating the consumption intention file, the method further comprises:
And updating the power consumption intention file in response to the updating information of the user aiming at the power consumption intention file.
Here, after the power consumption intention file is generated, the power consumption intention file is updated in response to the updating information of the user aiming at the power consumption intention file, so that the flexible modification of the power consumption intention file is realized, the power consumption intention file is suitable for different chip design requirements, and the diversity and the flexibility of file generation are improved.
The following description of the effects of the apparatus, the electronic device, etc. refers to the description of the above method, and will not be repeated here.
In a second aspect, the present disclosure provides a file generating apparatus, including:
the acquisition module is used for acquiring the general configuration file of the current chip subsystem and the information description file aiming at different chip subsystems;
the analysis module is used for generating a condition constraint set for carrying out low-power-consumption design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power-consumption design stages on the power consumption intention description file; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file;
the generating module is used for filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information to generate the power consumption intention file.
In a possible implementation manner, the generating module is configured to, when generating the power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the power consumption policy information:
determining target power consumption strategy information required for low-power consumption design of the current chip subsystem from the power consumption strategy information based on the condition constraint set;
and filling a file template of a power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file.
In a possible implementation manner, the generating module is configured to, when generating the power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the target power consumption policy information:
determining template content to be filled from the file template based on the condition constraint set and the target power consumption strategy information;
filling the template content by utilizing the target power consumption strategy information;
and generating the power consumption intention file based on the filled template content.
In a possible implementation manner, the generating module is configured to, when filling the template content with the target power consumption policy information:
Performing target operation processing on the target power consumption strategy information based on the template content to generate processed target power consumption strategy information; the target operation processing comprises at least one of data format conversion, data statistics and data calculation;
and filling the template content by using the processed target power consumption strategy information.
In a possible implementation manner, the condition constraint set includes one or more of the following: global macro variables, design types, tool types, mapping relationships for module instantiations, power lists.
In a possible implementation manner, the power consumption policy information includes one or more of the following information:
statement information of power domain, integration information of power domain, power domain information of port, information of power switch, information of power mode, information of power isolation strategy, information of level shift strategy, information of power retention strategy, incremental design information and post-processing information.
In a possible implementation manner, the acquiring module is configured to, when acquiring a general configuration file of a current chip subsystem and an information description file for a different chip subsystem:
Acquiring a general configuration file of a current chip subsystem;
and acquiring the information description file from a target storage position corresponding to the access path according to the access path indicated in the general configuration file.
In one possible embodiment, after generating the consumption intention file, the apparatus further comprises: an updating module for:
and updating the power consumption intention file in response to the updating information of the user aiming at the power consumption intention file.
In a third aspect, the present disclosure provides an electronic device comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory in communication over the bus when the electronic device is running, the machine-readable instructions when executed by the processor performing the steps of the file generation method as described in the first aspect or any of the embodiments above.
In a fourth aspect, the present disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the file generation method as described in the first aspect or any of the embodiments.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below, which are incorporated in and constitute a part of the specification, these drawings showing embodiments consistent with the present disclosure and together with the description serve to illustrate the technical solutions of the present disclosure. It is to be understood that the following drawings illustrate only certain embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
FIG. 1 is a schematic flow chart of a method for generating a file according to an embodiment of the disclosure;
FIG. 2 is a flowchart illustrating a specific manner of generating a power consumption intention file in a file generating method according to an embodiment of the disclosure;
FIG. 3 is a flow chart illustrating a method for generating a file according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an architecture of a document generation device according to an embodiment of the present disclosure;
fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
In order to describe the low power architecture of the SoC, it is necessary to provide the chip with descriptions of various power domain types, power domain boundaries and power consumption scenarios, and then the power consumption intention file may be written manually by a professional engineer using a general power consumption format (Common Power Format, CPF) or a unified power consumption format (Uniform Power Format, UPF). However, in the above manner of writing the power consumption intention file by the professional engineer, writing errors are likely to occur, and the generation efficiency is low.
Meanwhile, the SoC is composed of a plurality of chip subsystems, and in the low-power design, each chip subsystem needs to be designed with low power consumption, namely, a corresponding power consumption intention file needs to be generated for each chip subsystem. Because there are multiple iteration versions of CPF and UPF, the versions of the power consumption intention files provided by each chip subsystem may have inconsistent conditions, and the difficulty of the overall low-power consumption design of the chip is increased.
In the whole chip development process, certain differences exist in the power consumption intention files in different design stages, and after the corresponding power consumption intention files are generated for each design stage, the problems of inconsistent file formats and design contents of the power consumption intention files in different design stages can occur, so that the difficulty is increased for the overall low-power consumption design of the subsequent chip.
In order to alleviate the above problems, embodiments of the present disclosure provide a method, an apparatus, an electronic device, and a storage medium for generating a file.
The present invention is directed to a method for manufacturing a semiconductor device, and a semiconductor device manufactured by the method.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
For the convenience of understanding the embodiments of the present disclosure, a detailed description will be first made of a document generating method disclosed in the embodiments of the present disclosure. The execution subject of the file generation method provided by the embodiments of the present disclosure is generally a computer device having a certain computing capability, where the computer device includes, for example: the terminal device or server or other processing device may be a User Equipment (UE), a mobile device, a User terminal, a personal digital assistant (Personal Digital Assistant, PDA), a computing device, or the like. In some possible implementations, the file generation method may be implemented by way of a processor invoking computer readable instructions stored in a memory.
Referring to fig. 1, a flowchart of a file generation method according to an embodiment of the disclosure is shown, where the method includes S101 to S103, where:
s101, acquiring a general configuration file of a current chip subsystem and an information description file aiming at different chip subsystems;
S102, generating a condition constraint set for low-power-consumption design of a current chip subsystem by analyzing a general configuration file, wherein the condition constraint set is used for indicating requirements of different low-power-consumption design stages on power consumption intention description files; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file;
s103, filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information, and generating the power consumption intention file.
In the method, the general configuration file is analyzed to generate the condition constraint set for low-power-consumption design of the current chip subsystem, wherein the condition constraint set is used for indicating the requirements of different low-power-consumption design stages on the power-consumption intention description file, and the design requirements of the power-consumption intention description file of the current chip subsystem can be determined according to the condition constraint set; the information description file can be analyzed to generate power consumption strategy information for low-power consumption design of different chip subsystems; furthermore, the file template of the power consumption intention file can be filled based on the condition constraint set and the power consumption strategy information, the power consumption intention file is automatically generated, a professional engineer is not required to write the power consumption intention file, the generation efficiency of the power consumption intention file is improved, the occurrence of writing errors caused when the professional engineer writes the power consumption intention file can be relieved, and the accuracy of the power consumption intention file is improved.
S101 to S103 are specifically described below.
For S101:
the generic configuration file may be a file capable of representing a data structure, for example, the generic configuration file may be a JSON file. The current design stage of the current chip subsystem and the type of tools which can be used by the current chip subsystem in the current design stage can be clarified through the general configuration file, and the type of the generated power consumption intention file and the like. For each design stage, a corresponding power consumption intent file needs to be designed for each chip subsystem. For example, the general configuration file may include the following information: the type of the information description file; an access path corresponding to the information description file; design type: rtl, netlist, …; tool type: icc, vcs, …; defined macro variables: m1, M2, etc.
The information description file may be a file having a spreadsheet property, for example, the information description file may be a spreadsheet, a database, a comma score file, or the like. All description information needed when designing power consumption intention files aiming at different chip subsystems in each design stage can be contained in the information description file, so that the information description file can completely describe the low power consumption strategy of the whole SoC system. For example, when the information description file is a spreadsheet, one or more of the following spreadsheets may be included in the information description file: an integrated map page, a power domain port page, a power mode page, a power isolation page, a level shift page, a power reserve page, a post-processing page, and the like of the power consumption intent.
The specific contents of the integrated map page for power consumption intent are shown in table 1 below:
TABLE 1 Integrated map pages
In practice, the SoC is formed with a plurality of chip subsystems, each of which may be divided into a plurality of modules. The integrated map page shown in table 1 includes a hierarchy, an instantiation path, a module name, a module power domain, and a current system power domain. The level may be used to describe a level of a corresponding module, the instantiated path may be path information of the module after instantiation, the module power domain may be used to describe power domain information of the module, and the current system power domain may be used to describe power domain information of the current chip subsystem.
The specific contents of the power domain page are shown in table 2 below:
TABLE 2 Power Domain page
The power domain page shown in table 2 includes power domain, power line, ground line, power domain type, parent power domain, control information, off condition, and switching unit of library.
The specific contents of the power domain port page are shown in table 3 below:
TABLE 3 Power Domain Port Page
Examples of modules, power domain 1, power domain 2, power domains 3, …, module ports, etc. are included in the power domain port page of table 3; i.e., the instance name of power domain 1, the instance name of power domain 2, etc., included under any module may be determined, and the instance name of power domain 1, the instance name of power domain 2, etc., included under any module port may be determined.
The specific contents of the power mode page are shown in table 4 below:
TABLE 4 Power mode page
The power mode page of table 4 includes a correspondence relationship between power domains and power modes, for example, a switching state of each power domain when the power mode is mode 1 may be determined; the switching state of each power domain when the power mode is mode 2, and the like.
The specific contents of the power isolation page are shown in table 5 below:
TABLE 5 Power isolation page
The power isolation page in table 5 includes isolation policy names, power generation domains, power arrival domains, locations, clamp values, isolation control, isolated port names, and isolation units of the library.
The specific contents of the level shift page are shown in table 6 below:
TABLE 6 level shift page
The level shift page in table 6 includes a level shift policy name, a power generation domain, an arrival power domain, a position, a level shift type, a level shift port name, and a level shift unit of a bank.
The specific contents of the power save page are shown in table 7 below:
TABLE 7 Power Retention page
The power reserve page in table 7 includes the power reserve policy name, the power domain for power down, the candidate power group, the registers involved, the control signals for the policy, and the units of the register reserve value for the bank.
The specific contents of the post-processing page are shown in table 8 below:
TABLE 8 post-processing page
The post-processing page of table 8 may include execution commands of custom tools, processed files, and the like.
In an alternative embodiment, obtaining a general configuration file of a current chip subsystem and an information description file for a different chip subsystem includes:
s1011, acquiring a general configuration file of a current chip subsystem;
s1012, according to the access path indicated in the general configuration file, the information description file is obtained from the target storage position corresponding to the access path.
Here, after the general configuration file of the current chip subsystem is acquired, according to the access path indicated in the general configuration file, an information description file may be acquired from the target storage location corresponding to the access path, and the information description file may be stored in the determined dynamic storage, so as to perform subsequent parsing processing.
Here, by setting the access path corresponding to the information description file in the general configuration file, the information description file can be acquired more quickly according to the access path after the general configuration file is acquired, transmission of the information description file is not needed, and the acquisition process is more convenient.
For S102:
the general configuration file can be parsed to generate a conditional constraint combination for low power design of the current chip subsystem, wherein the conditional constraint combination comprises one or more of the following: global macro variables, design types, tool types, mapping relationships for module instantiations, power lists, attached files.
In implementation, the global macro variable may be used to analyze the information description file, for example, a variable corresponding to the macro variable M1 may be set as b in the information description file, whereas a corresponding variable is x; when the macro variable M1 is found to exist after the general configuration file is analyzed, a variable b is selected; when macro variable M1 is not present, variable x is selected. The design type can be used for limiting the output of the design grammar, namely, the template content matched with the design type can be selected from the file template for filling and outputting; the tool type can be used for limiting the output of the tool grammar, namely, the template content matched with the tool type can be selected from the file template for filling and outputting.
The mapping relation of module instantiation can be used for solving the problem of inconsistent instantiation among netlists, for example, when different modules perform power consumption design, names of the same port or the same power domain may be inconsistent, and the mapping relation of module instantiation can solve the problem of inconsistent instantiation. The power list may be used to set the operating voltage and range of the power source. The additional file is used for adding some extra content to the generated power consumption intention file, and the extra content can be content designed by a user according to the chip requirement, for example, test content, time sequence content and the like can be included in the additional file. Wherein, the additional file can be designed according to the requirement.
And the information description file can be analyzed to generate power consumption strategy information for designing the low power consumption of different chip subsystems. The power consumption policy information may include power consumption policy information required by each chip subsystem. Furthermore, when determining the power consumption intention file corresponding to each chip subsystem, multiple times of analysis of the information description file are not needed, so that resource waste caused by multiple times of analysis of the information description file is avoided, and the file generation efficiency can be improved.
Wherein the power consumption policy information includes one or more of the following: statement information of power domain, integration information of power domain, power domain information of port, information of power switch, information of power mode, information of power isolation strategy, information of level shift strategy, information of power retention strategy, incremental design information and post-processing information.
In implementation, the declaration information of the power domain may include basic information such as a type of the power domain, a switching time of the power domain, and a ground line of the power domain. The integrated information of the power domain may include a connection relationship of the power domain, a power connection relationship between the module and the subsystem. The power domain information of the ports includes a power domain corresponding to each port, a power domain type, and the like. The information of the power switch may include the time the switch of the power is in an on state, the time in an off state, what power the switch inputs, what power the output is, etc. The information of the power modes may include a corresponding switch state of the power domain in each power mode. Information of the power supply isolation policy, information of the level shift policy, and information of the power supply retention policy can be seen from tables 5, 6, and 7. The incremental design information may be additional information designed by the user according to the chip requirements, as shown in table 8. The post-processing information may update the defined information for the generated power consumption intention file after the power consumption intention file is generated.
For S103:
here, a file template corresponding to the power consumption intention file may be set in advance. The power consumption intention file may be in a CPF format, a UPF format, or other description format, etc. For example, when the power consumption intention file is in the CPF format, the file template is in the CPF format. When the power consumption intention file is in a UPF format, the file template is in the UPF format. And then the file template of the power consumption intention file can be filled based on the condition constraint set and the power consumption strategy information to generate the power consumption intention file.
In an alternative embodiment, referring to fig. 2, based on the set of condition constraints and the power consumption policy information, populating a file template of the power consumption intention file, generating the power consumption intention file may include:
s201, determining target power consumption strategy information required for low-power consumption design of a current chip subsystem from power consumption strategy information based on a condition constraint set;
s202, filling a file template of the power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file.
The power consumption strategy information can comprise power consumption strategy information required by low-power consumption design of different chip subsystems in each design stage, so that when the low-power consumption design is performed on different chip subsystems in each design stage, the power consumption strategy information matched with each chip subsystem can be directly determined from the analyzed power consumption strategy information, the information description file is not required to be analyzed for multiple times, the file generation efficiency is improved, and meanwhile, resource waste caused by multiple times of analysis of the information description file can be avoided, and processing resources are saved.
Because the power consumption strategy information comprises the power consumption strategy information required by the low-power consumption design of each chip subsystem, the target power consumption strategy information corresponding to the current chip subsystem is determined from the power consumption strategy information according to the condition constraint set. For example, the current design stage corresponding to the current chip subsystem may be determined according to the condition constraint set, and then target power consumption policy information required by the current design stage of the current chip subsystem may be selected from the power consumption policy information. And filling the file template based on the condition constraint condition and the target power consumption strategy information to generate a power consumption intention file.
In an alternative embodiment, in S202, based on the condition constraint set and the target power consumption policy information, the file template of the power consumption intention file is filled, and generating the power consumption intention file may include:
s2021, determining template content to be filled from a file template based on a condition constraint set and target power consumption strategy information;
s2022, filling the template content by using the target power consumption strategy information;
s2023 generates a power consumption intention file based on the filled template content.
In the method, the file template can comprise a plurality of template contents, and each template content corresponds to different power consumption strategy information and/or condition constraint combination, so that the template content to be filled can be determined from the file template based on the condition constraint set and the target power consumption strategy information; filling the template content by utilizing the target power consumption strategy information; and generating a power consumption intention file based on the filled template content, wherein the power consumption intention file is simpler and more convenient in generation process and higher in efficiency.
Here, the file template includes content sets corresponding to the power consumption policy information, and each content set corresponding to the power consumption policy information includes template content corresponding to different design types, different tool types, or the like. Therefore, the template content matched with the condition constraint set and the target power consumption strategy information can be selected from the file template and used as the template content to be filled. For example, the first template content may correspond to a tool type of the icc under the power domain, the second template content may correspond to a tool type of the vcs under the power domain, the third template content may correspond to a tool type of the icc under the power switch, the fourth template content may correspond to a tool type of the vcs under the power switch, and further the power domain is included in the target power consumption policy information, and when the tool type of the icc is included in the condition constraint set, the first template content may be used as the template content to be filled.
In implementation, the template content can be filled with the target power consumption policy information, for example, the module name in the template content is: xxx, the module name in the target power consumption policy information is: and filling the first module into the determined template content to generate the filled template content.
In an alternative embodiment, in S2022, filling the template content with the target power consumption policy information may include:
performing target operation processing on target power consumption strategy information based on template content, and generating processed target power consumption strategy information; the target operation processing comprises at least one of data format conversion, data statistics and data calculation;
and step two, filling the template content by using the processed target power consumption strategy information.
Here, the target power consumption policy information may be subjected to target operation processing based on the template content, for example, when the template content is xx-xx, the target power consumption policy information may be subjected to data format conversion, converted into xx-xx format, and then the processed target power consumption policy information is filled into the value template content to generate the filled template content. Alternatively, the template content includes: a maximum value; a conventional value; and the minimum value can carry out data statistics on the target power consumption strategy information, and the maximum value, the conventional value and the minimum value of the voltage are determined, so that the maximum value, the conventional value and the minimum value are filled into the template content, and the filled template content is generated. Or, data calculation may be performed on the target power consumption policy information according to the template content, for example, the calculation determines the input and output of the power domain, and the template content is filled according to the calculation result.
And finally, generating a power consumption intention file according to the filled template content. For example, the filled template content may be stored in an initialization file to generate a power consumption intention file.
In an alternative embodiment, after generating the consumption intention file, the method further comprises: and updating the power consumption intention file in response to the updating information of the user aiming at the power consumption intention file.
Here, the user may design corresponding update information for the power consumption intention file, for example, the update information may be information that refines the power consumption intention file, so the power consumption intention file may be updated in response to the update information for the power consumption intention file.
Here, after the power consumption intention file is generated, the power consumption intention file is updated in response to the updating information of the user aiming at the power consumption intention file, so that the flexible modification of the power consumption intention file is realized, the power consumption intention file is suitable for different chip design requirements, and the diversity and the flexibility of file generation are improved.
Referring to fig. 3, a general configuration file (i.e., the configuration file in fig. 3) and an information description file (i.e., the electronic data table in fig. 3) may be acquired, and the general configuration file and the information description file are parsed by using an edited parsing tool (i.e., the program in fig. 3) to obtain a condition constraint set and power consumption policy information; and filling the file template based on the condition constraint set and the power consumption strategy information to generate a power consumption intention file.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
Based on the same concept, the embodiment of the present disclosure further provides a file generating apparatus, which is shown in fig. 4, and is an architecture schematic diagram of the file generating apparatus provided in the embodiment of the present disclosure, including an obtaining module 401, an analyzing module 402, and a generating module 403, and specifically:
an obtaining module 401, configured to obtain a general configuration file of a current chip subsystem and an information description file for different chip subsystems;
the parsing module 402 is configured to generate a condition constraint set for performing low-power design on the current chip subsystem by parsing the general configuration file, where the condition constraint set is used to indicate requirements of different low-power design stages on power consumption intention description files; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file;
a generating module 403, configured to populate a file template of the power consumption intention file based on the condition constraint set and the power consumption policy information, and generate the power consumption intention file.
In a possible implementation manner, the generating module 403 is configured to, when generating the power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the power consumption policy information:
determining target power consumption strategy information required for low-power consumption design of the current chip subsystem from the power consumption strategy information based on the condition constraint set;
and filling a file template of a power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file.
In a possible implementation manner, the generating module 403 is configured to, when generating the power consumption intention file by filling a file template of the power consumption intention file based on the condition constraint set and the target power consumption policy information:
determining template content to be filled from the file template based on the condition constraint set and the target power consumption strategy information;
filling the template content by utilizing the target power consumption strategy information;
and generating the power consumption intention file based on the filled template content.
In a possible implementation manner, the generating module 403 is configured to, when filling the template content with the target power consumption policy information:
Performing target operation processing on the target power consumption strategy information based on the template content to generate processed target power consumption strategy information; the target operation processing comprises at least one of data format conversion, data statistics and data calculation;
and filling the template content by using the processed target power consumption strategy information.
In a possible implementation manner, the condition constraint set includes one or more of the following: global macro variables, design types, tool types, mapping relationships for module instantiations, power lists.
In a possible implementation manner, the power consumption policy information includes one or more of the following information:
statement information of power domain, integration information of power domain, power domain information of port, information of power switch, information of power mode, information of power isolation strategy, information of level shift strategy, information of power retention strategy, incremental design information and post-processing information.
In a possible implementation manner, the obtaining module 401 is configured to, when obtaining a general configuration file of a current chip subsystem and an information description file for a different chip subsystem:
Acquiring a general configuration file of a current chip subsystem;
and acquiring the information description file from a target storage position corresponding to the access path according to the access path indicated in the general configuration file.
In one possible embodiment, after generating the consumption intention file, the apparatus further comprises: an update module 404 for:
and updating the power consumption intention file in response to the updating information of the user aiming at the power consumption intention file.
In some embodiments, the functions or templates included in the apparatus provided by the embodiments of the present disclosure may be used to perform the methods described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
Based on the same technical concept, the embodiment of the disclosure also provides electronic equipment. Referring to fig. 5, a schematic structural diagram of an electronic device according to an embodiment of the disclosure includes a processor 501, a memory 502, and a bus 503. The memory 502 is configured to store execution instructions, including a memory 5021 and an external memory 5022; the memory 5021 is also referred to as an internal memory, and is used for temporarily storing operation data in the processor 501 and data exchanged with an external memory 5022 such as a hard disk, the processor 501 exchanges data with the external memory 5022 through the memory 5021, and when the electronic device 500 is running, the processor 501 and the memory 502 communicate with each other through the bus 503, so that the processor 501 executes the following instructions:
Acquiring a general configuration file of a current chip subsystem and an information description file aiming at different chip subsystems;
generating a condition constraint set for carrying out low-power design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power design stages on power consumption intention description files; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file;
and filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information, and generating the power consumption intention file.
Furthermore, the embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, which when executed by a processor performs the steps of the file generation method described in the above-described method embodiments. Wherein the storage medium may be a volatile or nonvolatile computer readable storage medium.
The embodiments of the present disclosure further provide a computer program product, where the computer program product carries a program code, where instructions included in the program code may be used to perform steps of a file generating method described in the foregoing method embodiments, and specifically reference may be made to the foregoing method embodiments, which are not described herein in detail.
Wherein the above-mentioned computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A document generation method, comprising:
acquiring a general configuration file of a current chip subsystem and an information description file aiming at different chip subsystems;
generating a condition constraint set for carrying out low-power design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power design stages on the power consumption intention description file and comprises at least one constraint condition information required by the different low-power design stages on the power consumption intention description file; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file; the power consumption strategy information comprises power consumption strategy information required by low-power consumption design of different chip subsystems in each design stage;
Filling a file template of a power consumption intention file based on the condition constraint set and the power consumption strategy information to generate the power consumption intention file;
the file template of the power consumption intention file is filled based on the condition constraint set and the power consumption strategy information, and the power consumption intention file is generated, which comprises the following steps: determining target power consumption strategy information required for low-power consumption design of the current chip subsystem from the power consumption strategy information based on the condition constraint set; filling a file template of a power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file;
the file template of the power consumption intention file is filled based on the condition constraint set and the target power consumption strategy information, and the power consumption intention file is generated, which comprises the following steps: determining template content to be filled from the file template based on the condition constraint set and the target power consumption strategy information; filling the template content by utilizing the target power consumption strategy information; and generating the power consumption intention file based on the filled template content.
2. The method of claim 1, wherein populating the template content with the target power consumption policy information comprises:
Performing target operation processing on the target power consumption strategy information based on the template content to generate processed target power consumption strategy information; the target operation processing comprises at least one of data format conversion, data statistics and data calculation;
and filling the template content by using the processed target power consumption strategy information.
3. The method according to claim 1 or 2, wherein the set of conditional constraints comprises one or more of:
global macro variables, design types, tool types, mapping relationships for module instantiations, power lists.
4. The method of claim 1 or 2, wherein the power consumption policy information comprises one or more of the following:
statement information of power domain, integration information of power domain, power domain information of port, information of power switch, information of power mode, information of power isolation strategy, information of level shift strategy, information of power retention strategy, incremental design information and post-processing information.
5. The method according to claim 1 or 2, wherein the obtaining a generic profile of a current chip subsystem and an information profile for a different chip subsystem comprises:
Acquiring a general configuration file of a current chip subsystem;
and acquiring the information description file from a target storage position corresponding to the access path according to the access path indicated in the general configuration file.
6. The method according to claim 1 or 2, wherein after generating the consumption intention file, the method further comprises:
and updating the power consumption intention file in response to the updating information of the user aiming at the power consumption intention file.
7. A document generating apparatus, comprising:
the acquisition module is used for acquiring the general configuration file of the current chip subsystem and the information description file aiming at different chip subsystems;
the analysis module is used for generating a condition constraint set for carrying out low-power-consumption design on the current chip subsystem by analyzing the general configuration file, wherein the condition constraint set is used for indicating the requirements of different low-power-consumption design stages on the power-consumption intention description file and comprises at least one constraint condition information required by the different low-power-consumption design stages on the power-consumption intention description file; generating power consumption strategy information for designing low power consumption of different chip subsystems by analyzing the information description file; the power consumption strategy information comprises power consumption strategy information required by low-power consumption design of different chip subsystems in each design stage;
The generating module is used for filling a file template of the power consumption intention file based on the condition constraint set and the power consumption strategy information to generate the power consumption intention file;
the generating module is used for, when a file template of the power consumption intention file is filled in based on the condition constraint set and the power consumption strategy information, generating the power consumption intention file: determining target power consumption strategy information required for low-power consumption design of the current chip subsystem from the power consumption strategy information based on the condition constraint set; filling a file template of a power consumption intention file based on the condition constraint set and the target power consumption strategy information, and generating the power consumption intention file;
the generating module is used for, when a file template of a power consumption intention file is filled in based on the condition constraint set and the target power consumption strategy information, generating the power consumption intention file: determining template content to be filled from the file template based on the condition constraint set and the target power consumption strategy information; filling the template content by utilizing the target power consumption strategy information; and generating the power consumption intention file based on the filled template content.
8. An electronic device, comprising: a processor, a memory and a bus, said memory storing machine readable instructions executable by said processor, said processor and said memory communicating over the bus when the electronic device is running, said machine readable instructions when executed by said processor performing the steps of the file generation method according to any of claims 1 to 6.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the file generation method according to any of claims 1 to 6.
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| CN117521569A (en) * | 2023-12-07 | 2024-02-06 | 摩尔线程智能科技(北京)有限责任公司 | Chip function simulation method and device, electronic equipment and storage medium |
| CN117454809B (en) * | 2023-12-26 | 2024-04-16 | 奇捷科技(深圳)有限公司 | Low-power-consumption circuit design change processing method, system and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108121842A (en) * | 2016-11-30 | 2018-06-05 | 深圳市中兴微电子技术有限公司 | The verification method and device of the low energy consumption operation mode of multiprocessor system chip |
| US10503243B1 (en) * | 2016-12-21 | 2019-12-10 | Cadence Design Systems, Inc. | Instrumenting low power coverage counters in emulation |
-
2021
- 2021-06-25 CN CN202110709512.5A patent/CN113408222B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108121842A (en) * | 2016-11-30 | 2018-06-05 | 深圳市中兴微电子技术有限公司 | The verification method and device of the low energy consumption operation mode of multiprocessor system chip |
| US10503243B1 (en) * | 2016-12-21 | 2019-12-10 | Cadence Design Systems, Inc. | Instrumenting low power coverage counters in emulation |
Non-Patent Citations (1)
| Title |
|---|
| "基于UPF的低功耗验证中的关电电压域边界检查的自动化实现";陈世娟;中国优秀硕士学位论文全文数据库（信息科技辑）(第2018年06期);全文 * |
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